IDT74LVCH162374A
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT
IDT74LVCH162374A
EDGE TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O, BUS-HOLD
DESCRIPTION:
FEATURES:
The LVCH162374A 16-bit edge-triggered D-type flip-flop is built using
advanced dual metal CMOS technology. This high-speed, low-power
register is ideal for use as a buffer register for data synchronization and
storage. The output enable (OE) and clock (CLK) controls are organized
to operate each device as two 8-bit registers or one 16-bit register with
common clock. Flow-through organization of signal pins simplifies layout.
All inputs are designed with hysteresis for improved noise margin.
All pins of the LVCH162374A can be driven from either 3.3V or 5V
devices. This feature allows the use of this device as a translator in a mixed
3.3V/5V supply system.
The LVCH162374A has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been developed to drive ±12mA at the designated thresholds.
The LVCH162374A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
μ W typ. static)
• CMOS power levels (0.4μ
• All inputs, outputs, and I/O are 5V tolerant
• Available in TSSOP package
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
1OE
1CLK
1D1
1
48
47
24
2CLK
25
2D1
1D
C1
2OE
2
36
1D
13
C1
1Q1
2Q1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
JANUARY 2015
1
© 2015 Integrated Device Technology, Inc.
DSC-4678/5
IDT74LVCH162374A
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
Description
Max
VTERM
Terminal Voltage with Respect to GND
–0.5 to +6.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–50 to +50
mA
IIK
IOK
Continuous Clamp Current,
VI < 0 or VO < 0
–50
mA
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
1OE
1
48
1CLK
1Q1
2
47
1D1
1Q2
3
46
1D2
GND
4
45
GND
1Q3
5
44
1D3
1Q4
6
VCC
7
42
VCC
1Q5
8
41
1D5
1Q6
9
40
1D6
GND
10
39
GND
1Q7
11
38
1D7
1Q8
12
37
1D8
2Q1
13
36
2D1
2Q2
14
35
2D2
GND
15
34
GND
2Q3
16
33
2D3
2Q4
17
32
2D4
VCC
18
31
VCC
2Q5
19
30
2D5
2Q6
20
29
2D6
xCLK
Clock Inputs
xQx
3-State Outputs
xOE
3-State Output Enable Inputs (Active LOW)
43
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1D4
GND
21
28
GND
2Q7
22
27
2D7
2Q8
23
26
2D8
2OE
24
25
2CLK
Unit
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Symbol
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
COUT
Output Capacitance
VOUT = 0V
6.5
8
pF
CI/O
I/O Port Capacitance
VIN = 0V
6.5
8
pF
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
xDx
Description
Data Inputs(1)
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
FUNCTION TABLE
(EACH FLIP-FLOP)(1)
Inputs
TSSOP
TOP VIEW
Outputs
xOE
xCLK
xDx
xQx
L
↑
H
H
L
↑
L
L
L
H or L
X
Q(2)
H
X
X
Z
NOTES:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
2. Output level before the indicated steady-state input conditions were established.
2
IDT74LVCH162374A
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
Symbol
VIH
VIL
Min.
Typ.(1)
Max.
Unit
VCC = 2.3V to 2.7V
1.7
—
—
V
VCC = 2.7V to 3.6V
2
—
—
VCC = 2.3V to 2.7V
—
—
0.7
VCC = 2.7V to 3.6V
—
—
0.8
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Test Conditions
V
Input Leakage Current
VCC = 3.6V
VI = 0 to 5.5V
—
—
±5
μA
IOZH
High Impedance Output Current
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
μA
IOZL
(3-State Output pins)
IOFF
Input/Output Power Off Leakage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
±50
μA
VIK
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
—
–0.7
–1.2
V
VH
ICCL
ICCH
ICCZ
ΔICC
Input Hysteresis
Quiescent Power Supply Current
VCC = 3.3V
VCC = 3.6V
VIN = GND or VCC
—
—
100
—
—
10
mV
μA
3.6 ≤ VIN ≤ 5.5V(2)
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
—
—
10
500
μA
Min.
Typ.(2)
Max.
Unit
μA
IIH
IIL
Quiescent Power Supply Current
Variation
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol
IBHH
Parameter(1)
Bus-Hold Input Sustain Current
Test Conditions
VCC = 3V
VI = 2V
IBHL
IBHH
Bus-Hold Input Sustain Current
VCC = 2.3V
IBHL
IBHHO
Bus-Hold Input Overdrive Current
VCC = 3.6V
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
– 75
—
—
VI = 0.8V
75
—
—
VI = 1.7V
—
—
—
VI = 0.7V
—
—
—
VI = 0 to 3.6V
—
—
±500
μA
μA
IDT74LVCH162374A
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
Test Conditions(1)
Parameter
Output HIGH Voltage
Unit
V
IOH = – 0.1mA
VCC – 0.2
—
VCC = 2.3V
IOH = – 4mA
1.9
—
IOH = – 6mA
1.7
—
IOH = – 4mA
2.2
—
IOH = – 8mA
2
—
IOH = – 6mA
2.4
—
IOH = – 12mA
2
—
VCC = 2.3V to 3.6V
IOL = 0.1mA
—
0.2
VCC = 2.3V
IOL = 4mA
—
0.4
IOL = 6mA
—
0.55
IOL = 4mA
—
0.4
IOL = 8mA
—
0.6
IOL = 6mA
—
0.55
IOL = 12mA
—
0.8
VCC = 3V
Output LOW Voltage
Max.
VCC = 2.3V to 3.6V
VCC = 2.7V
VOL
Min.
VCC = 2.7V
VCC = 3V
V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
Parameter
CPD
Power Dissipation Capacitance per Flip-Flop Outputs enabled
CPD
Power Dissipation Capacitance per Flip-Flop Outputs disabled
Test Conditions
Typical
Unit
CL = 0pF, f = 10Mhz
—
—
pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V
Symbol
Parameter
VCC = 3.3V ± 0.3V
Min.
Max.
Min.
Max.
Unit
2
6.5
2
6.2
ns
1.5
6.3
1.5
6.1
ns
1.5
6.2
1.5
6
ns
tPLH
Propagation Delay
tPHL
xCLK to xQx
tPZH
Output Enable Time
tPZL
xOE to xQx
tPHZ
Output Disable Time
tPLZ
xOE to xQx
tSU
Set-up Time HIGH or LOW, xDx before xCLK
2.5
—
2.5
—
ns
tH
Hold Time HIGH or LOW, xDx after xCLK
1.5
—
1.5
—
ns
tW
xCLK Pulse Width HIGH or LOW
3
—
3
—
ns
—
—
—
500
ps
tSK(o)
Output Skew(2)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVCH162374A
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
VLOAD
6
VCC(2)= 2.5V±0.2V
Unit
2 x Vcc
V
6
VIH
2.7
2.7
Vcc
V
VT
1.5
1.5
Vcc / 2
V
VLZ
300
300
150
mV
VHZ
300
300
150
mV
CL
50
50
30
pF
VIH
VT
0V
VOH
VT
VOL
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
tPLH
tPHL
OUTPUT
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
LVC Link
Propagation Delay
Pulse (1, 2)
Generator
tPZL
GND
500
VOUT
OUTPUT
SWITCH
NORMALLY CLOSED
LOW
tPZH
OUTPUT SWITCH
NORMALLY
OPEN
HIGH
D.U.T.
500
RT
CL
Test Circuit for All Outputs
VIH
VT
0V
CONTROL
INPUT
Open
VIN
DISABLE
ENABLE
VLOAD
VCC
tPLZ
VLOAD/2
VT
VLOAD/2
VLZ
VOL
tPHZ
VOH
VHZ
0V
VT
0V
LVC Link
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
DATA
INPUT
SWITCH POSITION
Switch
Open Drain
Disable Low
Enable Low
VLOAD
ASYNCHRONOUS
CONTROL
Disable High
Enable High
GND
SYNCHRONOUS
CONTROL
All Other Tests
Open
OUTPUT 1
tSK (x)
tSK (x)
tPLH2
tH
Set-up, Hold, and Release Times
VOH
VT
VOL
VT
tW
HIGH-LOW-HIGH
PULSE
VT
LVC Link
tPHL2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
tSU
LOW-HIGH-LOW
PULSE
VOH
VT
VOL
OUTPUT 2
tREM
LVC Link
VIH
VT
0V
tPHL1
tPLH1
tH
TIMING
INPUT
Test
INPUT
tSU
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
LVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVCH162374A
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
X
LVC
XX
Bus-Hold
Temp. Range
XX
Family
XXXX
XX
Device Type Package
X
Blank
8
Tube or Tray
Tape and Reel
PAG
Thin Shrink Small Outline Package - Green
374A
16-Bit Edge Triggered D-Type Flip-Flop
162
Double-Density with Resistors, ±12mA
H
Bus-hold
74
-40°C to +85°C
Datasheet Document History
01/29/2015
Pg. 1,2,6
Updated the ordering information by removing the "IDT" notation, non RoHS part, SSOP package and
by adding Tape and Reel information.
6
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