74LVCH16374APVG8

IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT IDT74LVCH16374A EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, 5V TOLERANT I/O AND BUS-HOLD DESCRIPTION FEATURES: The LVCH16374A 16-bit edge-triggered D-type register is built using advanced dual metal CMOS technology. This high-speed, low-power register is ideal for use as a buffer register for data synchronization and storage. The Output Enable (OE) and clock (CLK) controls are organized to operate each device as two 8-bit registers or one 16-bit register with common clock. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. All pins of the LVCH16374A can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVCH16374A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The LVCH16374A has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range μ W typ. static) • CMOS power levels (0.4μ • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in SSOP and TSSOP packages DRIVE FEATURES: • High Output Drivers: ±24mA • Reduced system switching noise APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 1OE 1CLK 1 48 2OE 24 2CLK 25 C1 1D1 47 1D C1 2 1Q1 2D1 36 13 1D 2Q1 TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS IDT and the IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 1 © 2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. OCTOBER 2015 DSC-4643/5 IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V 1OE 1 48 1CLK TSTG Storage Temperature –65 to +150 °C 1Q1 2 47 1D1 IOUT DC Output Current –50 to +50 mA 1Q2 3 46 1D2 IIK IOK Continuous Clamp Current, VI < 0 or VO < 0 –50 mA GND 4 45 GND mA 5 44 1D3 Continuous Current through each VCC or GND ±100 1Q3 ICC ISS 1Q4 6 VCC 7 42 VCC 1Q5 8 41 1D5 1Q6 9 40 1D6 GND 10 39 GND 1Q7 11 38 1D7 1Q8 12 37 1D8 2Q1 13 36 2D1 2Q2 14 35 2D2 GND 15 34 GND 2Q3 16 33 2D3 2Q4 17 32 2D4 VCC 18 31 VCC 2Q5 19 30 2D5 2Q6 20 29 2D6 GND 21 28 GND xDx Data Inputs 2Q7 22 27 2D7 xCLK Clock Inputs 2Q8 23 26 2D8 xOE Output Enable Inputs (Active LOW) 2CLK xQx 3-State Outputs 2OE 24 43 25 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1D4 CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol Conditions Typ. Max. CIN Input Capacitance VIN = 0V 4.5 6 Unit pF COUT Output Capacitance VOUT = 0V 6.5 8 pF CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names Description (1) NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. SSOP / TSSOP TOP VIEW FUNCTION TABLE (EACH FLIP-FLOP)(1) Inputs Outputs xDx xCLK xOE xQx H ↑ L H L ↑ L L X H or L L Q(2) X X H Z NOTES: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level Z = High-Impedance ↑ = LOW-to-HIGH transition 2. Output level before the indicated steady-state input conditions were established. 2 IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 μA IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 μA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 μA VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ΔICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 — — 10 mV μA 3.6 ≤ VIN ≤ 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND — — — — 10 500 μA Min. Typ.(2) Max. Unit – 75 — — μA VI = 0.8V 75 — — VI = 1.7V — — — IIH IIL Quiescent Power Supply Current Variation NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Test Conditions Bus-Hold Input Sustain Current VCC = 3V Bus-Hold Input Sustain Current VCC = 2.3V Bus-Hold Input Overdrive Current VCC = 3.6V VI = 2V IBHL IBHH IBHL IBHHO IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3 VI = 0.7V — — — VI = 0 to 3.6V — — ±500 μA μA IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL Test Conditions(1) Parameter Output HIGH Voltage Output LOW Voltage Min. Max. Unit V VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — VCC = 2.7V 2.2 — VCC = 3V 2.4 — VCC = 3V IOH = – 24mA 2.2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance per Flip-Flop Outputs enabled CPD Power Dissipation Capacitance per Flip-Flop Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical Unit 58 pF 24 SWITCHING CHARACTERISTICS(1) VCC = 2.7V Symbol Parameter fMAX tPLH Propagation Delay tPHL xCLK to xQx tPZH Output Enable Time VCC = 3.3V ± 0.3V Min. Max. Min. Max. Unit 150 — 150 — MHz — 4.9 1.5 4.5 ns — 5.3 1.5 4.6 ns — 6.1 1.5 5.5 ns tPZL xOE to xQx tPHZ Output Disable Time tPLZ xOE to xQx tSU Set-up Time HIGH or LOW, data before CLK↑ 1.9 — 1.9 — ns tH Hold Time HIGH or LOW, data after CLK↑ 1.1 — 1.1 — ns Pulse duration, CLK HIGH or LOW 3.3 — 3.3 — ns Output Skew(2) — — — 500 ps tW tSK(o) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VLOAD 6 VCC(2)= 2.5V±0.2V Unit 2 x Vcc V 6 VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF Pulse (1, 2) Generator LVC Link DISABLE ENABLE VIH VT 0V CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH D.U.T. 500 CL Test Circuit for All Outputs tPHL Propagation Delay VOUT RT tPLH VIH VT 0V GND 500 tPHL OPPOSITE PHASE INPUT TRANSITION Open VIN tPLH OUTPUT VLOAD VCC VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION tPLZ VLOAD/2 VT VLOAD/2 VLZ VOL tPHZ VOH VHZ 0V VT 0V LVC Link LVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. DATA INPUT SWITCH POSITION tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V tH TIMING INPUT Test Switch Open Drain Disable Low Enable Low VLOAD ASYNCHRONOUS CONTROL Disable High Enable High GND SYNCHRONOUS CONTROL All Other Tests Open tREM tSU tH LVC Link Set-up, Hold, and Release Times INPUT OUTPUT 1 VIH VT 0V tPHL1 tPLH1 tSK (x) tSK (x) LOW-HIGH-LOW PULSE VOH VT VOL tW HIGH-LOW-HIGH PULSE VOH VT VOL OUTPUT 2 tPLH2 VT LVC Link Pulse Width tPHL2 tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) VT LVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION X LVC XX Bus-Hold Temp. Range XX Family XX XXXX Device Type Package X Blank 8 Tube or Tray Tape and Reel PVG PAG Shrink Small Outline Package - Green Thin Shrink Small Outline Package - Green 374A 16-Bit Edge-Triggered D-Type Flip-Flop with 3-State Outputs 16 Double-Density, ±24mA H Bus-hold 74 -40°C to +85°C DATASHEET DOCUMENT HISTORY 10/20/2015 Pg. 6 Updated the ordering information by removing non RoHS parts and adding Tape and Reel information. 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