7630

To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 7600 SERIES 7630 Group User’s Manual k eep safety first in your circuit designs ! q Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials q These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. q Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. q All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. q Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. q The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. q If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of JAPAN and/or the country of destination is prohibited. q Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. REVISION DESCRIPTION LIST REVISION SEP-98 JAN-99 DATE NEW 09-98 01-99 1-13 1-14 1-21 1-28 1-38 1-41 3-4 1-13 1-14 1-21 1-28 1-38 1-41 3-4 PAGE OLD 7630 GROUP USER’S MANUAL MODIFICATIONS First Edition "CAN controller" is replaced by "CAN module" in whole documents. Schematics (1) is modified. Schematics (8) and (11) are corrected. Replaced:"PUPDJ" with "PUP4J". Replaced:"URXD" with "SOUT" . Replaced:"URXD" with "SIN". Fig.41 is modified. Replaced:"FFFBH" with "FFFB16". Replaced:"FFFAH" with "FFFA16". Values changed:Iih (35,113) to (20,200) and Iih (-122,-70) to (-200,-20);typical values are removed. (1/1) Preface This user’s manual describes Mitsubishi’s CMOS 8-bit microcomputers 7630 Group. After reading this manual, the user should have a through knowledge of the functions and features of the 7630 Group, and should be able to fully utilize the product. The manual starts with specifications and ends with application examples. For details of software, refer to the “SERIES MELPS 7600 USER’S MANUAL.” For details of development support tools, refer to the “DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS” data book. BEFORE USING THIS USER’S MANUAL This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. Chapter 3 also includes necessary information for systems denelopment. Be sure to refer to this chapter. 1. Organization q C HAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. q C HAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. q C HAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer, electric characteristics, a list of registers, the masking confirmation (mask ROM version), and mark specifications which are to be submitted when ordering. 2. Structure of register The figure of each register structure describes its functions, contents at reset, and attributes as follows : (Note 2) Bit attributes Bits CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 (Note 1) Contents immediately after reset release CPU mode register (CPUM) [Address : 000016] B 0 1 2 Stack page selection bit Name Processor mode bits b1 b0 Function 0 0 : Single chip mode 0 1 : Not available 1 0 : Not available 1 1 : Not available 0 : In page 0 1 : In page 1 At reset R W 0 0 1 0 0 0 1 0 3 Not used (“0” when read, don't write “1”.) 4 5 6 Internal clock selection bit 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode) 7 Not used (“0” when read, don't write “1”.) : Bit in which nothing is arranged Note 1: Contents immediately after reset release 0 •••••• “0” at reset release 1 •••••• “1” at reset release undefined •••••• Undefined at reset release V •••••• Contents determined by option at reset release Note 2: Bit attributes •••••• The attributes of control register bits are classified into 3 types : read-only, write-only and read and write. In the figure, these attributes are represented as follows: R •••••• Read W •••••• Write •••••• Read enabled •••••• Write enabled •••••• Read disabled •••••• Write disabled T able of contents Table of contents CHAPTER 1. HARDWARE DESCRIPTION .......................................................................................................................... 1-2 FEATURES ................................................................................................................................ 1-2 APPLICATION ........................................................................................................................... 1-2 PIN CONFIGURATION ............................................................................................................ 1-2 FUNCTIONAL BLOCK DIAGRAM .......................................................................................... 1-3 PIN DESCRIPTION .................................................................................................................. 1-4 PART NUMBERING ................................................................................................................. 1-5 GROUP EXPANSION .............................................................................................................. 1-6 Memory Type .................................................................................................................... 1-6 Memory Size ..................................................................................................................... 1-6 Package ............................................................................................................................. 1-6 FUNCTIONAL DESCRIPTION ................................................................................................ 1-7 Central Processing Unit (CPU) ...................................................................................... 1-7 Memory ............................................................................................................................ 1-11 I/O Ports .......................................................................................................................... 1-13 Interrupts ......................................................................................................................... 1-17 Key-on Wake-up ............................................................................................................. 1-21 Timers .............................................................................................................................. 1-22 Serial I/Os ....................................................................................................................... 1-28 CAN Module .................................................................................................................... 1-33 A-D Converter ................................................................................................................. 1-38 Watchdog Timer ............................................................................................................. 1-40 Reset Circuit ................................................................................................................... 1-41 Clock Generating Circuit ............................................................................................... 1-43 Data Required for Mask Orders ................................................................................... 1-44 Absolute Maximum Rating ............................................................................................ 1-45 Electrical Characteristics ............................................................................................... 1-46 A-D Converter Characteristics ...................................................................................... 1-47 Timing Requirements ..................................................................................................... 1-48 Switching Characteristics .............................................................................................. 1-49 Timing Diagram .............................................................................................................. 1-50 CHAPTER 2. APPLICATION 2.1 I/O ports ................................................................................................................................... 2-2 2.1.1 Memory map of I/O ports ............................................................................................. 2-2 2.1.2 Related registers ............................................................................................................ 2-3 2.1.3 Overvoltage conditions at digital input ports .............................................................. 2-7 2.1.4 Handling examples of unused pins ............................................................................. 2-8 2.2 Interrupts ................................................................................................................................. 2-9 2.2.1 Memory map of interrupt related registers ................................................................. 2-9 2.2.2 Related registers .......................................................................................................... 2-10 2.2.3 Interrupt setting method .............................................................................................. 2-14 2.2.4 Key-on wake-up interrupt ............................................................................................ 2-16 2.3 Timers .................................................................................................................................... 2-18 2.3.1 Memory map of timer .................................................................................................. 2-18 2.3.2 Related registers .......................................................................................................... 2-19 2.3.3 Timer application examples ........................................................................................ 2-22 7630 GROUP USER’S MANUAL i T able of contents 2.4 Controller Area Network (CAN) module ......................................................................... 2-34 2.4.1 Description .................................................................................................................... 2-34 2.4.2 Special function register map ..................................................................................... 2-35 2.4.3 Related registers .......................................................................................................... 2-37 2.4.4 Operational modes ....................................................................................................... 2-48 2.4.5 Module initialization ...................................................................................................... 2-50 2.4.6 Module reset ................................................................................................................. 2-53 2.4.7 Acceptance filtering ...................................................................................................... 2-54 2.4.8 Message reception ....................................................................................................... 2-55 2.4.9 Message transmission ................................................................................................. 2-60 2.4.10 Abort transmission ..................................................................................................... 2-62 2.4.11 CAN interrupts ............................................................................................................ 2-65 2.4.12 Error condition ............................................................................................................ 2-65 2.4.13 Wake-up via CAN ...................................................................................................... 2-66 2.5 Serial I/O ................................................................................................................................ 2-67 2.5.1 Memory map of serial I/O ........................................................................................... 2-67 2.5.2 Related registers .......................................................................................................... 2-68 2.5.3 Serial I/O connection examples ................................................................................. 2-72 2.5.4 Setting of serial I/O transfer data format ................................................................. 2-74 2.5.5 Serial I/O application examples ................................................................................. 2-75 2.6 A-D converter ....................................................................................................................... 2-90 2.6.1 Memory map of A-D conversion ................................................................................ 2-90 2.6.2 Related registers .......................................................................................................... 2-91 2.6.3 A-D conversion application example ......................................................................... 2-92 2.6.4 Conversion time ............................................................................................................ 2-93 2.6.5 Notes on use ................................................................................................................ 2-93 2.7 Watchdog timer .................................................................................................................... 2-94 2.7.1 Related register ............................................................................................................ 2-94 2.7.2 Watchdog timer cycle .................................................................................................. 2-95 2.7.3 Watchdog timer procedure .......................................................................................... 2-95 2.8 Reset ....................................................................................................................................... 2-96 2.9 Oscillation Circuit ................................................................................................................ 2-97 2.9.1 Memory map of oscillation circuit related registers ................................................ 2-97 2.9.2 Related registers .......................................................................................................... 2-98 2.9.3 Application examples ................................................................................................... 2-99 2.10 Development support tools (M37630T-RFS) .............................................................. 2-100 2.11 Built-in PROM version .................................................................................................... 2-101 2.11.1 Product expansion ................................................................................................... 2-101 2.11.2 Pin configuration ...................................................................................................... 2-102 2.11.3 Programming adapter .............................................................................................. 2-103 2.11.4 Notes on use ............................................................................................................ 2-104 CHAPTER 3. APPENDIX 3.1 Electrical characteristics ..................................................................................................... 3-2 3.1.1 Absolute maximum ratings ............................................................................................ 3-2 3.1.2 Recommended operating conditions ............................................................................ 3-3 3.1.3 Electrical characteristics ................................................................................................ 3-4 3.1.4 A-D converter characteristics ....................................................................................... 3-5 3.1.5 Timing requirements ...................................................................................................... 3-5 3.1.6 Switching characteristics ............................................................................................... 3-6 3.2 Standard characteristics ...................................................................................................... 3-8 3.2.1 Power source current standard characteristics .......................................................... 3-8 ii 7630 GROUP USER’S MANUAL T able of contents 3.2.2 Output current standard characteristics .................................................................... 3-10 3.2.3 Input current standard characteristics ....................................................................... 3-11 3.2.4 A-D conversion standard characteristics ................................................................... 3-12 3.3 Notes on use ........................................................................................................................ 3-13 3.3.1 Notes on interrupts ...................................................................................................... 3-13 3.3.2 Notes on A-D converter .............................................................................................. 3-13 ____________ 3.3.3 Notes on RESET pin ................................................................................................... 3-14 3.3.4 Notes on input and output pins ................................................................................. 3-14 3.3.5 Notes on programming ................................................................................................ 3-15 3.4 Countermeasures against noise ...................................................................................... 3-17 3.4.1 Shortest wiring length .................................................................................................. 3-17 3.4.2 Connection of a bypass capacitor across the V SS l ine and the V CC l ine ........... 3-18 3.4.3 Wiring to analog input pins ........................................................................................ 3-18 3.4.4 Consideration for oscillator ......................................................................................... 3-19 3.4.5 Setup for I/O ports ....................................................................................................... 3-20 3.4.6 Providing of watchdog timer function by software .................................................. 3-21 3.5 List of registers ................................................................................................................... 3-22 3.6 Mask ROM ordering method ............................................................................................. 3-49 3.7 Mark specification form ..................................................................................................... 3-51 3.8 Package outline ................................................................................................................... 3-52 3.9 List of instruction codes ................................................................................................... 3-53 3.10 Machine instructions ........................................................................................................ 3-54 3.11 SFR memory map .............................................................................................................. 3-64 3.12 Pin configuration ............................................................................................................... 3-65 7630 GROUP USER’S MANUAL iii L ist of figures List of figures CHAPTER 1. HARDWARE Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 1 Pin configuration of M37630M4T-XXXFP .................................................................. 1-2 2 Functional block diagram ............................................................................................. 1-3 3 Part numbering ............................................................................................................. 1-5 4 Memory expansion plan ............................................................................................... 1-6 5 740 Family CPU register structure ............................................................................ 1-7 6 Register push and pop at interrupt generation and subroutine call ..................... 1-8 7 Structure of CPU mode register ............................................................................... 1-10 8 Memory map diagram ................................................................................................ 1-11 9 Memory map of special register (SFR) ................................................................... 1-12 10 Structure of Port- and Port direction registers ..................................................... 1-13 11 Structure of Port I/Os (1) ........................................................................................ 1-13 12 Structure of Port I/Os (2) ........................................................................................ 1-14 13 Structure of Port pull-up/down control registers .................................................. 1-15 14 Structure of Polarity control register ...................................................................... 1-15 15 Interrupt control ........................................................................................................ 1-19 16 Structure of Interrupt polarity selection register................................................... 1-19 17 Structure of Interrupt request and control registers A, B and C ....................... 1-20 18 Block diagram of key-on wake-up circuit .............................................................. 1-21 19 Block diagram of timers X and Y .......................................................................... 1-22 20 Structure of Timer X mode register ....................................................................... 1-23 21 Structure of Timer Y mode register ....................................................................... 1-24 22 Timer X bi-phase counter mode operation ........................................................... 1-25 23 Block diagram of timers 1 to 3 .............................................................................. 1-26 24 Timer 123 mode register configulation .................................................................. 1-27 25 Block diagram of clock syncronous SI/O .............................................................. 1-28 26 Timing of clock syncronous SI/O function ............................................................ 1-28 27 Structure of Serial I/O control register .................................................................. 1-29 28 Block diagram of UART ........................................................................................... 1-30 29 Structure of UART mode register .......................................................................... 1-31 30 Structure of UART control register ........................................................................ 1-31 31 Structure of UART status register .......................................................................... 1-32 32 Bit time of CAN module .......................................................................................... 1-33 33 Block diagram of CAN module ............................................................................... 1-33 34 Structure of CAN transmit control register ........................................................... 1-34 35 Structure of CAN receive control register ............................................................. 1-34 36 Structure of CAN transmit abort request register ................................................ 1-35 37 Structure of CAN bus timing control register 1 ................................................... 1-35 38 Structure of CAN bus timing control register 2 ................................................... 1-36 39 Structure of CAN mask and code registers ......................................................... 1-36 40 Structure of CAN transmission and reception buffer registers .......................... 1-37 41 Block diagram of A-D converter ............................................................................. 1-38 42 Structure of A-D control register ............................................................................ 1-39 43 Block diagram of watchdog timer ........................................................................... 1-40 44 Structure of watchdog timer register ..................................................................... 1-40 45 Example of reset circuit ........................................................................................... 1-41 46 Reset sequence ........................................................................................................ 1-41 47 Internal status of microcomputer after reset ........................................................ 1-42 iv 7630 GROUP USER’S MANUAL L ist of figures Fig. Fig. Fig. Fig. Fig. 48 49 50 51 52 Ceramic resonator circuit ........................................................................................ 1-43 Block diagram of clock generating circuit ............................................................. 1-43 Programming and testing of One Time PROM version ...................................... 1-44 Circuit for measuring output switching characteristics ........................................ 1-49 Timing diagram ......................................................................................................... 1-50 CHAPTER 2. APPLICATION Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.1.1 Memory map of I/O port related registers .......................................................... 2-2 2.1.2 Structure of Port Pi register (i = 0, 1, 2, 3, 4) ................................................. 2-3 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4) ................................. 2-3 2.1.4 Structure of Port Pi pull-up register (i = 0, 2) ................................................... 2-4 2.1.5 Structure of Port P1 pull-up register ................................................................... 2-4 2.1.6 Structure of Port P3 pull-up control register ...................................................... 2-5 2.1.7 Structure of Port P4 pull-up/down control register ............................................ 2-5 2.1.8 Structure of Porarity control register ................................................................... 2-6 2.1.9 External circuit example applying overvoltage to digital inputs....................... 2-7 2.2.1 Memory map of interrupt related registers ......................................................... 2-9 2.2.2 Structure of Interrupt request register A ........................................................... 2-10 2.2.3 Structure of Interrupt request register B ........................................................... 2-10 2.2.4 Structure of Interrupt request register C .......................................................... 2-11 2.2.5 Structure of Interrupt control register A ............................................................ 2-11 2.2.6 Structure of Interrupt control register B ............................................................ 2-12 2.2.7 Structure of Interrupt control register C ............................................................ 2-12 2.2.8 Structure of Interrupt polarity selection register .............................................. 2-13 2.2.9 Structure of Polarity control register ................................................................. 2-13 2.2.10 Interrupt setting method (1) .............................................................................. 2-14 2.2.11 Interrupt setting method (2) .............................................................................. 2-15 2.2.12 Setting method for registers related to key-on wake-up interrupt (1) ........ 2-16 2.2.13 Setting method for registers related to key-on wake-up interrupt (2) ........ 2-17 2.3.1 Memory map of timer related registers ............................................................. 2-18 2.3.2 Structure of Timer 1, Timer 3 ............................................................................ 2-19 2.3.3 Structure of Timer 2 ............................................................................................ 2-19 2.3.4 Structure of Timer 123 mode register ............................................................... 2-20 2.3.5 Structure of Timer XL, Timer XH, Timer YL, Timer YH ................................. 2-20 2.3.6 Structure of Timer X mode register .................................................................. 2-21 2.3.7 Structure of Timer Y mode register .................................................................. 2-21 2.3.8 Timers connection and division ratios [Clock function] .................................. 2-23 2.3.9 Setting of related registers [Clock function] ..................................................... 2-24 2.3.10 Control procedure [Clock function] .................................................................. 2-25 2.3.11 A method for judging if input pulse exists ..................................................... 2-26 2.3.12 Setting of related registers [Measurement of frequency] (1) ....................... 2-27 2.3.13 Setting of related registers [Measurement of frequency] (2) ....................... 2-28 2.3.14 Control procedure [Measurement of frequency] ............................................ 2-29 2.3.15 Timer connection and division ratios [Measurement of pulse width] .......... 2-30 2.3.16 Setting of related registers [Measurement of pulse width] .......................... 2-31 2.3.17 Control procedure [Measurement of pulse width] (1) ................................... 2-32 2.3.18 Control procedure [Measurement of pulse width] (2) ................................... 2-33 2.4.1 Block diagram of CAN module ........................................................................... 2-35 2.4.2 Memory map of CAN related registers ............................................................. 2-36 2.4.3 Structure of CAN transmit control register ....................................................... 2-37 2.4.4 Structure of CAN bus timing control register 1 ............................................... 2-37 2.4.5 Structure of CAN bus timing control register 2 ............................................... 2-38 7630 GROUP USER’S MANUAL v L ist of figures Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.4.6 Structure of CAN acceptance code register 0 ................................................. 2-38 2.4.7 Structure of CAN acceptance code register 1 ................................................. 2-39 2.4.8 Structure of CAN acceptance code register 2 ................................................. 2-39 2.4.9 Structure of CAN acceptance code register 3 ................................................. 2-40 2.4.10 Structure of CAN acceptance code register 4 ............................................... 2-40 2.4.11 Structure of CAN acceptance mask register 0 .............................................. 2-41 2.4.12 Structure of CAN acceptance mask register 1 .............................................. 2-41 2.4.13 Structure of CAN acceptance mask register 2 .............................................. 2-42 2.4.14 Structure of CAN acceptance mask register 3 .............................................. 2-42 2.4.15 Structure of CAN acceptance mask regiater 4 .............................................. 2-43 2.4.16 Structure of CAN receive control register ...................................................... 2-43 2.4.17 Structure of CAN transmit abort register ........................................................ 2-44 2.4.18 Structure of CAN transmit/receive buffer registers 0 .................................... 2-44 2.4.19 Structure of CAN transmit/receive buffer registers 1 .................................... 2-45 2.4.20 Structure of CAN transmit/receive buffer registers 2 .................................... 2-45 2.4.21 Structure of CAN transmit/receive buffer registers 3 .................................... 2-46 2.4.22 Structure of CAN transmit/receive buffer registers 4 .................................... 2-46 2.4.23 Structure of CAN transmit/receive buffer registers 5 .................................... 2-47 2.4.24 Structure of CAN transmit/receive buffer registers 6 to D ........................... 2-47 2.4.25 Transitions between operational modes ......................................................... 2-48 2.4.26 Transitions among module sub-modes ........................................................... 2-49 2.4.27 Segmentation of bit-time ................................................................................... 2-50 2.4.28 Module initialization sequence ......................................................................... 2-52 2.4.29 Module reset sequence ..................................................................................... 2-53 2.4.30 Structure of acceptance mask/code registers ................................................ 2-54 2.4.31 Acceptance filter logic ....................................................................................... 2-55 2.4.32 Receive buffer handling .................................................................................... 2-56 2.4.33 Flowchart of the receve process ..................................................................... 2-57 2.4.34 Receive sequence timing .................................................................................. 2-58 2.4.35 Receive sequense timing (overrun condition) ................................................ 2-59 2.4.36 Transmit buffer organization ............................................................................. 2-61 2.4.37 Transmit sequence timing (arbitration win) .................................................... 2-62 2.4.38 Flowchart of transmit process .......................................................................... 2-64 2.4.39 Error state diagram ............................................................................................ 2-65 2.5.1 Memory map of serial I/O related registers ..................................................... 2-67 2.5.2 Structure of Serial I/O shift register .................................................................. 2-68 2.5.3 Structure of Serial I/O control register .............................................................. 2-68 2.5.4 Structure of UART mode register ...................................................................... 2-69 2.5.5 Structure of UART baud rate generator ........................................................... 2-69 2.5.6 Structure of UART control register .................................................................... 2-70 2.5.7 Structure of UART status register ..................................................................... 2-70 2.5.8 Structure of UART transmit buffer register 1, 2 .............................................. 2-71 2.5.9 Structure of UART receive buffer register 1, 2 ............................................... 2-71 2.5.10 Serial I/O connection examples (1) ................................................................. 2-72 2.5.11 Serial I/O connection examples (2) ................................................................. 2-73 2.5.12 Setting of serial I/O transfer data format ....................................................... 2-74 2.5.13 Connection diagram [Output of serial data] ................................................... 2-75 2.5.14 Timing chart [Output of serial data] ................................................................ 2-75 2.5.15 Setting of serial I/O related registers [Output of serial data] ...................... 2-76 2.5.16 Setting of serial I/O transmission data [Output of serial data] ................... 2-77 2.5.17 Control procedure of clock synchronous serial I/O [Output of serial data] ... 2-78 2.5.18 Connection diagram [Communication using UART] ...................................... 2-79 2.5.19 Timing chart [Communication using UART] ................................................... 2-79 vi 7630 GROUP USER’S MANUAL L ist of figures Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.5.20 Setting of related registers on transmitting side [Communication using UART] ........ 2-81 2.5.21 Setting of related registers on receiving side [Communication using UART] ......... 2-82 2.5.22 Control procedure on transmitting side [Communication using UART] ...... 2-83 2.5.23 Control procedure on receiving side [Communication using UART] ........... 2-84 2.5.24 Connection diagram [Communication using UART] ...................................... 2-85 2.5.25 Timing chart [Communication using UART] ................................................... 2-85 2.5.26 Setting of related registers on transmitting side [Communication using UART] ........ 2-86 2.5.27 Setting of related registers on receiving side [Communication using UART] ............ 2-87 2.5.28 Control procedure on transmitting side [Communication using UART] ...... 2-88 2.5.29 Control procedure on receiving side [Communication using UART] ........... 2-89 2.6.1 Memory map of A-D conversion related registers ........................................... 2-90 2.6.2 Structure of A-D conversion register ................................................................. 2-91 2.6.3 Structure of A-D control register ........................................................................ 2-91 2.6.4 Connection diagram [Measurement of analog signals] ................................... 2-92 2.6.5 Setting of related registers [Measurement of analog signals] ....................... 2-92 2.6.6 Control procedure [Measurement of analog signals] ...................................... 2-93 2.7.1 Structure of Watchdog timer register ................................................................ 2-94 2.7.2 Set-up procedure of watchdog timer ................................................................. 2-95 2.8.1 Example of Power on reset circuit .................................................................... 2-96 2.8.2 RAM back-up system ........................................................................................... 2-96 2.9.1 Memory map of oscillation circuit related registers ........................................ 2-97 2.9.2 Structure of CPU mode register ........................................................................ 2-98 2.9.3 Structure of Watchdog timer register ................................................................ 2-98 2.9.4 Switching procedure to Stop mode ................................................................... 2-99 2.9.5 Switching procedure to Wait mode .................................................................... 2-99 2.10.1 Configuration example of using M37630T-RFS ......................................... 2-100 2.11.1 Pin configuration of 7630 group’s built-in PROM versions ........................ 2-102 2.11.2 Programming and testing of One Time PROM version .............................. 2-104 CHAPTER 3. APPENDIX Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.1.1 3.1.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.3.1 3.3.2 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.4.9 Circuit for measuring output switching characteristics ...................................... 3-6 Timing diagram ....................................................................................................... 3-7 Icc-Vcc standard characteristics (in high-speed mode) .................................... 3-8 Icc-Vcc standard characteristics (in middle-speed mode) ................................ 3-8 Power source current standard characteristics (in high-speed mode) ........... 3-9 Power source current standard characteristics (in middle-speed mode) ....... 3-9 Output current standard characteristics (P-channel) ....................................... 3-10 Output current standard characteristics (N-channel) ....................................... 3-10 Pull-up transistor standard characteristics I IL-V I .......................................................... 3-11 Pull-down transistor standard characteristics IIL-VI .................................................... 3-11 A-D conversion standard characteristics ........................................................... 3-12 Stack memory contents after instruction execution ......................................... 3-15 Interrupt routine .................................................................................................... 3-16 ____________ Wiring for the RESET input pin ......................................................................... 3-17 Wiring for clock I/O pins ..................................................................................... 3-17 W iring for the VPP p in of the One Time PROM and the EPROM version................ 3-18 Bypass capacitor across the V SS l ine and the V CC l ine ................................ 3-18 Analog signal line and a resistor and a capacitor .......................................... 3-18 Wiring for a large current signal line ................................................................ 3-19 Wiring to a signal line where potential levels change frequently ................. 3-19 V SS p attern on the underside of an oscillator ................................................. 3-20 Setup for I/O ports ............................................................................................... 3-20 7630 GROUP USER’S MANUAL vii L ist of figures Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.4.10 Watchdog timer by software ............................................................................. 3-21 3.5.1 Structure of CPU mode register ........................................................................ 3-22 3.5.2 Structure of Interrupt request register A ........................................................... 3-22 3.5.3 Structure of Interrupt request register B ........................................................... 3-23 3.5.4 Structure of Interrupt request register C .......................................................... 3-23 3.5.5 Structure of Interrupt control register A ............................................................ 3-24 3.5.6 Structure of Interrupt control register B ............................................................ 3-24 3.5.7 Structure of Interrupt control register C ............................................................ 3-25 3.5.8 Structure of Port Pi register (i = 0, 1, 2, 3, 4) ............................................... 3-25 3.5.9 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4) ............................... 3-26 3.5.10 Structure of Serial I/O shift register ................................................................ 3-26 3.5.11 Structure of Serial I/O control register ............................................................ 3-27 3.5.12 Structure of A-D conversion register ............................................................... 3-27 3.5.13 Structure of A-D control register ...................................................................... 3-28 3.5.14 Structure of Timer 1, Timer 3 .......................................................................... 3-28 3.5.15 Structure of Timer 2 .......................................................................................... 3-29 3.5.16 Structure of Timer 123 mode register ............................................................. 3-29 3.5.17 Structure of Timer XL, Timer XH, Timer YL, Timer YH ............................... 3-30 3.5.18 Structure of Timer X mode register ................................................................ 3-30 3.5.19 Structure of Timer Y mode register ................................................................ 3-31 3.5.20 Structure of UART mode register .................................................................... 3-31 3.5.21 Structure of UART baud rate generator ......................................................... 3-32 3.5.22 Structure of UART control register .................................................................. 3-32 3.5.23 Structure of UART status register ................................................................... 3-33 3.5.24 Structure of UART transmit buffer register 1, 2 ............................................ 3-33 3.5.25 Structure of UART receive buffer register 1, 2 ............................................. 3-34 3.5.26 Structure of Port Pi pull-up control register (i = 0, 2).................................. 3-34 3.5.27 Structure of Port P1 pull-up control register .................................................. 3-35 3.5.28 Structure of Port P3 pull-up control register .................................................. 3-35 3.5.29 Structure of Port P4 pull-up/down control register ........................................ 3-36 3.5.30 Structure of Interrupt polarity selection register ............................................ 3-36 3.5.31 Structure of Watchdog timer register .............................................................. 3-37 3.5.32 Structure of Polarity control register ............................................................... 3-37 3.5.33 Structure of CAN transmit control register ..................................................... 3-38 3.5.34 Structure of CAN bus timing control register 1 ............................................. 3-38 3.5.35 Structure of CAN bus timing control register 2 ............................................. 3-39 3.5.36 Structure of CAN acceptance code register 0 ............................................... 3-39 3.5.37 Structure of CAN acceptance code register 1 ............................................... 3-40 3.5.38 Structure of CAN acceptance code register 2 ............................................... 3-40 3.5.39 Structure of CAN acceptance code register 3 ............................................... 3-41 3.5.40 Structure of CAN acceptance code register 4 ............................................... 3-41 3.5.41 Structure of CAN acceptance mask register 0 .............................................. 3-42 3.5.42 Structure of CAN acceptance mask register 1 .............................................. 3-42 3.5.43 Structure of CAN acceptance mask register 2 .............................................. 3-43 3.5.44 Structure of CAN acceptance mask register 3 .............................................. 3-43 3.5.45 Structure of CAN acceptance mask regiater 4 .............................................. 3-44 3.5.46 Structure of CAN receive control register ...................................................... 3-44 3.5.47 Structure of CAN transmit abort register ........................................................ 3-45 3.5.48 Structure of CAN transmit/receive buffer registers 0 .................................... 3-45 3.5.49 Structure of CAN transmit/receive buffer registers 1 .................................... 3-46 3.5.50 Structure of CAN transmit/receive buffer registers 2 .................................... 3-46 3.5.51 Structure of CAN transmit/receive buffer registers 3 .................................... 3-47 3.5.52 Structure of CAN transmit/receive buffer registers 4 .................................... 3-47 viii 7630 GROUP USER’S MANUAL L ist of figures Fig. 3.5.53 Structure of CAN transmit/receive buffer registers 5 .................................... 3-48 Fig. 3.5.54 Structure of CAN transmit/receive buffer registers 6 to D ........................... 3-48 7630 GROUP USER’S MANUAL ix List of tables List of tables CHAPTER 1. HARDWARE Table Table Table Table Table Table Table Table Table Table Table Table Table Table 1 Pin description .......................................................................................................... 1-4 2 List of supported products ...................................................................................... 1-6 3 Push and pop instructions of accumulator of processor status register ......... 1-8 4 Set and clear instructions of each bit of processor status register ................. 1-9 5 Interrupt vector addresses and priority ............................................................... 1-18 6 Timer X count direction in bi-phase counter mode .......................................... 1-24 7 Output control conditions ...................................................................................... 1-30 8 Programming adapter name ................................................................................. 1-44 9 Absolute maximum ratings ................................................................................... 1-45 10 Recommended operating conditions ................................................................... 1-45 11 Electrical characteristics ....................................................................................... 1-46 12 A-D converter characteristic ................................................................................. 1-47 13 Timing requirements .............................................................................................. 1-48 14 Switching characteristics ...................................................................................... 1-49 CHAPTER 2. APPLICATION Table Table Table Table Table Table Table Table 2.1.1 Handling of unused pins .................................................................................... 2-8 2.5.1 Setting examples of Baud rate generator values and transfer bit rate values ..... 2-80 2.5.2 Clock divider selection for serial I/O .............................................................. 2-80 2.7.1 Watchdog timer cycle ....................................................................................... 2-95 2.11.1 7630 group’s built-in PROM version supporting products ....................... 2-101 2.11.2 Programming adapter ................................................................................... 2-103 2.11.3 Setting of programming adapter switch ..................................................... 2-103 2.11.4 Setting of PROM programmer address ...................................................... 2-103 CHAPTER 3. APPENDIX Table Table Table Table Table Table 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 Absolute maximum ratings ................................................................................. 3-2 Recommended operating conditions ................................................................. 3-3 Electrical characteristics ..................................................................................... 3-4 A-D converter characteristics ............................................................................ 3-5 Timing requirements ........................................................................................... 3-5 Switching characteristics .................................................................................... 3-6 7630 GROUP USER’S MANUAL ix CHAPTER 1 HARDWARE DESCRIPTION FEARURES APPLICATION FUNCTION BLOCK DIAGRAM PIN DESCRIPTION PART NUMBERING GROUP EXPANSION FUNCTIONAL DESCRIPTION +$5':$5( DESCRIPTION DESCRIPTION The 7630 group is a single chip 8-bit microcomputer designed with CMOS silicon gate technology. Being equipped with a CAN (Controller Area Network) module circuit, the microcomputer is suited to drive automotive equipments. The CAN module complies with CAN specification version 2.0, part B and allows priority-based message management. In addition to the microcomputers simple instruction set, the ROM, RAM and I/O addresses are placed in the same memory map to enable easy programming. The built-in ROM is available as mask ROM or One Time PROM. For development purposes, emulator- and EPROM-type microcomputers are available as well. z z z z z z z z z z z FEATURES z z z z Basic machine-language instructions . . . . . . . . . . . . . . . . . 71 Minimum instruction execution time (at 10 MHz oscillation frequency). . . . . . . . . . . . . . . . . . .0.2 µs Memory size ROM. . . . . . . . . . . . . . . . . 16252 bytes (M37630M4T-XXXFP) RAM . . . . . . . . . . . . . . . . . . . 512 bytes (M37630M4T-XXXFP) I/O ports Programmable I/O ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 24 sources, 24 vectors Timers 16-bit Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 channels 8-bit Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 channels Serial I/Os Clock synchronous. . . . . . . . . . . . . . . . . . . . . . . . . . . 1 channel UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 channel CAN module (CAN specification version 2.0, part B) . . . . . . . . . . . 1 channel A-D converter . . . . . . . . . . . . . . . . . . . . . . . . 8-bits x 8 channels Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Clock Generating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Built-in with internal feedback resistor Power source voltage (at 10 MHz oscillation frequency). . . . . . . . . . . . . . . 4.0 to 5.5 V Power dissipation In high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 mW (at 8 MHz oscillation frequency, at 5 V power source voltage) Operating temperature range. . . . . . . . . . . . . . . . . –40 to 85 °C Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44QFP (44P6N-A) APPLICATION Automotive controls PIN CONFIGURATION (TOP VIEW) P15/CNTR1 P16/PWM P14/CNTR0 P12/INT1 P11/INT0 P07/AN7 P06/AN6 P05/AN5 25 P04/AN4 24 33 32 31 30 29 28 27 26 23 P03/AN3 P13/TX0 P17 P20/SIN P21/SOUT P22/SCLK P23/SRDY VSS P24/URXD P25/UTXD P26/URTS P27/UCTS P30 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 M37630M4T-XXXFP M37630E4T-XXXFP 18 17 16 15 14 13 12 P02/AN2 P01/AN1 P00/AN0 VREF AVSS VCC XOUT XIN VSS RESET P47/KW7 10 P34 P40/KW0 P33 P41/KW1 P42/KW2 P43/KW3 P44/KW4 P45/KW5 Package type: 44P6N-A 44-pin plastic molded QFP Fig. 1 Pin configuration of M37630M4T–XXXFP 1-2 7630 Group User’s Manual P32/CRX P46/KW6 P31/CTX 11 1 2 3 4 5 6 7 8 9 Fig. 2 Functional block diagram M37630MXT-XXXFP FUNCTIONAL BLOCK DIAGRAM (PACKAGE: 44P6N-A) Clock output XOUT 16 Clock input XIN 15 Reset input RESET 13 VCC 17 14 VSS 39 AVSS 18 Clock generating circuit CPU A (8) X (8) Y (8) S (8) ROM RAM WDT 2 Timer X (16) Timer Y (16) Timer 1 (8) Timer 2 (8) Timer 3 (8) PWM PCH (8) PCL (8) PS (8) 7630 Group User’s Manual 1-3 key on wake up CAN 2 UART 4 Serial I/O 4 A-D Converter INT0, INT1 2 8 FUNCTIONAL BLOCK DIAGRAM P4 (8) P3 (5) P2 (8) 3 P1 (7) P0 (8) +$5':$5( 12 11 10 9 8 7 6 5 4 3 2 1 44 43 42 41 40 38 37 36 35 34 33 32 31 30 29 28 19 27 26 25 24 23 22 21 20 VREF input I/O port P4 I/O port P3 I/O port P2 I/O port P1 I/O port P0 +$5':$5( PIN DESCRIPTION PIN DESCRIPTION Table 1: Pin description Pin VCC, VSS AVSS Name Power source voltage Analog power source voltage Input/Output Description Power supply pins; apply 4.0 to 5.5 V to VCC and 0 V to VSS Ground pin for A-D converter. Connect to VSS Reset pin. This pin must be kept at “L” level for more than 2 µs, to enter the reset state. If the crystal or ceramic resonator requires more time to stabilize, extend the “L” level period. Input and output pins of the internal clock generating circuit. Connect a ceramic or quartz–crystal resonator between the XIN and XOUT pins. When an external clock source is used, connect it to XIN and leave XOUT open. Reference voltage input pin for A-D converter RESET Reset input Input XIN XOUT VREF P00/AN0— P07/AN7 Clock input Clock output Reference voltage input I/O port P0 Input Output Input I/O CMOS I/O ports or analog input ports CMOS input port or external interrupt input port. The active edge (rising or falling) of external interrupts can be selected. This pin will be used as VPP pin during PROM programming of One Time PROM Versions. CMOS I/O port or external interrupt input port. The active edge (rising or falling) of external interrupts can be selected. CMOS I/O port or input pin used in the bi-phase counter mode P11/INT0 Input P12/INT1 P13/TX0 P14/CNTR0 P15/CNTR1 P16/PWM P17 P20/SIN P21/SOUT P22/SCLK P23/SRDY I/O port P2 P24/URXD P25/UTXD P26/URTS P27/UCTS P30 P31/CTX I/O port P3 P32/CRX P33—P34 P40/KW0— P47/KW7 I/O port P4 I/O I/O I/O I/O port P1 I/O CMOS I/O port or timer X input pin used for the event counter, pulse width measurement and bi-phase counter mode CMOS I/O port or timer Y input pin used for the event counter, pulse width and pulse period measurement mode CMOS I/O port or PWM output pin used in the PWM mode of timers 2 and 3 CMOS I/O port CMOS I/O ports or clock synchronous serial I/O pins CMOS I/O ports or asynchronous serial I/O pins CMOS I/O port CMOS I/O port or CAN transmit data pin CMOS I/O port or CAN receive data pin CMOS I/O port CMOS I/O ports. These ports can be used for key-on wake-up when configured as inputs. 1-4 7630 Group User’s Manual +$5':$5( PART NUMBERING PART NUMBERING Product M37630 M 4 T– XXX FP Package type FP: 44P6N-A package FS: 80D0 package ROM number Omitted in One Time PROM version (blank) and EPROM version T: Automotive use ROM/PROM size 4: 16384 bytes The first 128 bytes and the last 4 bytes of ROM are reserved areas. They cannot be used. Memory type M: Mask ROM version E: EPROM or One Time PROM version Fig. 3 Part numbering 7630 Group User’s Manual 1-5 +$5':$5( GROUP EXPANSION GROUP EXPANSION Mitsubishi plans to expand the 7630 group as follows: Memory Size ROM/PROM size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Kbytes RAM size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 bytes Memory Type Support mask ROM, One Time PROM and EPROM versions. Package 44P6N-A . . . . . . . . . . . . . . . . . .0.8mm-pitch plastic molded QFP 80D0 . . . . . . . . . . . 0.8mm-pitch ceramic LCC (EPROM version) ROM External 60K 48K 32K 28K 24K 20K M37630M4T 16K 12K 8K M37630E4T Mass product Under development 384 512 640 768 896 1024 RAM size (bytes) Fig. 4 Memory expansion plan Currently supported products are listed below: Table 2: List of supported products Product M37630M4T-XXXFP M37630E4T-XXXFP M37630E4FP M37630E4FS 16384 (16252) 80D0 512 44P6N-A (P)ROM size (bytes) ROM size for User ( ) RAM size (bytes) Package Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Remarks As of March 1998 1-6 7630 Group User’s Manual HARDWARE FUNCTIONAL DESCRIPTION FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 7630 group uses the standard 740 family instruction set. Refer to the table of 7600 series addressing modes and machine instructions or the 7600 series Software Manual for details on the instruction set. Machine-resident 7600 series instructions are as follows: The MUL, DIV, WIT and STP instruction can be used. The central processing unit (CPU) has the six registers. Stack pointer (S) The stack pointer is an 8-bit register used during sub-routine calls and interrupts. The stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack address are determined by the Stack Page Selection Bit. If the Stack Page Selection Bit is “0”, then the RAM in the zero page is used as the stack area. If the Stack Page Selection Bit is “1”, then RAM in page 1 is used as the stack area. The Stack Page Selection Bit is located in the SFR area in the zero page. Note that the initial value of the Stack Page Selection Bit varies with each microcomputer type. Also some microcomputer types have no Stack Page Selection Bit and the upper eight bits of the stack address are fixed. The operations of pushing register contents onto the stack and popping them from the stack are shown in Fig.7. Accumulator (A) The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. Index register X (X), Index register Y (Y) Both index register X and index register Y are 8-bit registers. In the index addressing modes, the value of the OPERAND is added to the contents of register X or register Y and specifies the real address. When the T flag in the processor status register is set to “1”, the value contained in index register X becomes the address for the second OPERAND. Program counter (PC) The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. b7 b0 A b7 b0 Accumulator Index Register X b0 X b7 Y b7 b0 Index Register Y Stack Pointer b0 S b15 b7 PCH b7 PCL b0 Program Counter N V T B D I Z C Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag Fig. 5 740 Family CPU register structure 7630 Groop User’s Manual 1-7 HARDWARE FUNCTIONAL DESCRIPTION On-going Routine Interrupt request (Note 1) Execute JSR M (S) Store Return Address on Stack (Note 2) (S) M (S) (S) (PCH) (S – 1) (PCL) (S – 1) M (S) (S) M (S) (S) M (S) (S) (PCH) (S – 1) (PCL) (S – 1) (PS) (S – 1) Store Contents of Processor Status Register on Stack Store Return Address on Stack (Note 2) Subroutine Execute RTS Restore Return Address (S) (PCL) (S) (PCH) (S + 1) M (S) (S + 1) M (S) Interrupt Service Routine Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S + 1) M (S) (S + 1) M (S) (S + 1) M (S) I Flag “0” to “1” Fetch the Jump Vector Restore Contents of Processor Status Register Restore Return Address Note 1 : The condition to enable the interrupt Interrupt enable bit is “1” Interrupt disable flag is “0” 2 : When an interrupt occurs, the address of the next instruction to be executed is stored in the stack area. When a subroutine is called, the address one before the next instruction to be executed is stored in the stack area. Fig. 6 Register push and pop at interrupt generation and subroutine call Table 3 Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP 1-8 7630 Groop User’s Manual HARDWARE FUNCTIONAL DESCRIPTION Processor status register (PS) The processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. After reset, the Interrupt disable (I) flag is set to “1”, but all other flags are undefined. Since the Index X mode (T) and Decimal mode (D) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. (2) Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. (3) Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. When an interrupt occurs, this flag is automatically set to “1” to prevent other interrupts from interfering until the current interrupt is serviced. (4) Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. (5) Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. The saved processor status is the only place where the break flag is ever set. (6) Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations, i.e. between memory and memory, memory and I/O, and I/O and I/O. In this case, the result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1. The address of memory location 1 is specified by index register X, and the address of memory location 2 is specified by normal addressing modes. (7) Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. (8) Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 4 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag – – I flag SEI CLI D flag SED CLD B flag – – T flag SET CLT V flag – CLV N flag – – 7630 Groop User’s Manual 1-9 +$5':$5( FUNCTIONAL DESCRIPTION FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The core of 7630 group microcomputers is the 7600 series CPU. This core is based on the standard instruction set of 740 series; however the performance is improved by allowing to execute the same instructions as that of the 740 series in less cycles. Refer to the 7600 Series Software Manual for details of the instruction set. 7 0 CPU mode register (address 000016) CPUM Processor mode bits (set these bits to “00”) b1 b0 CPU Mode Register CPUM The CPU mode register contains the stack page selection bit and internal system clock selection bit. The CPU mode register is allocated to address 000016. 0 0 1 1 0 1 0 1 : : : : Single–chip mode Not used Not used Not used Stack page selection bit 0 : 0 page 1 : 1 page Not used (“0” when read, do not write “1”) Internal system clock selection bit 0 : φ=f(XIN) divided by 2 (high–speed mode) 1 : φ=f(XIN) divided by 8 (middle–speed mode) Not used (“0” when read, do not write “1”) Fig. 7 Structure of CPU mode register 1-10 7630 Group User’s Manual +$5':$5( FUNCTIONAL DESCRIPTION MEMORY Special Function Register (SFR) Area The special function register (SFR) area contains the registers relating to functions such as I/O ports and timers. Interrupt Vector Area The interrupt vector area is for storing jump destination addresses used at reset or when an interrupt is generated. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Zero Page This area can be accessed most efficiently by means of the zero page addressing mode. ROM ROM is used for storing user’s program code as well as the interrupt vector area. RAM area RAM size (byte) 192 256 384 512 640 768 896 1024 1536 2048 Address XXXX16 011F16 015F16 01DF16 025F16 02DF16 035F16 03DF16 045F16 06DF16 085F16 Special Page This area can be accessed most efficiently by means of the special page addressing mode. 000016 004016 SFR area CAN SFRs Zero page 006016 00FF16 User RAM XXXX16 086016 ROM area ROM size (byte) 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 Address YYYY16 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 Address ZZZZ16 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 FFCA16 FFFB16 FFFC16 FFFF16 YYYY16 ZZZZ16 Not used Reserved ROM area ROM FF0016 Interrupt vector area Reserved ROM area Special page Fig. 8 Memory map diagram 7630 Group User’s Manual 1-11 +$5':$5( FUNCTIONAL DESCRIPTION SPECIAL FUNCTION REGISTERS (SFR) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 CPU mode register Not used Interrupt request register A Interrupt request register B Interrupt request register C Interrupt control register A Interrupt control register B Interrupt control register C Port P0 register Port P0 direction register Port P1 register Port P1 direction register Port P2 register Port P2 direction register Port P3 register Port P3 direction register Port P4 register Port P4 direction register Serial I/O shift register Serial I/O control register A-D conversion register A-D control register Timer 1 Timer 2 Timer 3 Timer 123 mode register CPUM IREQA IREQB IREQC ICONA ICONB ICONC P0 P0D P1 P1D P2 P2D P3 P3D P4 P4D SIO SIOCON AD ADCON T1 T2 T3 T123M TXL TXH TYL TYH TXM TYM UMOD UBRG UCON USTS UTBR1 UTBR2 URBR1 URBR2 PUP0 PUP1 PUP2 PUP3 PUP4 IPOL WDT PCON 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 CAN transmit control register CAN bus timing control register 1 CAN bus timing control register 2 CAN acceptance code register 0 CAN acceptance code register 1 CAN acceptance code register 2 CAN acceptance code register 3 CAN acceptance code register 4 CAN acceptance mask register 0 CAN acceptance mask register 1 CAN acceptance mask register 2 CAN acceptance mask register 3 CAN acceptance mask register 4 CAN receive control register CAN transmit abort register Reserved CAN transmit buffer register 0 CAN transmit buffer register 1 CAN transmit buffer register 2 CAN transmit buffer register 3 CAN transmit buffer register 4 CAN transmit buffer register 5 CAN transmit buffer register 6 CAN transmit buffer register 7 CAN transmit buffer register 8 CAN transmit buffer register 9 CTRM CBTCON1 CBTCON2 CAC0 CAC1 CAC2 CAC3 CAC4 CAM0 CAM1 CAM2 CAM3 CAM4 CREC CABORT CTB0 CTB1 CTB2 CTB3 CTB4 CTB5 CTB6 CTB7 CTB8 CTB9 CTBA CTBB CTBC CTBD Timer XL 001B16 Timer XH 001C16 Timer YL 001D16 Timer YH 001E16 Timer X mode register 001F16 Timer Y mode register 002016 UART mode register 002116 UART baud rate generator 002216 UART control register 002316 UART status register 002416 UART transmit buffer register 1 002516 UART transmit buffer register 2 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 UART receive buffer register 1 UART receive buffer register 2 Port P0 pull-up control register Port P1 pull-up control register Port P2 pull-up control register Port P3 pull-up control register Port P4 pull-up/down control register Interrupt polarity selection register Watchdog timer register Polarity control register CAN transmit buffer register A 004B16 CAN transmit buffer register B 004C16 CAN transmit buffer register C 004D16 CAN transmit buffer register D 004E16 Reserved 004F16 Reserved 005016 CAN receive buffer register 0 005116 CAN receive buffer register 1 005216 CAN receive buffer register 2 005316 CAN receive buffer register 3 005416 CAN receive buffer register 4 005516 CAN receive buffer register 5 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 CAN receive buffer register 6 CAN receive buffer register 7 CAN receive buffer register 8 CAN receive buffer register 9 CAN receive buffer register A CAN receive buffer register B CAN receive buffer register C CAN receive buffer register D Reserved Reserved CRB0 CRB1 CRB2 CRB3 CRB4 CRB5 CRB6 CRB7 CRB8 CRB9 CRBA CRBB CRBC CRBD Fig. 9 Memory map of special register (SFR) 1-12 7630 Group User’s Manual +$5':$5( I/O PORTS I/O PORTS The 7630 group has 35 programmable I/O pins and one input pin arranged in five I/O ports (ports P0 to P4). The I/O ports are controlled by the corresponding port registers and port direction registers; each I/O pin can be controlled separately. When data is read from a port configured as an output port, the port latch’s contents are read instead of the port level. A port configured 7 0 Port Pi register (i = 0 to 4) (address 000816 + 2 · i) Pi Port Pij control bit (j = 0 to 7) 0 : “L” level 1 : “H” level Note : The control bits corresponding to P10, P35, P36 and P37 are not used (“0” when read, do not write “1”). as an input port becomes floating and its level can be read. Data written to this port will affect the port latch only; the port remains floating. Refer to Structure of port- and port direction registers, Structure of port I/Os (1) and Structure of port I/Os (2). 7 0 Port Pi direction register (i = 0 to 4) (address 000916 + 2 · i) PiD Port Pij direction control bit (j = 0 to 7) 0 : Port configured as input 1 : Port configured as output Note : The direction control bits corresponding to P10, P11, P35, P36 and P37 are not used (“0” when read, do not write “1”). Port direction registers are undefined when read (write only). Fig. 10 Structure of port- and port direction registers (1) Ports P00/AN0 to P07/AN7 Pull-up control bit Analog input selection Direction register Data bus Port latch Data bus direction register Port latch (4) Port P13/TX0 Pull-up control bit ADC input Analog input selection Timer bi-phase mode input (5) Ports P14/CNTR0, P15/CNTR1 Pull-up control bit (2) Port P11/INT0 Interrupt input Data bus Data bus Direction register Port latch Timer bi-phase mode input (3) Port P12/INT1 Pull-up control bit Direction register Data bus Port latch (6) Port P16/PWM Pull-up control bit PWM output enable Direction register Data bus Port latch Interrupt input PWM output Fig. 11 Structure of port I/Os (1) 7630 Group User’s Manual 1-13 +$5':$5( I/O PORTS (7) Ports P17, P30, P33, P34 Pull-up control bit Direction register Data bus Port latch (12) Ports P24/URXD, P27/UCTS Transmission* or reception in Pull-up control bit progress Transmit* or receive enable bit Direction register Data bus Port latch URXD or UCTS input (8) Port P20/SIN Pull-up control bit SIO Port Select Direction register Data bus Port latch (13) Ports P25/UTXD, P26/URTS Transmission or reception** in Pull-up control bit progress Transmit or receive** enable bit Direction register Data bus Port latch SIO1 input UTXD or URTS output (*) for UCTS (**) for URTS (9) Port P21/SOUT Pull-up control bit SIO port selection bit Transmit complete signal Direction register Data bus Port latch (14) Port P31/CTX Pull-up control bit CAN port selection bit Direction register Data bus Port latch SIO output CTX output (15) Port P32/CRX (10) Port P22/SCLK Pull-up control bit Clock selection bit Port selection bit direction register Data bus Port latch CAN interrupt SIO clock output External clock input CRX input CAN dominant level control bit Pull-up/down control bit Direction register Data bus Port latch (16) Ports P40/KW0 to P47/KW7 (11) Port P23/SRDY Pull-up control bit SRDY output selection bit Direction register Data bus Port latch Key-on wake-up interrupt SRDY output Data bus Key-on wake-up control bit Pull-up/down control bit Direction register Port latch Fig. 12 Structure of port I/Os (2) 1-14 7630 Group User’s Manual +$5':$5( I/O PORTS Port Pull-up/pull-down Function Each pin of ports P0 to P4 except P11 is equipped with a programmable pull-up transistor. P32/CRX and P40/KW0 to P47/KW7 are equipped with programmable pull-down transistors as well. The pullup function of P0 to P3 can be controlled by the corresponding port 7 0 Port Pi pull-up control register (address 002816 + i) (i = 0, 2) PUP0, PUP2 Pij pull-up transistor control bit (j = 0 to 7) 0 : Pull-up transistor disabled 1 : Pull-up transistor enabled 7 0 Port P1 pull-up control register (address 002916) PUP1 Not used (“0” when read, do not write “1”) P1j pull-up transistor control bit (j = 2 to 7) 7 0 Port P3 pull-up control register (address 002B16) PUP3 P3j pull-up transistor control bit (j = 0, 1) P32 pull-up/down transistor control bit P3j pull-up transistor control bit (j = 3, 4) Not used (“0” when read, do not write “1”) 7 0 Port P4 pull-up/down control register (address 002C16) PUP4 P4j pull-up/down transistor control bit (j = 0 to 7) pull-up control registers (see Structure of port pull-up/down control registers). The pull-up/down function of ports P32 and P4 can be controlled by the corresponding port pull-up/pull-down registers together with the polarity control register (see Structure of polarity control register). 0 : Pull-up/down transistor disabled 1 : Pull-up/down transistor enabled Fig. 13 Structure of port pull-up/down control registers 7 0 Polarity control register (address 002F16) PCON Key-on wake-up polarity control bit 0 : Low level active 1 : High level active CAN module dominant level control bit 0 : Low level dominant 1 : High level dominant Not used (undefined when read) Fig. 14 Structure of polarity control register 7630 Group User’s Manual 1-15 +$5':$5( I/O PORTS Port Overvoltage Application When configured as input ports, P1 to P4 may be subjected to overvoltage (VI > VCC) if the input current to the applicable port is limited to the specified values (see “Table 10:”). Use a serial resistor of appropriate size to limit the input current. To estimate the resistor value, assume the port voltage to be VCC at overvoltage condition. Notes: • Subjecting ports to overvoltage may effect the supply voltage. Assure to keep VCC and VSS within the target limits. • • Avoid to subject ports to overvoltage causing VCC to rise above 5.5 V. The overvoltage condition causing input current flowing through the internal port protection circuits has a negative effect on the ports noise immunity. Therefore, careful and intense testing of the target system’s noise immunity is required. Refer to the “countermeasures against noise” of the corresponding users manual. Port P0 must not be subjected to overvoltage conditions. • 1-16 7630 Group User’s Manual +$5':$5( INTERRUPTS INTERRUPTS There are 24 interrupts: 6 external, 17 internal, and 1 software. 2. 3. Interrupt Control Each interrupt except the BRK instruction interrupt has both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs when the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be cleared or set by software. Interrupt request bits can be cleared by software but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupt requests occur at the same time, the interrupt with the highest priority is accepted first. 4. The contents of the program counter and processor status register are automatically pushed onto the stack. Concurrently with the push operation, the interrupt jump destination address is read from the vector table into the program counter. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. Notes on use When the active edge of an external interrupt (INT0, INT1, CNTR0, CNTR1, CWKU or KOI) is changed, the corresponding interrupt request bit may also be set. Therefore, take the following sequence. (1) Disable the external interrupt which is selected. (2) Change the active edge in interrupt edge selection register. (in the case of CNTR0: Timer X mode register; in the case of CNTR1: Timer Y mode register) (3) Clear the interrupt request bit to “0”. (4) Enable the external interrupt which is selected. Interrupt Operation Upon acceptance of an interrupt, the following operations are automatically performed. 1. The processing being executed is stopped. 7630 Group User’s Manual 1-17 +$5':$5( INTERRUPTS . Table 5: Interrupt vector addresses and priority Vector Address (Note 1) Interrupt source Reset (Note 2) Watchdog timer INT0 INT1 CAN successful transmit Priority High 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16 FFDB16 FFD916 FFD716 FFD516 FFD316 Low FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16 FFDA16 FFD816 FFD616 FFD416 FFD216 Interrupt Request Generating Conditions At Reset At Watchdog timer underflow At detection of either rising or falling edge of INT0 interrupt At detection of either rising or falling edge of INT1 interrupt At CAN module successful transmission of message At CAN module successful reception of message If CAN module receives message when receive buffers are full. When CAN module enters into error passive state When CAN module enters into bus off state When CAN module wakes up via CAN bus At Timer X underflow or overflow At Timer Y underflow At Timer 1 underflow At Timer 2 underflow At Timer 3 underflow At detection of either rising or falling edge in CNTR0 input At detection of either rising or falling edge in CNTR1 input At completion of UART receive At completion of UART transmit At UART transmit buffer empty When UART reception error occurs. At completion of serial I/O data transmit and receive At completion of A-D conversion At detection of either rising or falling edge of P4 input At BRK instruction execution Remarks Non-maskable Non-maskable External Interrupt (active edge selectable) External Interrupt (active edge selectable) Valid when CAN module is activated and request transmit Valid when CAN module is activated Valid when CAN module is activated Valid when CAN module is active Valid when CAN module is active CAN successful receive CAN overrun CAN error passive CAN error bus off CAN wake up Timer X Timer Y Timer 1 Timer 2 Timer 3 CNTR0 CNTR1 UART receive UART transmit UART transmit buffer empty UART receive error Serial I/O A-D conversion Key-on wake-up BRK instruction External Interrupt (active edge selectable) External Interrupt (active edge selectable) Valid when UART is selected Valid when UART is selected Valid when UART is selected Valid when UART is selected 22 23 24 25 FFD116 FFCF16 FFCD16 FFCB16 FFD016 FFCE16 FFCC16 FFCA16 Valid when serial I/O is selected External Interrupt (active edge selectable) Non-maskable Notes 1: Vector addresses contain interrupt jump destination address 2: Reset function in the same way as an interrupt with the highest priority 1-18 7630 Group User’s Manual +$5':$5( INTERRUPTS Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request Fig. 15 Interrupt control For the external interrupts INT0 and INT1, the active edge causing the interrupt request can be selected by the INT0 and INT1 interrupt edge selection bits of the interrupt polarity selection register (IPOL); please refer to Fig. 16 below. 7 0 Interrupt polarity selection register (Address 002D16) IPOL Not used (returns to “0” when read, do not write “1” in this bit) INT0 interrupt edge selection bit INT1 interrupt edge selection bit Not used (returns to “0” when read, do not write “1” in these bits) 0 : Falling edge active 1 : Rising edge active Fig. 16 Structure of interrupt polarity selection register 7630 Group User’s Manual 1-19 +$5':$5( INTERRUPTS Interrupt request register A (address 000216) IREQA Not used (returns to ”0” when read) External interrupt INT0 request bit External interrupt INT1 request bit CAN successful transmission interrupt request bit CAN successful receive interrupt request bit CAN overrun interrupt request bit CAN error passive interrupt request bit CAN bus off interrupt request bit 7 0 Interrupt request register B (address 000316) IREQB CAN wake up interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit 7 0 Interrupt request register C (address 000416) IREQC UART receive complete (receive buffer full) interrupt request bit UART transmit complete (transmit register empty) interrupt request bit UART transmit buffer empty interrupt request bit UART receive error interrupt request bit Serial I/O interrupt request bit AD conversion complete interrupt request bit Key-on wake-up interrupt request bit Not used (returns to ”0” when read) 0 : No interrupt request 1 : Interrupt requested Fig. 17 Structure of interrupt request and control registers A, B and C 0: 1: Interrupt disabled Interrupt enabled 7 0 Interrupt control register C (address 000716) ICONC UART receive complete (receive buffer full) interrupt enable bit UART transmit complete (transmit register empty) interrupt enable bit UART transmit buffer empty interrupt enable bit UART receive error interrupt enable bit Serial I/O interrupt enable bit AD conversion complete interrupt enable bit Key-on wake-up interrupt enable bit Not used (returns to ”0” when read) 7 Interrupt control register A (address 000516) ICONA Not used (returns to ”0” when read) External interrupt INT0 enable bit External interrupt INT1 enable bit CAN successful transmission interrupt enable bit CAN successful receive interrupt enable bit CAN overrun interrupt enable bit CAN error passive interrupt enable bit CAN bus off interrupt enable bit 7 0 7 0 0 Interrupt control register B (address 000616) ICONB CAN wake–up interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit 1-20 7630 Group User’s Manual +$5':$5( KEY-ON WAKE-UP KEY-ON WAKE-UP “Key-on wake-up” is one way of returning from a power-down state caused by the STP or WIT instruction. Any terminal of port P4 can be used to generate the key-on wake-up interrupt request. The active polarity can be selected by the key-on wake-up polarity control bit of PCON (see Fig. 14). If any pin of port P4 has the selected active level applied, the key-on wake-up interrupt request will be set to “1”. Please refer to Fig. 18. key-on wake-up control bit P4Dj PUP4j port P4j/KWj … key-on wake-up interrupt port P4j I/O circuit j = 0 to 7 Fig. 18 Block diagram of key-on wake-up circuit 7630 Group User’s Manual 1-21 +$5':$5( TIMERS TIMERS The 7630 group has five timers: two 16-bit timers and three 8-bit timers . All these timers will be described in detail below. 16-bit Timers Timers X and Y are 16-bit timers with multiple operating modes. Please refer to Fig. 19. φ 1/4 1/16 1/64 1/128 TYM1,0 “00” “01” “10” “11” TXM5,4 “00”, “11” “01” “10” Count direction control TXM7 TXL latch (8) TXH latch (8) TXL counter (8) TXH counter (8) TX interrupt request P13/TX0 Edge detector Sign generator P14/CNTR0 Edge detector “0” “1” TXM6 “01” Down “00”, “10”, “11” TXM5, 4 CNTR0 interrupt request 1/2 1/8 1/32 “00” “01” “10” TXM5, 4=“11” TYM3, 2 “0x”, “11” TYM7 TYM5, 4 TYL latch (8) TYH latch (8) TYL counter (8) “10” TYM5, 4=“11” Rising edge detector Falling edge detector TYH counter (8) TY interrupt request 1/64 “11” P15/CNTR1 “1” “0” TYM5, 4=“01” “0x”, “10” “11” CNTR1 interrupt request TYM5, 4 TYM6 Fig. 19 Block diagram of timers X and Y ( φ is internal system clock) Timer X Timer X is a 16-bit timer with a 16-bit reload latch supporting the following operating modes: (1) Timer mode (2) Bi-phase counter mode (3) Event counter mode (4) Pulse width measurement mode These modes can be selected by the timer X mode register (TXM). In the timer- and pulse width measurement mode, the timer’s count source can be selected by the timer X count source selection bits of the timer Y mode register (TYM). Please refer to the Figures below for the TXM and TYM bit assignment. On read or write access to timer X, note that the high-order and loworder bytes must be accessed in the specific order. Write method When writing to the timer X, write the low-order byte first. The data written is stored in a temporary register which is assigned to the same address as TXL. Next, write the high-order byte. When this is finished, the data is placed in the timer X high-order reload latch and the low-order byte is transferred from its temporary register to the timer X low-order reload latch. Depending on the timer X write control bit, the latch contents are reloaded to the timer immediately (write control bit = “0”) or on the next timer underflow (write control bit = “1”). Read method When reading the timer X, read the high-order byte first. This causes the timer X high- and low-order bytes to be transferred to temporary registers being assigned to the same addresses as TXH and TXL. Next, read the low-order byte which is read from the temporary register. This method assures the correct timer value can be read during the timer count operation. Timer X count stop control Regardless of the actual operating mode, timer X can be stopped by setting the timer X count stop bit (bit 7 of the timer X mode register) to “1”. 1-22 7630 Group User’s Manual +$5':$5( TIMERS 7 0 Timer X mode register (address 001E16) TXM Timer X data write control bit 0 : Data is written to latch and timer 1 : Data is written to latch only Not used (“0” when read, do not write “1”) Timer X mode bits b5 b4 0 0: 0 1: 1 0: 1 1: Timer mode Bi-phase counter mode Event counter mode Pulse width measurement mode CNTR0 polarity selection bit 0 : For event counter mode, rising edge active For interrupt request, falling edge active For pulse width measurement mode, measure “H” period 1 : For event counter mode, falling edge active For interrupt request, rising edge active For pulse width measurement mode, measure “L” period Timer X stop control bit 0 : Timer counting 1 : Timer stopped Fig. 20 Structure of Timer X mode register Timer Y Timer Y is a 16 bit timer with a 16-bit reload latch supporting the following operating modes: (1) Timer mode (3) Event counter mode (5) Pulse period measurement mode (6) H/L pulse width measurement mode These modes can be selected by the timer Y mode register (TYM). In the timer, pulse period- and pulse width measurement modes’ the timer’s count source can be selected by the timer Y count source selection bits. Please refer to Fig. 21. On read or write access to timer Y, note that the high-order and loworder bytes must be accessed in a specific order. Write method When writing to timer Y, write the low-order byte first. The data written is stored in a temporary register which is assigned to the same address as TYL. Next, write the high-order byte. When this is finished, the data is placed in the timer Y high-order reload latch and the low-order byte is transferred from its temporary register to the timer Y low-order reload latch. Read method When reading the timer Y, read the high-order byte first. This causes the timer Y high- and low-order bytes to be transferred to temporary registers being assigned to the same addresses as TYH and TYL. Next, read the low-order byte which is read from the temporary register. This method assures the correct timer value can be read during timer count operation. Timer Y count stop control Regardless of the actual operating mode, timer Y can be stopped by setting the timer Y count stop bit (bit 7 of the timer Y mode register) to “1”. 7630 Group User’s Manual 1-23 +$5':$5( TIMERS 7 0 Timer Y mode register (address 001F16) TYM Timer X count source selection bits b1 b0 0 0 1 1 0: 1: 0: 1: φ divided by 4 φ divided by 16 φ divided by 64 φ divided by 128 Timer Y count source selection bits b3 b2 0 0 1 1 0: 1: 0: 1: φ divided by 2 φ divided by 8 φ divided by 32 φ divided by 64 Timer Y operation mode bits b5 b4 0 0 1 1 0: 1: 0: 1: Timer mode Pulse period measurement mode Event counter mode H/L pulse width measurement mode CNTR1 polarity selection bit 0 : For event counter mode, rising edge active For interrupt request, falling edge active For pulse period measurement mode, refer to falling edges 1 : For event counter mode, falling edge active For interrupt request, rising edge active For pulse period measurement mode, refer to rising edges Timer Y stop control bit 0 : Timer counting 1 : Timer stopped Fig. 21 Structure of timer Y mode register (φ is internal system clock) Operating Modes (1) Timer mode This mode is available with timer X and timer Y. • Count source The count source for timer X and Y is the output of the corresponding clock divider. The division ratio can be selected by the timer Y mode register. • Operation Both timers X and Y are down counters. On a timer underflow, the corresponding timer interrupt request bit will be set to “1”, the contents of the corresponding timer latches will be reloaded to the counters and counting continues. The count direction is determined by the edge polarity and level of count source inputs and may change during the count operation. Refer to the table below. Table 6: Timer X count direction in Bi-phase counter mode P13/TX0 ↑ E dge ↓ E dge L H L H P14/CNTR0 L H L H ↑ E dge ↓ E dg e Count direction Up Down Down Up Down Up Up Down (2) Bi-phase counter mode (quadruplicate) This mode is available with timer X only. • Count source The count sources are P14/CNTR0 and the P13/TX0 pins. • Operation Timer X will count both rising and falling edges on both input pins (see above). Refer to Timer X bi-phase counter mode operation for the timing chart of the bi-phase counter mode. On a timer over- or underflow, the corresponding interrupt request bit will be set to “1” and counting continues. 1-24 7630 Group User’s Manual +$5':$5( TIMERS P13/TX0 input signal P14/CNTR0 input signal TX counter Count direction Down Up Fig. 22 Timer X bi-phase counter mode operation (3) Event counter mode This mode is available with timer X and timer Y. • Count source The count source for timer X is the input signal to the P14/CNTR0 pin and for timer Y the input signal to P15/CNTR1 pin. • Operation The timer counts down. On a timer underflow, the corresponding timer interrupt request bit will be set to “1”, the contents of the corresponding timer latches will be reloaded to the counters and counting continues. The active edge used for counting can be selected by the polarity selection bit of the corresponding pin P14/CNTR0 or P15/CNTR1. These bits are part of TXM (Structure of Timer X mode register) and TYM (Structure of timer Y mode register (f is internal system clock)) registers. • Operation The active edge of input signal to be measured can be selected by CNTR1 polarity selection bit (Fig. 20). When this bit is set to “0”, the time between two consecutive falling edges of the signal input to P15/CNTR1 pin will be measured, when the polarity bit is set to “1”, the time between two consecutive rising edges will be measured. The timer counts down. On detection of an active edge of input signal, the contents of the TY counters will be transferred to temporary registers assigned to the same addresses as TY. At the same time, the contents of TY latches will be reloaded to the counters and counting continues. The active edge of input signal also causes the CNTR1 interrupt request bit to be set to “1”. The measurement result may be obtained by reading timer Y during interrupt service. (4) Pulse width measurement mode This mode is available with timer X only. • Count source The count source is the output of timer X clock divider. The division ratio can be selected by the timer Y mode register. • Operation The timer counts down while the input signal level on P14/CNTR0 matches the active polarity selected by the CNTR 0 polarity selection bit of TXM (Structure of Timer X mode register). On a timer underflow, the timer X interrupt request bit will be set to “1”, the contents of the timer latches are reloaded to the counters and counting continues. When the input level changes from active polarity (as selected), the CNTR0 interrupt request bit will be set to “1.” The measurement result may be obtained by reading timer X during interrupt service. (6) H/L pulse width measurement mode This mode is available with timer Y only. • • Count source The count source is the output of the timer Y’s clock divider. Operation This mode measures both the “H” and “L” periods of a signal input to P15/CNTR1 pin continuously. On detection of any edge (rising or falling) of input signal to P15/CNTR1 pin, the contents of timer Y counters are stored to temporary registers which are assigned to the same addresses as timer Y. At the same time, the contents of timer Y latches are reloaded to the counters and counting continues. The detection of an edge causes the CNTR1 interrupt request bit to be set to “1” as well. The result of measurement may be obtained by reading timer Y during interrupt service. This read access will address the temporary registers. On a timer underflow, the timer Y interrupt request bit will be set to “1”, the contents of timer Y latches will be transferred to the counters and counting continues. (5) Pulse period measurement mode This mode is available with timer Y only. • Count source The count source is the output of timer Y clock divider. 7630 Group User’s Manual 1-25 +$5':$5( TIMERS TIMER 1, TIMER 2, TIMER 3 Timers 1 to 3 are 8-bit timers with 8-bit reload latches and one common pre-divider. Timer 1 can operate in the timer mode only, whereas φ 1 1/8 1/32 1/128 T123M67 timers 2 and 3 can be used to generate a PWM output signal timing as well. Timers 1 to 3 are down count timers. See Fig. 23. “00” “01” “10” “11” T1 latch (8) T1 counter (8) T1 interrupt T2 latch (8) “1” “0” T2 counter (8) “0” “1” T123M1 T123M3 T2 interrupt S Q R T3 latch (8) “1” T123M4 “0” T3 counter (8) “0” “1” T123M1 T3 interrupt S Q R T123M0 S T Q P1D6 T123M1 P16 latch P16/PWM Fig. 23 Block diagram of timers 1 to 3 (φ is internal system clock) Timer 1 The count source of timer 1 is the output of timer 123 pre-divider. The division ratio of the pre-divider can be selected by the pre-divider division ratio bits of timer 123 mode register (T123M). Refer to Timer 123 mode register configuration (f is internal system clock). On a timer 1 underflow, the timer 1 interrupt request bit will be set to “1”. Writing to timer 1 initializes the latch and counter. be selected by the timer count source selection bits of timer 123 mode register (T123M). Writing to timer 2 register affects the reload latch only or both of the reload latch and counter depending on the timer 2 write control bit of T123M. When the timer write control bit is set to “0”, both latch and counter will be initialized simultaneously; when set to “1” only the reload latch will be initialized, on an underflow, the counter will be set to the modified reload value. Writing to timer 3 initializes latch and counter both. Timer 2 or 3 underflow causes the timer 2 or 3 interrupt request bit to be set to “1”. Timers 2 and 3 The count source of timers 2 and 3 can be either the output of the timer 123 pre-divider or the timer 1 underflow. The count source can 1-26 7630 Group User’s Manual +$5':$5( TIMERS 7 0 Timer 123 mode register (address 001916) T123M PWM polarity selection bit 0 : Start on “H” level output 1 : Start on “L” level output PWM output enable bit 0 : PWM output disabled 1 : PWM output enabled Timer 2 write control bit 0 : Latch and counter 1 : Latch only Timer 2 count source selection bit 0 : Timer 1 underflow 1 : Pre-divider output Timer 3 count source selection bit 0 : Timer 1 underflow 1 : Pre-divider output Not used (“0” when read, do not write “1”) Pre-divider division ratio bits b7 b6 0 0 1 1 0: 1: 0: 1: φ divided by 1 φ divided by 8 φ divided by 32 φ divided by 128 Fig. 24 Timer 123 mode register configuration (φ is internal system clock) Operating Modes (1) Timer Mode This mode is available with timers 1 to 3. • Count source For timer 1, the count source is the output of the corresponding pre-divider. For timers 2 and 3, the count source can be separately selected to be either the pre-divider output or timer 1 underflow. Operation The timer counts down. On a timer underflow, the corresponding timer interrupt request bit will be set to “1”, the contents of the corresponding timer latch will be reloaded to the counter and counting continues. (2) PWM Mode This mode is available with timer 2 and 3. • Count source The count source can be separately selected to be either the predivider output or timer 1 underflow. • Operation When the PWM-mode is enabled, timer 2 starts counting. As soon as timer 2 underflows, timer 2 stops and timer 3 starts counting. If bit 0 is set, timer 2 determines the low duration and the initial output level is low. Timer 3 determines the high duration. If bit 0 is zero timer 2 determines the high duration and the initial output level is high. In this case timer 3 determines the low duration. Note: Be sure to configure the P16/PWM pin as an output port before using PWM mode. • • 7630 Group User’s Manual 1-27 +$5':$5( SERIAL I/Os SERIAL I/Os The serial I/O section of 7630 group consists of one clock synchronous and one asynchronous (UART) interface. speeds. Refer to Block diagram of clock synchronous I/O (f is internal system clock). The operation of the clock synchronous serial I/O can be configured by the serial I/O control register SIOCON; refer to Fig. 27. Clock Synchronous Serial I/O (SI/O) The clock synchronous interface allows full duplex communication based on 8 bit word length. The transfer clock can be selected from an internal or external clock. When an internal clock is selected, a programmable clock divider allows eight different transmission φ SIOCON2, 1, 0 Clock divider P23/SRDY SIOCON4 “1” “0” P23 latch Sync. circuit SIOCON6 “1” “0” P22/SCLK SIOCON3 “1” “0” P22 latch SIO counter (3) SIO interrupt P21/SOUT SIOCON3 “1” “0” P21 latch SIO shift register (8) P20/SIN SIOCON3 “1” “0” P20 latch Fig. 25 Block diagram of clock synchronous I/O (φ is internal system clock) (1) Clock synchronous serial I/O operation Either an internal or external transfer clock can be selected by bit 6 of SIOCON. The internal clock divider can be programmed by bits 0 to 2 of SIOCON. Bit 3 of SIOCON determines whether the double function pins P20 to P22 will act as I/O ports or serve as SIO pins. Bit 4 of SIOCON allows the same selection for pin P23. When an internal transfer clock is selected, transmission can be triggered by writing data to the SI/O shift register (SIO, address 001216). After an 8–bit transmission has been completed, the SOUT pin will change to high impedance and the SIO interrupt request bit will be set to “1”. When an external transfer clock is selected, the SIO interrupt request bit will be set to “1” after 8 cycles but the contents of the SI/O shift register continue to be shifted while the transfer clock is being input. Therefore, the clock needs to be controlled externally; the SOUT pin will not change to high impedance automatically. synchronous clock transfer clock write signal to SIO receive enable signal SRDY Serial Output SOUT Serial input SIN D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 SIO interrupt request bit = “1” Note: When an internal clock is selected, SOUT pin will change to high impedance after 8 bits of data have been transmitted. Fig. 26 Timing of clock synchronous SI/O function (LSB first selected) 1-28 7630 Group User’s Manual +$5':$5( SERIAL I/Os 7 0 SIO control register (address 001316) SIOCON Clock divider selection bits b2 b1 b0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0: 1: 0: 1: 0: 1: 0: 1: φ divided by 4 φ divided by 8 φ divided by 16 φ divided by 32 φ divided by 64 φ divided by 128 φ divided by 256 φ divided by 512 P20/SIN, P21/SOUT and P22/SCLK function selection bit 0 : I/O port function 1 : SI/O function P23/SRDY function selection bit 0 : I/O port function 1 : SI/O function Transmission order selection bit 0 : LSB first 1 : MSB first Synchronization clock selection bit 0 : Use external clock 1 : Use internal clock Not used (“0” when read) Fig. 27 Structure of serial I/O control register (φ is internal system clock) Clock Asynchronous Serial I/O (UART) The UART is a full duplex asynchronous transmit/receive unit. The built-in clock divider and baud rate generator enable a broad range of transmission speeds. Please refer to Block diagram of UART. UART mode register (UMOD, Structure of UART mode register) The UART mode register allows to select the transmission and reception format with the following options: • word length: 7, 8 or 9 bits • parity: none, odd or even • stop bits: 1 or 2 It allows to select the prescalers division ratio as well. (1) Description The transmit and receive shift registers have a buffer (consisting of high and low order byte) each. Since the shift registers cannot be written to or read from directly, transmit data is written to the transmit buffer and receive data is read from the receive buffer. A transmit or receive operation will be triggered by the transmit enable bit and receive enable bit of the UART control register UCON (see Structure of UART control register). The double function terminals P25/UTXD, P26/URTS and P24/URXD, P27/UCTS will be switched to the UART pins automatically. UART baud rate generator (UBRG) This 8 bit register allows to select the baud rate of the UART (see above). Set this register to the desired value before enabling reception or transmission. (2) Baud rate selection The baud rate of transmission and reception is determined by the setting of the prescaler and the contents of the UART baud rate generator register. It is calculated by: UART control register (UCON, Structure of UART control register) The UART control register consists of four control bits (bit 0 to bit 3) which allow to control reception and transmission. φ b = ---------------------------------16 ⋅ p ⋅ ( n + 1 ) where p is the division ratio of the prescaler and n is the contents of the UART baud rate generator register. The prescalers division ration can be selected by the UART mode register (see page 1-31). UART status register (USTS, Structure of UART status register) The read-only UART status register consists of 7 bits (bit 0 to bit 6) which indicate the operating status of the UART function and various errors. 7630 Group User’s Manual 1-29 +$5':$5( SERIAL I/Os (3) Handshaking signals When used as transmitter, the UART will recognize the clear-to-send signal via P27/UCTS terminal for handshaking. When used as receiver it will issue a request-to-send signal through P26/URTS pin. Clear-to-send input When used as a transmitter (transmit enable bit set to “1”), the UART starts transmission after recognizing “L” level on P27/UCTS. After started, the UART will continue to transmit regardless of the actual level of P27/UCTS or status of the transmit enable bit. Request-to-send output The UART controls the P26/URTS output according to the following conditions. Table 7: Output control conditions Condition Receive enable bit is set to “1” Reception completed during receive enable bit set to “1” Start bit (falling edge) detected Receive enable bit is set to “0” before reception started Hardware reset Receive initialization bit is set to “1” “H” “L” P26/URTS Data bus UART control register UART status register Transmit buffer (9) Transmit buffer empty interrupt request Transmit buffer empty flag φ 1 1/8 1/32 “00” “01” “10” UMOD2, 1 UMOD7, 6 UBRG (8) Bit counter Transmit shift register (9) UMOD4,3,2 Transmission control circuit Reception control circuit UMOD7, 6 Bit counter Receive shift register (9) Transmit register empty interrupt request P25/UTXD 1/256 “11” Transmit register empty flag P27/UCTS P26/URTS Receive error interrupt request P24/URXD Receive error flags Receive buffer (9) Receive buffer full interrupt request Receive buffer full flag Data bus Fig. 28 Block diagram of UART 1-30 7630 Group User’s Manual +$5':$5( SERIAL I/Os 7 0 UART mode register UMOD (address 002016) Not used (“0” when read, do not write “1”) Clock divider selection bits b2 b1 0 0 1 1 0: 1: 0: 1: φ divided by 1 φ divided by 8 φ divided by 32 φ divided by 256 Stop bits selection bit 0 : One stop bit 1 : Two stop bits Parity selection bit 0 : Even parity 1 : Odd parity Parity enable bit 0 : Parity disabled 1 : Parity enabled UART word length selection bits b7 b6 0 0 1 1 0: 1: 0: 1: 7 bits 8 bits 9 bits Not used Fig. 29 Structure of UART mode register 7 0 UART control register UCON (address 002216) Transmit enable bit 0 : Transmit disabled (an ongoing transmission will be finished correctly) 1 : Transmit enabled Receive enable bit 0 : Receive disabled (an ongoing reception will be finished correctly) 1 : Receive enabled Transmission initialization bit 0 : No action 1 : Clear transmit buffer full flag and transmit shifter full flag, set the transmit status register bits and stop transmission Receive initialization bit 0 : No action 1 : Clear receive status flags and the receive enable bit Not used (“0” when read, do not write “1”) Fig. 30 Structure of UART control register 7630 Group User’s Manual 1-31 +$5':$5( SERIAL I/Os 7 0 UART status register (address 002316) USTS Transmission register empty flag 0 : Register full 1 : Register empty Transmission buffer empty flag 0 : Buffer full 1 : Buffer empty Receive buffer full flag 0 : Buffer full 1 : Buffer empty Receive parity error flag 0 : No parity error detected 1 : Parity error detected Receive framing error flag 0 : No framing error detected 1 : Framing error detected Receive overrun flag 0 : No overrun detected 1 : Overrun detected Receive error sum flag 0 : No error detected 1 : Error detected Not used (“0” when read) Note: this register is read only; writing does not affect its contents. Fig. 31 Structure of UART status register 1-32 7630 Group User’s Manual +$5':$5( CAN MODULE CAN MODULE The CAN (Controller Area Network) interface of the 7630 group complies with the 2.0B specification, enabling reception and transmission of frames with either 11- or 29- bit identifier length. Refer to Fig. 33 for a block diagram of the CAN interface. The programmer’s interface to the CAN module is formed by three status/control registers (Fig. 34, Fig. 35, Fig. 36), two bus timing control registers (Fig. 37 Fig. 38), several registers for acceptance filtering (Fig. 39), the transmit and receive buffer registers (Fig. 40) and one dominant level control bit (Fig. 24). CAN Bus Timing Control Each bit-time consists of four different segments (see Fig. 32): • Synchronization segment (SS), • Propagation time segment (PTS), • Phase buffer segment 1 (PBS1) and • Phase buffer segment 2 (PBS2). Bit-time SS PTS PBS1 PBS2 Baud Rate Selection A programmable clock prescaler is used to derive the CAN module’s basic clock from the internal system clock frequency (φ). Bit 0 to bit 3 of the CAN bus timing control register represent the prescaler allowing a division ratio from 1 to 1/16 to be selected. So the CAN module basic clock frequency fCANB can be calculated as follows: Sample point Fig. 32 Bit time of CAN module The first of these segments is of fixed length (one Time Quantum) and the latter three can be programmed to be 1 to 8 Time Quanta by the CAN bus timing control register 1 and 2 (see Fig. 37 and Fig. 38). The whole bit-time has to consist of minimum 8 and maximum 25 Time Quanta. The duration of one Time Quantum is the cycle time of fCANB. For example, assuming φ = 5 MHz, p = 0, one Time Quantum will be 200 ns long. This allows the maximum transmission rate of 625 kb/s to be reached (assuming 8 Time Quanta per bit-time). φ f CANB = ----------p+1 where p is the value of the prescaler (selectable from 1 to 15). The effective baud rate of the CAN bus communication depends on the CAN bus timing control parameters and will be explained below. Data bus Polarity control register CAN status/control registers Bus timing control register Acceptance mask register Acceptance code register Receive buffer 1 P31/CTX P32/CRX Protocol controller Transmit buffer Wake-up logic CAN wake-up Acceptance filter Receive buffer 2 Data bus Fig. 33 Block diagram of CAN module 7630 Group User’s Manual 1-33 +$5':$5( CAN MODULE 7 0 CAN transmit control register (address 003016) CTRM Sleep control bit 0 : CAN module in normal mode 1 : CAN module in sleep mode Reset/configuration control bit 0 : CAN module in normal mode 1 : CAN module in configuration mode (plus reset when write) Port double function control bit 0 : P31/CTX serves as I/O port 1 : P31/CTX serves as CTX output port Transmit request bit 0 : No transmission requested 1 : Transmission requested (write “0” has no effect) Not used (no operation, “0” when read) Transmit buffer control bit 0 : CPU access possible 1 : No CPU access (write “0” has no effect, while CTRM(3) = 1) Not used (no operation, “0” when read) Transmit status bit (read only) 0 : CAN module idle or receiving 1 : CAN module transmitting Fig. 34 Structure of CAN transmit control register 7 0 CAN receive control register (address 003D16) CREC Receive buffer control bit 0 : Receive buffer empty 1 : Receive buffer full (write “1” has no effect) Receive status bit (read only) 0 : CAN module idle or transmitting 1 : CAN module receiving Not used (do not write “1”, read as “0”) Auto-receive disable bit 0 : Auto-receive enabled 1 : Auto-receive disabled Note: Suppresses reception of self initiated/transmitted frames Not used (do not write “1”, “0” when read) Fig. 35 Structure of CAN receive control register 1-34 7630 Group User’s Manual +$5':$5( CAN MODULE 7 0 CAN transmit abort register (address 003E16) CABORT Transmit abort control bit 0 : No transmit abort request 1 : Transmit abort request (write “1” has no effect, while CTRM(3) = 0) Not used (No operation, “0” when read) Fig. 36 Structure of CAN transmit abort register 7 0 CAN bus timing control register 1 (address 003116) CBTCON1 Prescaler division ratio selection bits b3 b2 b1 b0 0 0 0 0: 0 0 0 1: 0 0 1 0: … 1 1 1 0: 1 1 1 1: φ divided by 1 φ divided by 2 φ divided by 3 φ divided by 15 φ divided by 16 Sampling control bit 0 : One sample per bit 1 : Three sample per bit Propagation time duration control bits b7 b6 b5 0 0 0: 0 0 1: … 1 1 0: 1 1 1: Fig. 37 Structure of CAN bus timing control register 1 One Time Quantum Two Time Quanta Seven Time Quanta Eight Time Quanta 7630 Group User’s Manual 1-35 +$5':$5( CAN MODULE 7 0 CAN bus timing control register 2 (address 003216) CBTCON2 Phase buffer segment 1 duration control bits b2 b1 b0 0 0 0: One Time Quantum 0 0 1: Two Time Quanta … 1 1 0: Seven Time Quanta 1 1 1 : Eight Time Quanta Phase buffer segment 2 duration control bits b5 b4 b3 0 0 0: One Time Quantum 0 0 1: Two Time Quanta … 1 1 0: Seven Time Quanta 1 1 1 : Eight Time Quanta Synchronization jump width control bits b7 b6 0 0 1 1 0 1 0 1 : : : : One Time Quantum Two Time Quanta Three Time Quanta Four Time Quanta Fig. 38 Structure of CAN bus timing control register 2 name 7 CAC0 Not used Not used Not used CSID10 CAC1 CSID5 CSID4 CSID3 CSID2 0 CSID6 address 003316 003416 003516 003616 003716 Acceptance code registers: CSID9 CSID1 CSID8 CSID0 CEID16 CEID8 CEID0 CSID7 Not used Not used CEID15 CEID7 CEID14 CEID6 CAC2 Not used Not used Not used Not used CEID17 CAC3 CAC4 CEID13 CEID5 CEID12 CEID4 CEID11 CEID3 CEID10 CEID2 CEID9 CEID1 Not used Not used Select the bit pattern of identifiers which allows to pass acceptance filtering. 7 CAM0 Not used Not used Not used MSID10 CAM1 MSID5 MSID4 MSID3 MSID2 0 MSID6 Acceptance mask registers: MSID9 MSID1 MSID8 MSID0 MEID16 MEID8 MEID0 MSID7 003816 003916 003A16 003B16 003C16 Not used Not used MEID15 MEID7 MEID14 MEID6 CAM2 Not used Not used Not used Not used MEID17 CAM3 CAM4 MEID13 MEID5 MEID12 MEID4 MEID11 MEID3 MEID10 MEID2 MEID9 MEID1 Not used Not used 0 : Mask identifier bit (do not care) 1 : Compare identifier bit with acceptance code register bit (Not used: write to “0”) Fig. 39 Structure of CAN mask and code registers 1-36 7630 Group User’s Manual +$5':$5( CAN MODULE name CTB0, CRB0 CTB1, CRB1 CTB2, CRB2 CTB3, CRB3 CTB4, CRB4 CTB5, CRB5 CTB6, CRB6 CTB7, CRB7 CTB8, CRB8 CTB9, CRB9 CTBA, CRBA CTBB, CRBB CTBC, CRBC CTBD, CRBD 7 Not used Not used Not used SID5 SID4 SID3 0 SID10 SID2 SID9 SID1 EID17 EID9 EID1 DLC3 SID8 SID0 EID16 EID8 EID0 DLC2 SID7 RTR/SRR offset 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 SID6 IDE EID14 EID6 r1 DLC0 Not used Not used Not used Not used EID13 EID5 EID12 EID4 EID11 EID3 EID10 EID2 r0 EID15 EID7 RTR DLC1 Not used Not used Not used Data byte 0 Data byte 1 Data byte 2 Data byte 3 Data byte 4 Data byte 5 Data byte 6 Data byte 7 Calculate the actual address as follows: TxD buffer address = 004016 + offset RxD buffer address = 005016 + offset (Not used: write to “0”) Fig. 40 Structure of CAN transmission and reception buffer registers Note 1: All CAN related SFRs must not be written in ”CAN sleep” mode. 7630 Group User’s Manual 1-37 +$5':$5( A-D CONVERTER A-D CONVERTER The A-D converter uses the successive approximation method with 8 bit resolution. The functional blocks of the A-D converter are described below. Refer to Block diagram of A-D converter. Channel Selector The channel selector selects one of ports P00/AN0 to P07/AN7, and inputs its voltage to the comparator. Comparison Voltage Generator The comparison voltage generator divides the voltage between AVSS and VREF by 256, and outputs the divided voltage. A-D conversion register AD The A-D conversion register is a read-only register that stores the result of an A-D conversion. This register must not be read during an A-D conversion. Data bus b7 A-D control register 3 b0 A-D control circuit P00/AN0 channel selector Comparator A-D interrupt request A-D conversion register P07/AN7 comparison voltage generator VREF/Input switch bit VREF AVSS Fig. 41 Block diagram of A-D converter A-D control register (Structure of A-D control register) The A-D control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 3 signals the completion of an A-D conversion. The value of this bit remains “0” during an A-D conversion, and changes to “1” when an A-D conversion ends. Writing “0” to this bit starts the A-D conversion. Bit 4 is the VREF/Input switch bit. 1-38 7630 Group User’s Manual +$5':$5( A-D CONVERTER 7 0 A-D control register (address 001516) ADCON Analog input pin selection bits b2 b1 b0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0: 1: 0: 1: 0: 1: 0: 1: P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 A-D conversion completion bit 0 : Conversion in progress 1 : Conversion completed VREF/Input switch bit 0 : Off 1 : On Not used (“0” when read, do not write “1”) Fig. 42 Structure of A-D control register A-D Converter Operation The comparator and control circuit reference an analog input voltage with the reference voltage, then stores the result in the A-D conversion register. When an A-D conversion is complete, the control circuit sets the A-D conversion completion bit and the A-D interrupt request bit to “1”. The result of A-D conversion can be obtained from the A-D conversion register, AD (address 001416). Note that the comparator is linked to a capacitor, so set f(XIN) to 500 kHz or higher during A-D conversion. 7630 Group User’s Manual 1-39 +$5':$5( WATCHDOG TIMER WATCHDOG TIMER The watchdog timer consists of two separate counters: one 7-bit counter (WDH) and one 4-bit counter (WDL). Cascading both counters or using the high-order counter allows only to select the time-out from either 524288 or 32768 cycles of the internal clock φ. Refer to Fig. 43 and Fig. 44. Both counters are addressed by the same watchdog timer register (WDT). When writing to this register, both counters will be set to the following default values: • the high-order counter will be set to address 7F16 • the low-order counter will be set to address F16 regardless of the data written to the WDT register. Reading the watchdog timer register will return the corresponding control bit status, not the counter contents. φ 1/256 WDL counter (4) “F16” “0” WDT7 “7F16” Once the WDT register is written to, the watchdog timer starts counting down and the watchdog timer interrupt is enabled. Once it is running, the watchdog timer cannot be disabled or stopped except by reset. On a watchdog timer underflow, a non-maskable watchdog timer interrupt will be requested. To prevent the system being stopped by STP instruction, this instruction can be disabled by the STP instruction disable bit of WDT register. Once the STP instruction is disabled, it cannot be enabled again except by RESET. “1” WDH counter (7) WDT interrupt WDT register (8) Fig. 43 Block diagram of watchdog timer 7 0 Watchdog timer register (address 002E16) WDT Not used (undefined when read) Stop instruction disable bit 0 : Stop instruction enabled 1 : Execute two NOP instructions instead (once this bit is set to “1” it can‘t be cleared to “0” again, except on RESET.) Upper byte count source selection bit 0 : Underflow of the low order counter 1 : φ divided by 256 Fig. 44 Structure of watchdog timer register (φ is internal clock system) 1-40 7630 Group User’s Manual +$5':$5( RESET CIRCUIT RESET CIRCUIT The 7630 group is reset according to the sequence shown in Fig. 46. It starts program execution from the address formed by the contents of the addresses FFFB16 and FFFA16, when the RESET pin is held at “L” level for more than 2 µs while the power supply voltage is in the recommended operating condition and then returned to “H” level. Refer to Fig. 45 for an example of the reset circuit. Power on Power source voltage 0V Reset input voltage 0V 0.8V 4.0V VCC 1 5 M51953AL 4 0.1µF RESET 3 VSS 7630 group Fig. 45 Example of reset circuit XIN RESET internal reset Address Data ? ? ? ? ? ? ? ? ? ? FFFA16 ADL FFFB16 ADL, ADH ADH … 1st op code 8192 cycles of XIN (T1, T2) 28 to 34 cycles of XIN 24 cycles of XIN 20 cycles of XIN Fig. 46 Reset sequence 7630 Group User’s Manual 1-41 +$5':$5( RESET CIRCUIT Register CPU mode reg. Interrupt request reg. A Interrupt request reg. B Interrupt request reg. C Interrupt control reg. A Interrupt control reg. B Interrupt control reg. C Port P0 reg. Port P0 direction reg. Port P1 reg. Port P1 direction reg. Port P2 reg. Port P2 direction reg. Port P3 reg. Port P3 direction reg. Port P4 reg. Port P4 direction reg. Serial I/O control reg. A-D control reg. Timer 1 Timer 2 Timer 3 Timer 123 mode reg. Timer XL Address 000016 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001316 001516 001616 001716 001816 001916 001A16 Register contents 4816 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0816 FF16 0116 FF16 4016 FF16 Register Timer XH Timer YL Timer YH Timer X mode reg. Timer Y mode reg. UART mode reg. UART control reg. UART status reg. Port P0 pull-up control reg. Port P1 pull-up control reg. Port P2 pull-up control reg. Port P3 pull-up control reg. Port P4 pull-up/down control reg. Interrupt polarity selection reg. Watchdog timer reg. Polarity control reg. CAN transmit control reg. CAN bus timing control reg. 1 CAN bus timing control reg. 2 CAN receive control reg. CAN transmit abort reg. Processor status reg. Program counter (high-order byte) Program counter (low-order byte) Address 001B16 001C16 001D16 001E16 001F16 002016 002216 002316 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003D16 003E16 (PS) (PCH) (PCL) Register contents FF16 FF16 FF16 0016 0016 0010 0016 0710 0016 0016 0016 0016 0016 0016 3F16 0016 0216 0016 0016 0016 0016 0416 contents of FFFB16 contents of FFFA16 Note: The contents of RAM and registers other than the above registers are undefined after reset; thus software initialization is required. Fig. 47 Internal status of microcomputer after reset 1-42 7630 Group User’s Manual +$5':$5( CLOCK GENERATING CIRCUIT CLOCK GENERATING CIRCUIT The 7630 group is equipped with an internal clock generating circuit. Please refer to Fig. 48 for a circuit example using a ceramic resonator or quartz crystal oscillator. For the capacitor values, refer to the manufacturers recommended parameters which depend on each oscillators characteristics. When using an external clock, input it to the XIN pin and leave XOUT open. XIN XOUT CIN COUT Fig. 48 Ceramic resonator circuit . Oscillation Control The 7630 group has two low power modes: the stop and the wait mode. Stop mode The microcomputer enters the stop mode by executing the STP instruction. The oscillator stops with the internal clock φ at “H” level. Timers 1 and 2 will be cascaded and initialized by their reload latches contents. The count source for timer 1 will be set to f(XIN)/16. Oscillation is restarted if an external interrupt is accepted or at reset. When using an external interrupt, the internal clock φ remains at “H” level until timer 2 underflows allowing a time-out until the clock oscil- lation becomes stable. When using reset, a fixed time-out will be generated allowing oscillation to stabilize. Wait mode The microcomputer enters the wait mode by executing the WIT instruction. The internal clock ø stops at “H” level while the oscillator keeps running. Recovery from wait mode can be done in the same way as from stop mode. However, the time-out period mentioned above is not required to return from wait-mode, thus no such time-out mechanism has been implemented. Note: Set the interrupt enable bit of the interrupt source to be used to return from stop or wait mode to “1” before executing STP or WIT instruction. XOUT 1/4 “1” XIN 1/2 “0” CPUM6 Internal clock for peripherals Interrupt request Interrupt disable flag RESET STP Delay R S R Q STP S Q D T Q φ 2 R STP Oscillator countdown (timer 1 and 2) WIT S R S Q D T Q φ Internal clock for CPU Q P2 Fig. 49 Block diagram of clock generating circuit 7630 Group User’s Manual 1-43 +$5':$5( DATA REQUIRED FOR MASK ORDERS DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: 1 Mask ROM Order Confirmation Form 2 Mark Specification Form 3 Contents of Mask ROM, in EPROM form (three identical copies) The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Fig. 50 is recommended to verify programming. Programming with PROM programmer PROM PROGRAMMING METHOD The built-in PROM of the blank One Time PROM version and built-in EPROM version can be read or programmed with a general purpose PROM programmer using a special programming adapter. Set the address of PROM programmer to the user ROM area. For the programming adapter type name, please refer to the following table: Table 8: Programming adapter name MCU type One Time PROM EPROM Package 44P6N-A 80D0 Programming adapter type PCA7430 Functional test in target unit PCA7431 Note on screening: The screening temperature is far higher than the storage temperature. Never subject the device to 150 °C exceeding 100 hours. Fig. 50 Programming and testing of One Time PROM version Screening *(Note) (150 °C for 40 hours) Verification with PROM programmer 1-44 7630 Group User’s Manual +$5':$5( ABSOLUTE MAXIMUM RATING Table 9: ABSOLUTE MAXIMUM RATINGS Symbol VCC VI Output voltage VO Pd Topr Tstg Power dissipation Operating temperature Storage temperature Power source voltage Input voltage P00—P07, P11—P17, P20—P27, P30—P34, P40—P47, RESET, XIN P00—P07, P12—P17, P20—P27, P30—P34, P40—P47, XOUT Parameter Conditions Ratings –0.3 to 7.0 –0.3 to VCC + 0.3 Unit V V All voltages with respect to VSS and output transistors are “off”. –0.3 to VCC + 0.3 Ta = 25 °C 500 –40 to 85 –60 to 150 V mW °C °C Table 10: RECOMMENDED OPERATING CONDITIONS (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = – 40 to 85 °C unless otherwise noted) Limits Symbol VCC VSS VIH VIL Parameter min. Power source voltage “H” Input voltage “L” Input voltage “H” sum peak output current “H” sum average output current “L” sum peak output current “L” sum average output current “H” peak output current “H” average output current “L” peak output current “L” average output current input current at overvoltage condiP11—P17, P20—P27, tion P30—P34, P40—P47 (VI > VCC) total input current at overvoltage condition (VI > VCC) Timer input frequency (based on 50 % duty) Unit typ. 5.0 0 max. 5.5 V V VCC 0.2 · VCC –80 –40 80 40 –10 –5 10 5 1 V V mA mA mA mA mA mA mA mA mA 4.0 P00—P07, P11—P17, P20—P27, P30—P34, P40—P47, RESET, XIN P00—P07, P11—P17, P20—P27, P30—P34, P40—P47, RESET, XIN P00—P07, P12—P17, P20—P27, P30—P34, P40—P47 0.8 · VCC 0 ∑ IOH (peak) ∑ IOH (avg) ∑ IOL (peak) ∑ IOL (avg) IOH (peak) IOH (avg) IOL (peak) IOL (avg) IIO ∑ IIO f(CNTR) P11—P17, P20—P27, P30—P34, P40—P47 P14/CNTR0, P15/CNTR1 (except bi-phase counter mode) P13/TX0, P14/CNTR0 (bi-phase counter mode) 16 mA f(XIN)/16 f(XIN)/32 10 MHz MHz MHz f(XIN) Clock input oscillation frequency 7630 Group User’s Manual 1-45 +$5':$5( ELECTRICAL CHARACTERISTICS Table 11: ELECTRICAL CHARACTERISTICS (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = – 40 to 85 °C unless otherwise noted) Limits Symbol Parameter Test conditions min. P00—P07, P12—P17, P20—P27, P30—P34, P40—P47 P00—P07, P12—P17, P20—P27, P30—P34, P40—P47 P11/INT0, P12/INT1, P13/TX0, P14/CNTR0, P15/CNTR1,P20/SIN, P22/SCLK, P26/URTS, P27/UCTS, P32/CRX, RESET P00—P07, P11—P17, P20—P27, P30—P34, P40—P47, RESET XIN P00—P07, P11—P17, P20—P27, P30—P34, P40—P47, RESET XIN P32, P40—P47 P00—P07, P11—P17, P20—P27, P30—P34, P40—P47, RESET typ. max. Unit VOH “H” output voltage IOH = –5 mA 0.8 · VCC V VOL “L” output voltage IOL = 5 mA 2.0 V VT+ – VT– Hysteresis 0.5 V IIH “H” input current VI = VCC 5 µA µA µA µA IIH “H” input current VI = VCC 4 IIL “L” input current VI = VSS –5 IIL IIH “L” input current “H” input current VI = VSS VI = VCC Pull-Down = ’On’ VI = VSS Pull-Up = ’On’ When clock stopped high speed mode, f(XIN) = 8MHz, VCC = 5V, output transistors off, CAN module running, ADC running high speed mode, f(XIN) = 8MHz, VCC = 5V, output transistors off, CAN module stopped, ADC running middle speed mode, f(XIN) = 8MHz, VCC = 5V, output transistors off, CAN module running, ADC running middle speed mode, wait mode, f(XIN) = 8MHz, VCC = 5V, output transistors off, CAN module stopped, ADC stopped stop mode, f(XIN) = 0MHz, VCC = 5V, Ta = 25°C stop mode, f(XIN) = 0MHz, VCC = 5V, Ta = 85°C –4 20 200 µA IIL “L” input current -200 -20 µA VRAM RAM hold voltage 2.0 V 11.0 18.0 mA 9.0 16.0 mA ICC Power source current 6.0 11.0 mA 2.0 mA 0.1 1.0 10.0 µA µA 1-46 7630 Group User’s Manual +$5':$5( A-D CONVERTER CHARACTERISTICS Table 12: A-D converter characteristics (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Limits Symbol — — tCONV VREF IREF RLADDER IIAN Resolution Absolute accuracy Conversion time Reference input voltage Reference input current Ladder resistor value Analog input current VI = VSS to VCC VCC = VREF = 5.12 V high–speed mode middle–speed mode Parameter Test conditions min. typ. ±1.0 106 424 2.0 150 35 0.5 5.0 max. 8 ±2.5 108 432 VCC 200 Unit Bit LSB tC(XIN) tC(XIN) V µA kΩ µA 7630 Group User’s Manual 1-47 +$5':$5( TIMING REQUIREMENTS Table 13: Timing requirements (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Limits Symbol Parameter min. tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0, CNTR1 input cycle time (except bi-phase counter mode) CNTR0 input cycle time (bi-phase counter mode) CNTR0, CNTR1 input “H” pulse width (except bi-phase counter mode) CNTR0 input “H” pulse width (bi-phase counter mode) CNTR0, CNTR1 input “L” pulse width (except bi-phase counter mode) CNTR0 input “L” pulse width (bi-phase counter mode) tL(CNTR0-TX0) tC(TX0) tWH(TX0) tWL(TX0) tWH(INT) tWL(INT) tC(SCLK) tWH(SCLK) tWL(SCLK) tSU(SIN–SCLK) tH(SCLK–SIN) Lag of CNTR0 and TX0 input edges (bi-phase counter mode) TX0 input cycle time (bi-phase counter mode) TX0 input “H” pulse width (bi-phase counter mode) TX0 input “L” pulse width (bi-phase counter mode) INT0, INT1 input “H” pulse width INT0, INT1 input “L” pulse width Serial I/O clock input cycle time Serial I/O clock input “H” pulse width Serial I/O clock input “L” pulse width Serial I/O input setup time Serial I/O input hold time 2 100 37 37 1600 2000 800 1000 800 1000 500 3200 1600 1600 460 460 8 · tC(XIN) 4 · tC(XIN) 4 · tC(XIN) 200 150 typ. max. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tC(CNTR) tWH(CNTR) tWL(CNTR) 1-48 7630 Group User’s Manual +$5':$5( SWITCHING CHARACTERISTICS Table 14: Switching characteristics (VCC=4.0 to 5.5 V, VSS=AVSS=0 V, Ta=–40 to 85 °C unless otherwise noted) Limits Symbol Parameter min. tWH(SCLK) tWL(SCLK) tD(SCLK–SOUT) tV(SCLK–SOUT) tR(SCLK) tR(CMOS) tF(CMOS) Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time Serial I/O output valid time Serial I/O clock output rise time CMOS output rise time CMOS output fall time 10 10 0 0.5 · tC(SCLK) – 50 0.5 · tC(SCLK) – 50 50 50 50 50 50 typ. max. ns ns ns ns ns ns ns Unit Measurement output pin 100 pF CMOS output Fig. 51 Circuit for measuring output switching characteristics 7630 Group User’s Manual 1-49 +$5':$5( TIMING DIAGRAM TIMING DIAGRAM tC(TX0) tWH(TX0) TX0 0.8·VCC 0.2·VCC tWL(TX0) tC(CNTR) tWH(CNTR) CNTR0, CNTR1 0.8·VCC 0.2·VCC tWL(CNTR) tWH(INT) INT0, INT1 0.8·VCC 0.2·VCC tWL(INT) tWL(RESET) RESET 0.2·VCC tC(XIN) tWH(XIN) XIN 0.8·VCC 0.2·VCC tWL(XIN) tC(SCLK) tF SCLK 0.2·VCC tWL(SCLK) tR 0.8·VCC tWH(SCLK) tSU(SIN-SCLK) SIN 0.8·VCC 0.2·VCC tH(SCLK-SIN) tD(SCLK-SOUT) SOUT tV(SCLK-SOUT) Fig. 52 Timing diagram 1-50 7630 Group User’s Manual CHAPTER 2 APPLICATION 2.1 I/O Ports 2.2 Interrupts 2.3 Timers 2.4 Controller Area Network (CAN) module 2.5 Serial I/O 2.6 A-D converter 2.7 Watchdog timer 2.8 Reset 2.9 Oscillation circuit 2.10 Development support tools 2.11 Built-in PROM version APPLICATION 2.1 I/O ports 2.1 I/O ports 2.1.1 Memory map of I/O ports 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 002816 002916 002A16 002B16 002C16 002F16 Port P0 register (P0) Port P0 direction register (P0D) Port P1 register (P1) Port P1 direction register (P1D) Port P2 register (P2) Port P2 direction register (P2D) Port P3 register (P3) Port P3 direction register (P3D) Port P4 register (P4) Port P4 direction register (P4D) Port P0 pull-up control register (PUP0) Port P1 pull-up control register (PUP1) Port P2 pull-up control register (PUP2) Port P3 pull-up control register (PUP3) Port P4 pull-up/down control register (PUP4) Polarity control register (PCON) Fig. 2.1.1 Memory map of I/O port related registers 2-2 7630 Group User’s Manual APPLICATION 2.1 I/O ports 2.1.2 Related registers Port Pi register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi register (Pi) (i = 0, 1, 2, 3, 4) [Address : 000816, 000A16, 000C16, 000E16, 001016] B 0 1 2 3 4 5 6 7 Port Pi0 Port Pi1 Port Pi2 Port Pi3 Port Pi4 Port Pi5 Port Pi6 Port Pi7 Name Function • In output mode Write Port latch Read • In input mode Write : Port latch Read : Value of pins At reset R W 0 0 0 0 0 0 0 0 Note: The bits corresponding to P10, P35, P36 and P37 are reserved (“0” when read, don't write “1”). Fig. 2.1.2 Structure of Port Pi register (i = 0, 1, 2, 3, 4) Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4) [Address : 000916, 000B16, 000D16, 000F16, 001116] B 0 1 2 3 4 5 6 7 Name Port Pi direction register Function 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode At reset R W 0 0 0 0 0 0 0 0 Note: The direction control bits corresponding to P10, P11, P35, P36 and P37 are reserved (“0” when read, don't write “1”). Fig. 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4) 7630 Group User’s Manual 2-3 APPLICATION 2.1 I/O ports Port Pi pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi pull-up control register (PUPi) (i = 0, 2) [Address : 002816, 002A16] B 0 1 Name Pi0 pull-up transistor control bit Pi1 pull-up transistor control bit 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up Function At reset R W 0 0 0 0 0 0 0 0 2 Pi2 pull-up transistor control bit 3 4 5 6 7 Pi3 pull-up transistor control bit Pi4 pull-up transistor control bit Pi5 pull-up transistor control bit Pi6 pull-up transistor control bit Pi7 pull-up transistor control bit Fig. 2.1.4 Structure of Port Pi pull-up register (i = 0, 2) Port P1 pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Port P1 pull-up control register (PUP1) [Address : 002916] B Name Function At reset R W 0 Not used (“0” when read, don't write “1”.) 1 2 3 4 5 6 7 P12 pull-up transistor control bit P13 pull-up transistor control bit P14 pull-up transistor control bit P15 pull-up transistor control bit P16 pull-up transistor control bit P17 pull-up transistor control bit 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 0 0 0 0 0 0 0 Fig. 2.1.5 Structure of Port P1 pull-up register 2-4 7630 Group User’s Manual APPLICATION 2.1 I/O ports Port P3 pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Port P3 pull-up control register (PUP3) [Address : 002B16] B 0 1 2 3 4 Name P30 pull-up transistor control bit P31 pull-up transistor control bit P32 pull-up/down transistor control bit P33 pull-up transistor control bit P34 pull-up transistor control bit 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up/down 1 : Pull-up/down (Note) 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up Function At reset R W 0 0 0 0 0 0 0 0 5 Not used (“0” when read, don't write “1”.) 6 7 Note: Enables the pull-transistor towards the CAN module recessive level. This level depends on the CAN module dominant level control bit (bit 1 of the Polarity control register [address: 002F16] ). Fig. 2.1.6 Structure of Port P3 pull-up control register Port P4 pull-up/down control register b7 b6 b5 b4 b3 b2 b1 b0 Port P4 pull-up/down control register (PUP4) [Address : 002C16] B 0 1 2 3 4 5 6 7 Name P40 pull-up/down transistor control bit P41 pull-up/down transistor control bit P42 pull-up/down transistor control bit P43 pull-up/down transistor control bit P44 pull-up/down transistor control bit P45 pull-up/down transistor control bit P46 pull-up/down transistor control bit P47 pull-up/down transistor control bit Function 0 : No pull-up/down 1 : Pull-up/down (Note) 0 : No pull-up/down 1 : Pull-up/down (Note) 0 : No pull-up/down 1 : Pull-up/down (Note) 0 : No pull-up/down 1 : Pull-up/down (Note) 0 : No pull-up/down 1 : Pull-up/down (Note) 0 : No pull-up/down 1 : Pull-up/down (Note) 0 : No pull-up/down 1 : Pull-up/down (Note) 0 : No pull-up/down 1 : Pull-up/down (Note) At reset R W 0 0 0 0 0 0 0 0 Note: Enables the pull-transistor towards the passive polarity of key-on wake-up interrupt. This level depends on the Key-on wake-up polarity control bit (bit 0 of the Polarity control register [address: 002F16] ). Fig. 2.1.7 Structure of Port P4 pull-up/down control register 7630 Group User’s Manual 2-5 APPLICATION 2.1 I/O ports Polarity control register b7 b6 b5 b4 b3 b2 b1 b0 Polarity control register (PCON) [Address : 002F16] B 0 1 Name Key-on wake-up polarity control bit CAN module dominant level control bit (Note) Function 0: Low level active (P4 pull-up) 1: High level active (P4 pull-down) 0: Low level dominant (P32 pull-up) 1: High level dominant (P32 pull-down) At reset R W 0 0 ? ? ? ? ? ? 2 3 4 Not used (undefined when read.) 5 6 7 Note: The selected dominant level also controls the polarity of the pull-transistor enabled by the P32 pull-up/down transistor control bit (bit 2 of the Port P3 pull-up control register), the transistor pulling toward the recessive level is selected. Fig. 2.1.8 Structure of Polarity control register 2-6 7630 Group User’s Manual APPLICATION 2.1 I/O ports 2.1.3 Overvoltage conditions at digital input ports This section describes how to use digital input ports of the 7630 group at overvoltages. The terms over voltage refer to voltage levels beyond V CC+0.3V. When subjected to such input voltage levels, the builtin protection circuit of the input port attempts to limit the input voltage in order to avoid permanent damage to the device. This condition causes input current to the port. The built-in protection circuit tolerates input currents up to specified limits (refer to “ 3.1 Electrical characteristics ”). The input current levels must be limited by appropriate design of the application circuit connected to the coresponding port. Figure 2.1.9 shows an example circuit. VCC MCU R VIN VP Protection circuit Internal circuits VSS Fig. 2.1.9 External circuit example applying overvoltage to digital inputs Assume V IN the voltage to be connected to the MCU. The resistor R limits the input current to satisfy the “recommended operatiing conditions”. For an estimation of the resistor, the port voltage V P s hould be assumed to be V CC a t overvoltage (VIN > VCC +0.3V). To determine the appropriate resistor size refer to the below: V IN(max.) – V CC R≥ (VIN > V CC+0.3V) I IO Notes: • Subjecting ports to overvoltage may effect the supply voltage and ground levels of the application and the device. Ensure appropriate design (low impedance) of the power and ground supply to keep VCC and V SS within the specified limits. In particular, avoid subjecting ports to overvoltage causing V CC-V SS t o rise above 5.5 V. • Port P0 must not be subjected to overvoltage conditions. • Overvoltages causing input current flowing through the internal port protection circuits have a negative effect on the ports noise immunity. Therefore, careful and intense testing of the target system’s noise immunity is required. • Because of the above noise immunity issue, it is not recommended to subjects ports with interrupt functions (such as ports for external interrupt) to overvoltage conditions. • Refer to the “ 3.4 Countmeasures against noise”. 7630 Group User’s Manual 2-7 APPLICATION 2.1 I/O ports 2.1.4 Handling examples of unused pins Table 2.1.1 Handling of unused pins Name of Pins/Ports Handling P0, P11 (Note) P12 to P17, P2, Configure as inputs and pull to VCC o r V SS v ia a resistor of 1 k Ω t o 10 P3, P4 kΩ , or configure as outputs and leave open (expect P1 1 ). V REF Connect to VSS (GND) or leave open. AVSS Connect to VSS(GND). X OUT Leave open (only when using external clock). Note: The P1 1 p in of the built-in programmable ROM version is used in common with the VPP p in, insert a register of about 5 k Ω i n series and connect by the shortest wiring. 2-8 7630 Group User’s Manual APPLICATION 2.2 Interrupts 2.2 Interrupts 2.2.1 Memory map of interrupt related registers 000216 000316 000416 000516 000616 000716 Interrupt request register A (IREQA) Interrupt request register B (IREQB) Interrupt request register C (IREQC) Interrupt control register A (ICONA) Interrupt control register B (ICONB) Interrupt control register C (ICONC) 002D16 Interrupt polarity selection register (IPOL) 002F16 Polarity control register (PCON) Fig. 2.2.1 Memory map of interrupt related registers 7630 Group User’s Manual 2-9 APPLICATION 2.2 Interrupts 2.2.2 Related registers Interrupt request register A b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register A (IREQA) [Address : 000216] B 0 1 Name Not used (“0” when read.) External interrupt INT0 request bit 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested Function At reset R W 0 0 0 0 0 0 0 0 V V V V V V V 2 External interrupt INT1 request bit 3 4 CAN successful transmission interrupt request bit CAN successful receive interrupt request bit 5 CAN overrun interrupt request bit 6 7 CAN error passive interrupt request bit CAN bus off interrupt request bit V Can be cleared to “0” by software, but cannot be set to “1”. Fig. 2.2.2 Structure of Interrupt request register A Interrupt request register B b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register B (IREQB) [Address : 000316] B Name Function 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested At reset R W V V V V V V V V CAN wake-up 0 interrupt request bit 1 Timer X interrupt request bit 0 0 0 0 0 0 0 0 2 Timer Y interrupt request bit 3 4 5 6 7 Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit V Can be cleared to “0” by software, but cannot be set to “1”. Fig. 2.2.3 Structure of Interrupt request register B 2-10 7630 Group User’s Manual APPLICATION 2.2 Interrupts Interrupt request register C b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register C (IREQC) [Address : 000416] B Name Function 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested At reset R W V V V V V V V UART receive complete (receive 0 buffer full) interrupt request bit 1 register empty) interrupt request bit 2 UART transmit buffer empty interrupt request bit 3 4 UART receive error interrupt request bit Serial I/O interrupt request bit UART transmit complete (transmit 0 0 0 0 0 0 0 0 5 AD conversion complete interrupt request bit 6 7 Key-on wake-up interrupt request bit Not used (“0” when read.) V Can be cleared to “0” by software, but cannot be set to “1”. Fig. 2.2.4 Structure of Interrupt request register C Interrupt control register A b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register A (ICONA) [Address : 000516] B Name Function At reset R W 0 Not used (“0” when read.) 1 External interrupt INT0 enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 0 0 0 0 0 0 0 2 External interrupt INT1 enable bit 3 4 CAN successful transmission interrupt enable bit CAN successful receive interrupt enable bit 5 CAN overrun interrupt enable bit 6 7 CAN error passive interrupt enable bit CAN bus off interrupt enable bit Fig. 2.2.5 Structure of Interrupt control register A 7630 Group User’s Manual 2-11 APPLICATION 2.2 Interrupts Interrupt control register B b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register B (ICONB) [Address : 000616] B 0 1 Name CAN wake-up interrupt enable bit Timer X interrupt enable bit Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 0 0 0 0 0 2 Timer Y interrupt enable bit 3 4 5 6 7 Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit Fig. 2.2.6 Structure of Interrupt control register B Interrupt control register C b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register C (ICONC) [Address : 000716] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled At reset R W UART receive complete (receive 0 buffer full) interrupt enable bit 1 0 0 0 0 0 0 0 0 UART transmit complete (transmit 0 : Interrupt disabled register empty) interrupt enable bit 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 2 UART transmit buffer empty interrupt enable bit 3 4 UART receive error interrupt enable bit Serial I/O interrupt enable bit 5 AD conversion complete interrupt enable bit 6 7 Key-on wake-up interrupt enable bit Not used (“0” when read.) Fig. 2.2.7 Structure of Interrupt control register C 2-12 7630 Group User’s Manual APPLICATION 2.2 Interrupts Interrupt polarity selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt polarity selection register (IPOL) [Address : 002D16] B Name Function At reset R W 0 Not used (“0” when read, don't write “1”.) 0: Falling edge active 1 INT0 interrupt edge selection bit (Note) 1: Rising edge active 0: Falling edge active 2 INT1 interrupt edge selection bit (Note) 1: Rising edge active 3 Not used (“0” when read, don't write “1”.) 4 5 6 7 0 0 0 0 0 0 0 0 Note: To use the external interrupt functions, the pull-up transistor corresponding to the selected active level must be enabled by the corresponding pull-up transistor control bits of the Port P1 pull-up control register). Fig. 2.2.8 Structure of Interrupt polarity selection register Polarity control register b7 b6 b5 b4 b3 b2 b1 b0 Polarity control register (PCON) [Address : 002F16] B 0 1 Name Key-on wake-up polarity control bit CAN module dominant level control bit (Note) Function 0: Low level active (P4 pull-up) 1: High level active (P4 pull-down) 0: Low level dominant (P32 pull-up) 1: High level dominant (P32 pull-down) At reset R W 0 0 ? ? ? ? ? ? 2 3 4 Not used (undefined when read.) 5 6 7 Note: The selected dominant level also controls the polarity of the pull-transistor enabled by the P32 pull-up/down transistor control bit (bit 2 of the Port P3 pull-up control register), the transistor pulling toward the recessive level is selected. Fig. 2.2.9 Structure of Polarity control register 7630 Group User’s Manual 2-13 APPLICATION 2.2 Interrupts 2.2.3 Interrupt setting method Figure 2.2.10 and Figure 2.2.11 show interrupt setting method. Step 1: Disable all interrupts or the setting interrupts to prevent unnecessary interrupts occurring during setting. In the former, set the Interrupt disable flag (I) to “1”. In the latter, clear the corresponding interrupt enable bits to “0”. b7 b0 Interrupt control register A (ICONA) [Address: 000516] External interrupt INT0 enable bit External interrupt INT1 enable bit CAN successful transmission interrupt enable bit CAN successful receive interrupt enable bit CAN overrun interrupt enable bit CAN error passive interrupt enable bit CAN bus off interrupt enable bit b7 b0 Interrupt control register B (ICONB) [Address: 000616] CAN wake-up interrupt, interrupt disabled. Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit b7 b0 Interrupt control register C (ICONC) [Address: 000716] UART receive complete (receive buffer full) interrupt enable bit UART transmit complete (transmit register empty) interrupt enable bit UART transmit buffer empty interrupt enable bit UART receive error interrupt enable bit Serial I/O interrupt enable bit AD conversion complete interrupt enable bit Key-on wake-up interrupt enable bit Step 2: Set the each function related the setting interrupts (Note 1). Note 1: For details, refer to setting method of each function. Fig. 2.2.10 Interrupt setting method (1) 2-14 7630 Group User’s Manual APPLICATION 2.2 Interrupts Step 3: Clear the setting interrupt request bits to “0” (no interrupt request). b7 b0 Interrupt request register A (IREQA) [Address: 000216] External interrupt INT0 request bit External interrupt INT1 request bit CAN successful transmission interrupt request bit CAN successful receive interrupt request bit CAN overrun interrupt request bit CAN error passive interrupt request bit CAN bus off interrupt request bit b7 b0 Interrupt request register B (IREQB) [Address: 000316] CAN wake-up interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit b7 b0 Interrupt request register C (IREQC) [Address: 000416] UART receive complete (receive buffer full) interrupt request bit UART transmit complete (transmit register empty) interrupt request bit UART transmit buffer empty interrupt request bit UART receive error interrupt request bit Serial I/O interrupt request bit AD conversion complete interrupt request bit Key-on wake-up interrupt request bit Step 4: Set the using interrupt enable bits to “1” (interrupt enabled). Refer to Step 1. Step 5: When the Interrupt disable flag (I) is set to “1” in Step 1, clear the flag to “0” (interrupt enabled). Step 6: Operate the each functions related the using interrupts (Note 2). Note 2: For details, refer to setting method of each function. Fig. 2.2.11 Interrupt setting method (2) 7630 Group User’s Manual 2-15 APPLICATION 2.2 Interrupts 2.2.4 Key-on wake-up interrupt Figure 2.2.12 and Figure 2.2.13 show setting method for registers related to the key-on wake-up interrupt. Step 1: Disable the key-on wake-up interrupt or all interrupts to prevent unnecessary interrupts occurring during setting. In the former, set the Interrupt disable flag (I) to “1”. In the latter, clear the Key-on wake-up interrupt enable bit to “0”. b7 b0 0 Interrupt control register C (ICONC) [Address: 000716] Key-on wake-up interrupt enable bit Step 2: Set the ports of P4 used as key-on wake-up input pin to input mode. b7 b0 Port P4 direction register (P4D) [Address: 001116] Port P40 direction register Port P41 direction register Port P42 direction register Port P43 direction register Port P44 direction register Port P45 direction register Port P46 direction register Port P47 direction register 0 : Input mode 1 : Output mode Step 3: Pull-up/down the ports of P4 used as key-on wake-up input pin. b7 b0 Port P4 pull-up/down control register (PUP4) [Address: 002C16] Port P40 pull-up/down transistor control bit Port P41 pull-up/down transistor control bit Port P42 pull-up/down transistor control bit Port P43 pull-up/down transistor control bit Port P44 pull-up/down transistor control bit Port P45 pull-up/down transistor control bit Port P46 pull-up/down transistor control bit Port P47 pull-up/down transistor control bit 0 : No pull-up/down 1 : Pull-up/down Step 4: Set the key-on wake-up polarity. b7 b0 0 Polarity control register (PCON) [Address: 002F16] Key on wake-up polarity control bit 0 : Low level active (P4 pull-up) 1 : High level active (P4 pull-down) Fig. 2.2.12 Setting method for registers related to key-on wake-up interrupt (1) 2-16 7630 Group User’s Manual APPLICATION 2.2 Interrupts Step 5: Clear the Key-on wake-up interrupt request bit to “0” (no interrupt request). b7 b0 0 Interrupt request register C (IREQC) [Address: 000416] Key-on wake-up interrupt request bit Step 6: Set the Key-on wake-up interrupt enable bit to “1” (interrupt enabled). b7 b0 1 Interrupt control register C (ICONC) [Address: 000716] Key-on wake-up interrupt enable bit Step 7: When the Interrupt disable flag (I) is set to “1” in Step 1, clear the flag to “0” (interrupt enabled). Step 8: Execute the STP/WIT instruction to switch procedure to the stop/wait mode. Fig. 2.2.13 Setting method for registers related to key-on wake-up interrupt (2) 7630 Group User’s Manual 2-17 APPLICATION 2.3 Timers 2.3 Timers 2.3.1 Memory map of timer 001616 001716 001816 001916 001A16 001B16 Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 123 mode register (T123M) Timer XL (TXL) Timer XH (TXH) 001C16 Timer YL (TYL) 001D16 Timer YH (TYH) 001E16 001F16 Timer X mode register (TXM) Timer Y mode register (TYM) Fig. 2.3.1 Memory map of timer related registers 2-18 7630 Group User’s Manual APPLICATION 2.3 Timers 2.3.2 Related registers Timer 1, Timer 3 b7 b6 b5 b4 b3 b2 b1 b0 Timer 1 (T1) [Address : 001616] Timer 3 (T3) [Address : 001816] B Function At reset R W 0 q Set “0016” to “FF16” as Timer 1 or Timer 3 count value. 1 q The timer value is written to timer and latch at the same time. 2 3 4 5 6 7 q To get the actual Timer 1 or Timer 3 value read out the 1 1 1 1 1 1 1 1 corresponding timer register. Fig. 2.3.2 Structure of Timer 1, Timer 3 Timer 2 b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2) [Address : 001716] B Function At reset R W 0 q Set “0016” to “FF16” as Timer 2 count value. 1 q The timer value is written to Timer 2 and latch at the same time 2 3 4 5 6 7 1 0 0 0 0 0 0 0 or to the latch only (Note). q To get the actual Timer 2 value read out the Timer 2 register. Note: Depinding on the Timer 2 write control bit (bit 2 of the Timer 123 mode register [address: 001916] ). Fig. 2.3.3 Structure of Timer 2 7630 Group User’s Manual 2-19 APPLICATION 2.3 Timers Timer 123 mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer 123 mode register (T123M) [Address : 001916] B 0 1 Name PWM polarity selection bit PWM output enable bit Function 0 : Start on “H” level output 1 : Start on “L” level output 0 : PWM output disabled 1 : PWM output enabled 0 : Latch and counter 1 : Latch only 0 : Timer 1 underflow 1 : Pre-divider output 0 : Timer 1 underflow 1 : Pre-divider output At reset R W 0 0 0 0 0 0 1 0 2 Timer 2 write control bit 3 4 Timer 2 count source selection bit Timer 3 count source selection bit 5 Not used (“0” when read, don't write “1”.) 6 7 Pre-divider division ratio bits 0 0 : φ divided by 1 (Note) 0 1 : φ divided by 8 (Note) 1 0 : φ divided by 32 (Note) 1 1 : φ divided by 128 (Note) b7 b6 Note: The internal system clock φ is divided f(XIN) by 2 or by 8. The division ratio is decided by the Internal system clock selection bit (bit 6 of the CPU mode register [address: 000016] ). Fig. 2.3.4 Structure of Timer 123 mode register Timer XL, Timer XH, Timer YL, Timer YH b7 b6 b5 b4 b3 b2 b1 b0 Timer XL (TXL), Timer XH (TXH) [Address : 001A16, 001B16] Timer YL (TYL), Timer YH (TYH) [Address : 001C16, 001D16] B 0 1 2 3 4 5 6 7 Function q Set “000016” to “FFFF16” as timer count value. q Write access At reset R W 1 1 1 1 1 1 1 1 The timer value is written to Timer X or Timer Y and latch at the same timer or to the latch only (Note). Write first low byte (TXL, TYL) and then high byte (TXH, TYH). q Read access To get the actual Timer X or Timer Y value read out the corresponding timer register. A measurement value is read out in pulse period and pulse width measurement mode. Read first high byte (TXH, TYH) and then low byte (TXL, TYL). Note: Depinding on the Timer X or Timer Y data write control bit (bit 0 of the Timer X or Timer Y mode register [address: 001E16, 001F16] ). Fig. 2.3.5 Structure of Timer XL, Timer XH, Timer YL, Timer YH 2-20 7630 Group User’s Manual APPLICATION 2.3 Timers Timer X mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register (TXM) [Address : 001E16] B 0 1 2 3 4 5 CNTR0 polarity selection bit Timer X mode bits b5 b4 Name Timer X data write control bit Function 0 : Data is written to latch and timer. 1 : Data is written to latch only. At reset R W 0 0 0 0 0 0 Not used (“0” when read, don't write “1”.) 0 0 1 1 0 1 0 1 : : : : Timer mode Bi-phase counter mode Event counter mode Pulse width measurement mode 6 0 : For event counter mode, rising edge active For interrupt request, falling edge active For pulse width measurement mode, measure “H” period 1 : For event counter mode, falling edge active For interrupt request, rising edge active For pulse width measurement mode, measure “L” period 0 7 Timer X stop control bit 0 : Timer counting 1 : Timer stopped 0 Fig. 2.3.6 Structure of Timer X mode register Timer Y mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer Y mode register (TYM) [Address : 001F16] B 0 1 2 3 4 5 CNTR1 polarity selection bit Timer Y operation mode bits Timer Y count source selection bits Name Timer X count source selection bits b1 b0 Function 0 0 1 1 0 0 1 1 0 0 1 1 At reset R W 0 1 0 1 0 1 0 1 0 1 0 1 : : : : : : : : : : : : φ φ φ φ φ φ φ φ divided divided divided divided divided divided divided divided by by by by by by by by 4 (Note) 16 (Note) 64 (Note) 128 (Note) 2 (Note) 8 (Note) 32 (Note) 64 (Note) 0 0 0 0 0 0 b3 b2 b5 b4 Timer mode Pulse period measurement mode Event counter mode H/L pulse width measurement mode 6 0 : For event counter mode, rising edge active For interrupt request, falling edge active For pulse period measurement mode, refer to falling edge 1 : For event counter mode, falling edge active For interrupt request, rising edge active For pulse period measurement mode, refer to rising edge 0 7 Timer Y stop control bit 0 : Timer counting 1 : Timer stopped 0 Note: The internal system clock φ is divided f(XIN) by 2 or by 8. The division ratio is decided by the Internal system clock selection bit (bit 6 of the CPU mode register [address: 000016] ). Fig. 2.3.7 Structure of Timer Y mode register 7630 Group User’s Manual 2-21 APPLICATION 2.3 Timers 2.3.3 Timer application examples (1) Basic functions and uses [Function 1] Control of Event interval (Timer X, Timer Y, Timer 1, Timer 2, Timer 3) The Timer count stop bit is set to “0” after setting a count value to a timer. Then a timer interrupt request occurs after a certain period ( Timer mode ). [Use] • Generation of an output signal timing • Generation of a waiting time [Function 2] Control of Cyclic operation (Timer X, Timer Y, Timer 1, Timer 2, Timer 3) The value of a timer latch is automatically written to a corresponding timer every time a timer underflows, and each cyclic timer interrupt request occurs ( Timer mode ). [Use] • Generation of cyclic interrupts • Clock function (measurement of 25ms) → A pplication example 1 • Control of a main routine cycle [Function 3] Count of External pulse (Timer X) External pulses input to the CNTR pin are selected as a timer count source ( Bi-phase mode). [Use] • Measurement of incremental sensor output signals [Function 4] Count of External pulse (Timer X, Timer Y) External pulses input to the CNTR pin are selected as a timer count source (Event counter mode ). [Use] • Measurement of frequency → A pplication example 2 • Division of external pulses. • Generation of interrupts in a cycle based on an external pulse. (count of a reel pulse) [Function 5] Measurement of External pulse width (Timer X, Timer Y) The “H” or “L” level width of external pulses input to CNTR pin is measured ( Pulse width measurement mode ). [Use] • Measurement of external pulse frequency (Measurement of pulse width of FG pulseV generated by motor) → A pplication example 3 • Measurement of external pulse duty (when the frequency is fixed) V FG pulse : Pulse used for detecting the motor speed to control the motor speed. 2-22 7630 Group User’s Manual APPLICATION 2.3 Timers (2) Timer application example 1 : Clock function (measurement of 25 ms) Outline : T he input clock is divided by a timer so that the clock counts up every 25 ms. Specifications : • The clock f(XIN) = 8 MHz is divided by a timer. • The clock is counted at intervals of 25 ms by the Timer 3 interrupt. Figure 2.3.8 shows the timers connection and division ratios, Figures 2.3.9 show a setting of related registers, and Figure 2.3.10 shows a control procedure. f(XIN) = 8 MHz 1/2 (Note 1) φ Pre-divider (Note 2) 1/8 Timer 1 1/250 Timer 3 1/50 Timer 3 interrupt request 25 ms 1/40 The clock is divided by 40 by software. 1 second Note 1: The internal system clock φ is divided f(XIN) by 2 or by 8. The division ratio is decided by the Internal system clock selection bit (bit 6 of the CPU mode register [address: 000016] ). Note 2: The division ratio is decided by the Pre-divider division ratio bits (bit 6 and bit 7 of the Timer 123 mode register [address: 001916] ). Fig. 2.3.8 Timers connection and division ratios [Clock function] 7630 Group User’s Manual 2-23 APPLICATION 2.3 Timers CPU mode register [Address: 000016] b7 b0 CPUM 0 Internal system clock selection bit : φ = f(XIN) divided by 2 (high-speed mode) Timer 123 mode register [Address: 001916] b7 b0 T123M 0 1 0 Timer 3 count source selection bit : Output signal from Timer 1 Pre-divider division ratio bits : φ divided by 8 Timer 1 [Address: 001616] b7 b0 T1 249 Set “division ratio – 1” Timer 1 [Address: 001816] b7 b0 T3 49 Set “division ratio – 1” Interrupt request register B [Address: 000316] b7 b0 IREQB 0 Timer 3 interrupt request bit (becomes “1” every 25 ms) Interrupt control register B [Address: 000616] b7 b0 ICONB 1 Timer 3 interrupt enable bit : Interrupt enabled Fig. 2.3.9 Setting of related registers [Clock function] 2-24 7630 Group User’s Manual APPLICATION 2.3 Timers Control procedure : F igure 2.3.10 shows a control procedure. RESET Initialization SEI CPUM [Address: 000016] T123M [Address: 001916] ICONB [Address: 000616], bit 5 T1 [Address: 001616] T3 [Address: 001816] CLI Main processing [Processing for completion of setting clock] (Note 1) T1 [Address: 001616] 250 – 1 T3 [Address: 001816] IREQB [Address: 000316], bit 5 50 – 1 0 00000X002 0100XXXX2 1 250 – 1 50 – 1 X : These bits are not used in this application. Please set these bits to “0” or “1” appropriately. • All interrupts : Disabled • φ = f(XIN) divided by 2 (high-speed mode) • Select each count source of the Timer 1 and Timer 3. • Set “division ratio – 1” to the Timer 1 and Timer 3. • Interrupts : Enabled • When restarting the clock from zero second after completing to set the clock, reset timers. • Set the Timer 3 interrupt request bit to “0”. Note 1: This processing is performed only at completing to set the clock. Timer 3 interrupt processing routine CLT (Note 2) CLD (Note 3) Push registers to the stack area Note 2: When using the Index X mode flag (T). Note 3: When using the Decimal mode flag (D). • Push the registers used in the interrupt processing routine on the stack. Y • Check if the clock has already been set. Clock stop? N Clock count up (1/40 second to year) • Count up the clock. Pop registers from the stack area • Pop registers which are pushed on the stack. RTI Fig. 2.3.10 Control procedure [Clock function] 7630 Group User’s Manual 2-25 APPLICATION 2.3 Timers (3) Timer application example 2 : Measurement of frequency Outline : T o judge if the frequency is within a given range, the following two values are compared • Timer value (representing the number of pulses at P1 4/CNTR 0 ), • Referance value. Specifications : • The pulse is input to the P1 4/CNTR 0 p in and counted by the Timer X. • A count value is read out at the interval of about 2 ms (Timer Y interrupt interval). When the count value is between 28 and 40, the input signal is judged valid. • Because the timer is a down-counter, the count value is compared with 227 to 215V. V 2 27 to 215 = 255 (initialized value of counter) – 28 to 40 (the number of valid value) Figure 2.3.11 shows a method for judging if input pulse exists, and Figure 2.3.12 and Figure 2.3.13 show a setting of related registers. Input pulse More than 71.4 µs (Less than 14 kHz) Invalid 71.4 µs (14 kHz) Valid 2 ms = 28 counts 71.4 µs 50 µs (20 kHz) Less than 50 µs (More than 20 kHz) Invalid 2 ms = 40 counts 50 µs Fig. 2.3.11 A method for judging if input pulse exists 2-26 7630 Group User’s Manual APPLICATION 2.3 Timers CPU mode register [Address: 000016] b7 b0 CPUM 0 Internal system clock selection bit : φ = f(XIN) divided by 2 (high-speed mode) Timer X mode register [Address: 001E16] b7 b0 TXM 1 1 1 0 0 Timer X data write control bit : Write to latch and timer at the same time. Timer X mode bits : Event counter mode CNTR0 polarity selection bit : Count at falling edge Timer X stop control bit : Stop counting (Clear this bit to “0” to start counting.) Timer Y mode register [Address: 001F16] b7 b0 TYM 1 0001 Timer Y count source selection bits : φ divided by 8 Timer Y operation bits : Timer mode Timer Y stop control bit : Stop counting (Clear this bit to “0” to start counting.) Timer XL [Address: 001A16] b7 b0 TXL FF16 Timer XH [Address: 001B16] b7 b0 Set to “00FF16” before counting a pulse. (After being started, the timer decrements with each input pulse.) TXH 0016 Timer YL [Address: 001C16] b7 b0 TYL E716 Timer YH [Address: 001D16] b7 b0 Set to “division ratio – 1” to generate underflow every 2 ms at f(XIN) = 8 MHz. TYH 0316 Fig. 2.3.12 Setting of related registers [Measurement of frequency] (1) 7630 Group User’s Manual 2-27 APPLICATION 2.3 Timers Interrupt request register B [Address: 000316] b7 b0 IREQB 0 Timer Y interrupt request bit (becomes “1” every 2 ms) Interrupt control register B [Address: 000616] b7 b0 ICONB 10 Timer X interrupt enable bit : Interrupt disabled Timer Y interrupt enable bit : Interrupt enabled Port P1 direction register [Address: 000B16] b7 b0 P1D 0 Port P14 : Input mode Fig. 2.3.13 Setting of related registers [Measurement of frequency] (2) 2-28 7630 Group User’s Manual APPLICATION 2.3 Timers Control procedure : F igure 2.3.14 shows a control procedure. RESET Initialization SEI CPUM [Address: 000016] TXM [Address: 001E16] P1D [Address: 000B16] TXL [Address: 001A16] TXH [Address: 001B16] TYM [Address: 001F16] TYL [Address: 001C16] TYH [Address: 001D16] ICONB [Address: 000616], bit 2 ICONB [Address: 000616], bit 1 IREQB [Address: 000316], bit 2 TXM [Address: 001E16], bit 7 TYM [Address: 001F16], bit 7 CLI 00000X002 111000002 XXX0XX002 FF16 0016 1X0001XX2 E716 0316 1 0 0 0 0 X : These bits are not used in this application. Please set these bits to “0” or “1” appropriately. • All interrupts : Disabled • φ = f(XIN) divided by 2 (high-speed mode) • Timer X : Event counter mode (Count at falling edge of pulse input from CNTR0 pin), stop counting • Initialize the count value • Timer Y : Timer mode (φ divided by 8 as count source), stop counting • Set the Timer Y division ratio so that the Timer Y interrupt occurs every 2 ms. • Timer Y interrupt : Enabled • Timer X interrupt : Enabled • Set the Timer Y interrupt request bit to “0”. • Timer X : Start counting • Timer Y : Start counting • Interrupts : Enabled Timer Y interrupt processing routine CLT (Note 1) CLD (Note 2) Push registers to the stack area Note 1: When using the Index X mode flag (T). Note 2: When using the Decimal mode flag (D). • Push the registers used in the interrupt processing routine on the stack. ≠ 0016 TXH [Address: 001B16]? = 0016 • When the count value is 256 or more, the processing is performed as out of range. D616 < TXL [Address: 001A16] < E416? Out of range Fpulse 0 In range • Compare the count value with the reference value • Store the comparison result in flag Fpulse. Fpulse 1 TXL [Address: 001A16] TXH [Address: 001B16] FF16 0016 • Initialize the count value Processing for a result of judgment Pop registers from the stack area • Pop registers which are pushed on the stack. RTI Fig. 2.3.14 Control procedure [Measurement of frequency] 7630 Group User’s Manual 2-29 APPLICATION 2.3 Timers (4) Timer application example 3 : Measurement of pulse width of FG pulse generated by motor Outline : T he “H” level width of a pulse input to the P1 4/CNTR 0 p in is counted by Timer X. An underflow is detected by Timer X interrupt and an end of the input pulse “H” level is detected by a CNTR0 i nterrupt. Specifications : The “H” level width of FG pulse input to the P1 4 /CNTR0 pin is counted by Timer X. (Example : When the clock frequency is 8 MHz, the count source would be 4 µs that is obtained by dividing the clock frequency by 32. Measurement can be made up to 262.144 ms in the range of FFFF 16 t o 0000 16 .) Figure 2.3.15 shows timer connection and division ratio, and Figure 2.3.16 shows a setting of related registers. f(XIN) = 8 MHz 1/2 (Note 1) φ (Note 2) 1/16 Timer X 1/65536 Timer X interrupt request 262.144 ms Note 1: The internal system clock φ is divided f(XIN) by 2 or by 8. The division ratio is decided by the Internal system clock selection bit (bit 6 of the CPU mode register [address: 000016] ). Note 2: The division ratio is decided by the Timer count source selection bits (bit 0 and bit 1 of the Timer X mode register [address: 001E16] ). Fig. 2.3.15 Timer connection and division ratio [Measurement of pulse width] 2-30 7630 Group User’s Manual APPLICATION 2.3 Timers CPU mode register [Address: 000016] b7 b0 CPUM 0 Internal system clock selection bit : φ = f(XIN) divided by 2 (high-speed mode) Timer X mode register [Address: 001E16] b7 b0 TXM 1 0 1 1 0 Timer X data write control bit : Write to latch and timer at the same time. Timer X mode bits : Pulse width measurement mode CNTR0 polarity selection bit : Measure the “H” period Timer X stop control bit : Stop counting (Clear this bit to “0” to start counting.) Timer Y mode register [Address: 001F16] b7 b0 TYM 01 Timer X count source selection bits : φ divided by 16 Timer XL [Address: 001A16] b7 b0 TXL FF16 Timer XH [Address: 001B16] b7 b0 Set to “FFFF16” before counting a pulse. (After being started, the timer decrements with each input pulse.) TXH FF16 Interrupt control register B [Address: 000616] b7 b0 ICONB 1 1 Timer X interrupt enable bit : Interrupt enabled CNTR0 interrupt enable bit : Interrupt enabled Interrupt request register B [Address: 000316] b7 b0 IREQB 0 0 Timer X interrupt request bit (This bit is set to “1” at underflow of Timer X.) CNTR0 interrupt request bit (This bit is set to “1” at the falling edge of the input signal of CNTR0 pin.) Port P1 direction register [Address: 000B16] b7 b0 P1D 0 P14 : Input mode Fig. 2.3.16 Setting of related registers [Measurement of pulse width] 7630 Group User’s Manual 2-31 APPLICATION 2.3 Timers Control procedure : F igure 2.3.17 and Figure 2.3.18 show a control procedure. RESET Initialization SEI CPUM [Address: 000016] TXM [Address: 001E16] P1D [Address: 000B16] TYM [Address: 001F16] TXL [Address: 001A16] TXH [Address: 001B16] ICONB [Address: 000616], bit 1 ICONB [Address: 000616], bit 6 IREQB [Address: 000316], bit 1 IREQB [Address: 000316], bit 6 TXM [Address: 001E16], bit 7 CLI 00000X002 101100002 XXX0XX002 XXXXXX012 FF16 FF16 1 1 0 0 0 X : These bits are not used in this application. Please set these bits to “0” or “1” appropriately. • All interrupts : Disabled • φ = f(XIN) divided by 2 (high-speed mode) • Timer X : Pulse width measurement mode (Count “H” level width of pulse input from CNTR0 pin), stop counting • Timer X count source : φ divided by 16 • Initialize the count value of the Timer X • Timer X interrupt : Enabled • CNTR0 interrupt : Enabled • Set the Timer X interrupt request bit to “0”. • Set the CNTR0 interrupt request bit to “0”. • Timer X : Start counting • Interrupts : Enabled Timer X interrupt processing routine (Note 1) • Error occurs Note 1: The Timer X interrupt occurs at a level except a measurement level (when it is “L” level in this application example). Process by software in accordance with the necessity like as a processing for errors is performed only at a measurement level (the CNTR0 input level is judged by reading a content of the Port P14 register). Processing for error RTI Fig. 2.3.17 Control procedure [Measurement of pulse width] (1) 2-32 7630 Group User’s Manual APPLICATION 2.3 Timers CNTR0 interrupt processing routine (Note 2) CLT (Note 3) CLD (Note 4) Push registers to the stack area RAM for high-order 8-bit of a measurement result RAM for low-order 8-bit of a measurement result Pop registers from the stack area Note 3: When using the Index X mode flag (T). Note 4: When using the Decimal mode flag (D). • Push the registers used in the interrupt processing routine on the stack. TXH • A complemented count value is read out and stored to RAM. TXL • Pop registers which is pushed on the stack. RTI Note 2: The first measurement with Timer X is invalid as shown in the following figure. Example: 1. Make sure to start the Timer X count at “L” level of the CNTR0 input signal. (A level of the CNTR0 input signal is judged by reading a content of the Port P14 register. 2. Be sure to invalidate the first CNTR0 interrupt after starting the Timer X count. [When the Timer X count is started at “L” level of the CNTR0 input signal] 000016 t2 t1 Timer X Start Timer X FFFF16 A measurement result: Valid A measurement result: Valid CNTR0 input CNTR0 interrupt CNTR0 interrupt [When the Timer X count is started at “H” level of the CNTR0 input signal] 000016 t2 t1 Timer X Start Timer X FFFF16 A measurement result: Invalid A measurement result: Valid CNTR0 input CNTR0 interrupt CNTR0 interrupt Fig. 2.3.18 Control procedure [Measurement of pulse width] (2) 7630 Group User’s Manual 2-33 $33/,&$7,21 2.4 Controller Area Network (CAN) module 2.4 Controller Area Network (CAN) module This section outlines the Controller Area Network (CAN) module of the MCU. First the module’s architecture and the programming interface with its related special function registers are explained. Second, after having defined the fundamental operational modes of the module, the programming sequences to initialize and reset the module are clarified. Third, the module’s communication functions, that is acceptance filtering, reception, and transmission are discussed in detail. The closing of the section goes into the interrupt capabilities, CAN error conditions, and the wake-up function. 2.4.1 Description The CAN module can be characterized as follows: • Compatibility: The module’s protocol controller complies with CAN specification version 2.0, part B as defined by Bosch in September 1991 (this document is later on called CAN specification). The receive and transmit sections of the module are capable of handling standard (11-bit identifier) as well as extended (29-bit identifier) format frames of either data or remote type. • CPU interface: The module is memory mapped with sixteen control registers, two interrupt control registers, one transmission, and two receive buffer register sets. • Acceptance filtering: U p to 29-bit identifiers can be filtered by using one set of acceptance mask and code registers. • Multi-channel interrupt capability: Separate interrupt vectors for each event (successful transmission, successful reception, overrun, error passive, bus off) allow efficient and rapid interrupt service routine operation. • Low power (sleep) mode: To reduce power consumption, the module can be set to sleep mode; wake-up from CAN traffic is supported by a dedicated interrupt source and vector. • Priority based message management support: To cope with the problem of priority inversion, the contents of the transmission buffer can be released, in order to let another higher priority message to take over. • Baud rate prescaler: This programmable divider provides a flexible baud rate selection up to 625kbps (at f(XIN) = 10MHz). • Programmable bit timing: The durations of propagation time segment (PTS), phase buffer segments 1 (PBS1), and 2 (PBS2) are programmable. • Physical interface: A two terminal CMOS-compatible interface (formed by ports P31 and P32) allows direct connection to the most popular transceiver devices (e.g. ISO 11898, ISO 11519). Refer to the block diagram in Figure 2.4.1. 2-34 7630 Group User’s Manual $33/,&$7,21 2.4 Controller Area Network (CAN) module CAN module φ f(XIN) clock control sleep control Baud rate prescaler CAN receive control register Acceptance mask registers Acceptance code registers Bus timing control registers message handling receive control logic P31/CTX P32/CRX protocol controller and interface status/buffer control acceptance filter Receive buffers transmit control logic CAN transmit control register status/buffer control Transmit buffer CAN transmit abort register interrupt control logic Polarity control register wake up logic Successful receive interrupt Successful transmit interrupt Overrun interrupt Error passive interrupt Bus off interrupt CAN wake up interrupt Interrupt control registers Interrupt request registers Notation in this diagram: Special function register logic Fig. 2.4.1 Block diagram of CAN module 2.4.2 Special function register map The CAN module’s programming interface consists of the registers listed below: • Transmit control register • Bus timing control registers • Acceptance code and mask registers • Receive control register • Transmit abort register • Transmit/receive buffers • Polarity control register • Interrupt request and control registers Figure 2.4.2 shows the memory map of these registers. The next section explains each register in detail; for the polarity control register and the interrupt registers refer to section 2.2. 7630 Group User’s Manual 2-35 $33/,&$7,21 2.4 Controller Area Network (CAN) module 000216 000316 ... 000516 000616 ... 002F16 003016 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003A16 003B16 003C 16 003D 16 003E16 … 004016 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004A16 004B16 004C 16 004D 16 Interrupt request register A Interrupt request register B ... Interrupt control register A Interrupt control register B ... Polarity control register CAN transmit control register CAN bus timing control register 1 CAN bus timing control register 2 CAN acceptance code register 0 CAN acceptance code register 1 CAN acceptance code register 2 CAN acceptance code register 3 CAN acceptance code register 4 CAN acceptance mask register 0 CAN acceptance mask register 1 CAN acceptance mask register 2 CAN acceptance mask register 3 CAN acceptance mask register 4 CAN receive control register CAN transmit abort register … CAN transmit buffer register 0 CAN transmit buffer register 1 CAN transmit buffer register 2 CAN transmit buffer register 3 CAN transmit buffer register 4 CAN transmit buffer register 5 CAN transmit buffer register 6 CAN transmit buffer register 7 CAN transmit buffer register 8 CAN transmit buffer register 9 CAN transmit buffer register A CAN transmit buffer register B CAN transmit buffer register C CAN transmit buffer register D IREQA IREQB ICONA ICONB PCON CTRM CBTCON1 CBTCON2 CAC0 CAC1 CAC2 CAC3 CAC4 CAM0 CAM1 CAM2 CAM3 CAM4 CREC CABORT CTB0 CTB1 CTB2 CTB3 CTB4 CTB5 CTB6 CTB7 CTB8 CTB9 CTBA CTBB CTBC CTBD CRB0 CRB1 CRB2 CRB3 CRB4 CRB5 CRB6 CRB7 CRB8 CRB9 CRBA CRBB CRBC CRBD Interrupt request/control registers Control registers and acceptance filter registers Transmit buffer registers … 005016 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005A16 005B16 005C 16 005D 16 … CAN receive buffer register 0 CAN receive buffer register 1 CAN receive buffer register 2 CAN receive buffer register 3 CAN receive buffer register 4 CAN receive buffer register 5 CAN receive buffer register 6 CAN receive buffer register 7 CAN receive buffer register 8 CAN receive buffer register 9 CAN receive buffer register A CAN receive buffer register B CAN receive buffer register C CAN receive buffer register D Receive buffer registers (double buffer concept) Fig. 2.4.2 Memory map of CAN related registers 2-36 7630 Group User’s Manual $33/,&$7,21 2.4 Controller Area Network (CAN) module 2.4.3 Related registers This section comprises the description of special function registers allocated to the CAN module. CAN transmit control register b7 b6 b5 b4 b3 b2 b1 b0 CAN transmit control register (CTRM) [Address: 003016] B 0 Name Sleep control bit Function1 0: CAN module in normal mode 1: CAN module in sleep mode 0: CAN module in normal mode 1 Reset/configuration control bit 1: CAN module in configuration mode (plus reset when write) 0: P31/CTX serves as I/O port 1: P31/CTX serves as CTX output port R0: No transmission requested 3 Transmit request bit R1: Transmission requested W0: No operation W1: Request transmission 4 Reserved “0” when read. R0: CPU access possible 5 Transmit buffer control bit R1: CPU access not possible W0: No operation W1: Lock transmit buffer 6 7 Reserved Transmit status bit “0” when read. 0: CAN module idle or receiving 1: CAN module transmitting 0 0 O O X X 0 O O 0 O X 0 O O 1 O O At reset 0 R O W O 2 Port double function control bit 0 O O Note 1: R0/R1 denote read access, W0/W1 denote write access. Fig. 2.4.3 Structure of CAN transmit control register (CTRM) CAN bus timing control register 1 b7 b6 b5 b4 b3 b2 b1 b0 CAN bus timing control register 1 (CBTCON1) [Address: 003116] B 0 1 2 3 4 5 6 7 Propagation time duration control bits Sampling control bit Name b3b2b1b0 Function 0000: Divided by 1 0001: Divided by 2 At reset 0 0 0 0 0 0 0 0 R O O O O O O O O W1 O O O O O O O O Prescaler division ratio selection bits 0010: Divided by 3 … 1101: Divided by 14 1110: Divided by 15 1111: Divided by 16 0: One sample per bit 1: Three samples per bit b7b6b5 000: One time quantum 001: Two time quanta … 110: Seven time quanta 111: Eight time quanta Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 2.4.4 Structure of CAN bus timing control register 1 (CBTCON1) 7630 Group User’s Manual 2-37 $33/,&$7,21 2.4 Controller Area Network (CAN) module CAN bus timing control register 2 b7 b6 b5 b4 b3 b2 b1 b0 CAN bus timing control register 2 (CBTCON2) [Address: 003216] B 0 1 2 3 4 5 6 Synchronization jump width control bits Phase buffer segment 2 duration control bits Phase buffer segment 1 duration control bits Name b2b1b0 Function 000: One time quantum 001: Two time quanta … 110: Seven time quanta 111: Eight time quanta b5b4b3 At reset 0 0 0 0 0 0 0 R O O O O O O O W1 O O O O O O O 000: One time quantum 001: Two time quanta … 110: Seven time quanta 111: Eight time quanta b7b6 00: One time quantum 01: Two time quanta 10: Three time quanta 11: Four time quanta 7 0 O O Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 2.4.5 Structure of CAN bus timing control register 2 (CBTCON2) CAN acceptance code register 0 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance code register 0 (CAC0) [Address: 003316] B 0 1 2 3 4 5 6 7 Not used Undefined at read. Name Standard identifier bit 6 Standard identifier bit 7 Standard identifier bit 8 Standard identifier bit 9 Standard identifier bit 10 These bits (except when masked by the acceptance mask register 0, Figure 2.4.11) form the acceptance filtering condition for incoming CAN frames. They must be initialized with the identifier pattern of CAN frames to be received. Function At reset ? ? ? ? ? ? ? ? R O O O O O O O O W1 O O O O O X X X Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 2.4.6 Structure of CAN acceptance code register 0 (CAC0) 2-38 7630 Group User’s Manual $33/,&$7,21 2.4 Controller Area Network (CAN) module CAN acceptance code register 1 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance code register 1 (CAC1) [Address: 003416] B 0 Not used 1 2 3 4 5 6 7 Standard identifier bit 0 Standard identifier bit 1 Standard identifier bit 2 Standard identifier bit 3 Standard identifier bit 4 Standard identifier bit 5 These bits (except when masked by the acceptance mask register 1, Figure 2.4.12) form the acceptance filtering condition for incoming CAN frames. They must be initialized with the identifier pattern of CAN frames to be received. Undefined at read. ? ? ? ? ? ? ? O O O O O O O X O O O O O O Name Function At reset ? R O W1 X Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 2.4.7 Structure of CAN acceptance code register 1 (CAC1) CAN acceptance code register 2 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance code register 2 (CAC2) [Address: 003516] B 0 1 2 3 4 5 Not used 6 7 Undefined at read. ? ? O O X X Name Extended identifier bit 14 Extended identifier bit 15 Extended identifier bit 16 Extended identifier bit 17 These bits (except when masked by the acceptance mask register 2, Figure 2.4.13) form the acceptance filtering condition for incoming CAN frames. They must be initialized with the identifier pattern of CAN frames to be received. Function At reset ? ? ? ? ? ? R O O O O O O W1 O O O O X X Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 2.4.8 Structure of CAN acceptance code register 2 (CAC2) 7630 Group User’s Manual 2-39 $33/,&$7,21 2.4 Controller Area Network (CAN) module CAN acceptance code register 3 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance code register 3 (CAC3) [Address: 003616] B 0 1 2 3 4 5 6 7 Name Extended identifier bit 6 Extended identifier bit 7 Extended identifier bit 8 Extended identifier bit 9 Extended identifier bit 10 Extended identifier bit 11 Extended identifier bit 12 Extended identifier bit 13 These bits (except when masked by the acceptance mask register 3, Figure 2.4.14) form the acceptance filtering condition for incoming CAN frames. They must be initialized with the identifier pattern of CAN frames to be received. Function At reset ? ? ? ? ? ? ? ? R O O O O O O O O W1 O O O O O O O O Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 2.4.9 Structure of CAN acceptance code register 3 (CAC3) CAN acceptance code register 4 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance code register 4 (CAC4) [Address: 003716] B 0 Not used 1 2 3 4 5 6 7 Extended identifier bit 0 Extended identifier bit 1 Extended identifier bit 2 Extended identifier bit 3 Extended identifier bit 4 Extended identifier bit 5 These bits (except when masked by the acceptance mask register 4, Figure 2.4.15) form the acceptance filtering condition for incoming CAN frames. They must be initialised with the identifier pattern of CAN frames to be received. Undefined at read. ? ? ? ? ? ? ? O O O O O O O X O O O O O O Name Function At reset ? R O W1 X Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 2.4.10 Structure of CAN acceptance code register 4 (CAC4) 2-40 7630 Group User’s Manual $33/,&$7,21 2.4 Controller Area Network (CAN) module CAN acceptance mask register 0 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance mask register 0 (CAM0) [Address: 003816] B 0 1 2 3 4 5 6 7 These bits must be set to "0". Name Standard identifier mask bit 6 Standard identifier mask bit 7 Standard identifier mask bit 8 Standard identifier mask bit 9 Standard identifier mask bit 10 0: Mask identifier bit (don’t care) 1: Compare identifier bit Function These bits mask the corresponding bits of the acceptance code register 0, Figure 2.4.6 from the acceptance filtering. At reset ? ? ? ? ? ? ? ? R O O O O O O O O W1 O O O O O O O O Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 2.4.11 Structure of CAN acceptance mask register 0 (CAM0) CAN acceptance mask register 1 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance mask register 1 (CAM1) [Address: 003916] B 0 These bits must be set to "0". 1 2 3 4 5 6 7 Standard identifier mask bit 0 Standard identifier mask bit 1 Standard identifier mask bit 2 Standard identifier mask bit 3 Standard identifier mask bit 4 Standard identifier mask bit 5 ? ? ? ? ? ? ? O O O O O O O O O O O O O O Name Function At reset ? R O W1 O 0: Mask identifier bit (don’t care) 1: Compare identifier bit These bits mask the corresponding bit of the acceptance code register 1, Figure 2.4.7 from the acceptance filtering. Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 2.4.12 Structure of CAN acceptance mask register 1 (CAM1) 7630 Group User’s Manual 2-41 $33/,&$7,21 2.4 Controller Area Network (CAN) module CAN acceptance mask register 2 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance mask register 2 (CAM2) [Address: 003A16] B 0 1 2 3 4 5 These bits must be set to "0". 6 7 ? ? O O O O Name Extended identifier mask bit 14 Extended identifier mask bit 15 Extended identifier mask bit 16 Function At reset ? ? ? ? ? ? R O O O O O O W1 O O O O O O 0: Mask identifier bit (don’t care) 1: Compare identifier bit These bits mask the corresponding bits of the acceptance code register 2, Figure Extended identifier mask bit 17 2.4.8 from the acceptance filtering. Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 2.4.13 Structure of CAN acceptance mask register 2 (CAM2) CAN acceptance mask register 3 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance mask register 3 (CAM3) [Address: 003B16] B 0 1 2 3 4 5 6 7 Name Extended identifier mask bit 6 Extended identifier mask bit 7 Extended identifier mask bit 8 Extended identifier mask bit 9 Extended identifier mask bit 10 Extended identifier mask bit 11 These bits mask the corresponding bits of the acceptance code register 3, Figure Extended identifier mask bit 12 2.4.9 from the acceptance filtering. Extended identifier mask bit 13 0: Mask identifier bit (don’t care) 1: Compare identifier bit Function At reset ? ? ? ? ? ? ? ? R O O O O O O O O W1 O O O O O O O O Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 2.4.14 Structure of CAN acceptance mask register 3 (CAM3) 2-42 7630 Group User’s Manual $33/,&$7,21 2.4 Controller Area Network (CAN) module CAN acceptance mask register 4 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance mask register 4 (CAM4) [Address: 003C16] B 0 These bits must be set to "0". 1 2 3 4 5 6 7 Extended identifier mask bit 0 Extended identifier mask bit 1 Extended identifier mask bit 2 Extended identifier mask bit 3 Extended identifier mask bit 4 Extended identifier mask bit 5 ? ? ? ? ? ? ? O O O O O O O O O O O O O O Name Function At reset ? R O W1 O 0: Mask identifier bit (don’t care) 1: Compare identifier bit These bits mask the corresponding bits of the acceptance code register 4, Figure 2.4.10 from the acceptance filtering. Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 2.4.15 Structure of CAN acceptance mask register 4 (CAM4) CAN receive control register b7 b6 b5 b4 b3 b2 b1 b0 CAN receive control register (CREC) [Address: 003D16] B Name Function1 R0: Receive buffer empty (undefined) 0 Receive buffer control bit R1: Receive buffer full W0: Release (clear) receive buffer W1: No operation 1 2 3 Reserved 4 5 6 7 Auto-receive disable bit2 Reserved 0: Auto-receive enabled 1: Auto-receive disabled When these bits are read out, the values are "0". Don’t write to "1" Receive status bit 0: CAN module idle or transmitting 1: CAN module receiving 0 0 0 0 0 0 0 O O O O O O O X X X X X O X 0 O O At reset R W When these bits are read out, the values are "0". Don’t write to "1". Note 1: R0/R1 denote read access, W0/W1 denote write access. Note 2: Suppresses reception of self-initiated/transmitted frames; for details see section 2.4.8, (5). Fig. 2.4.16 Structure of CAN receive control register (CREC) 7630 Group User’s Manual 2-43 $33/,&$7,21 2.4 Controller Area Network (CAN) module CAN transmit abort register b7 b6 b5 b4 b3 b2 b1 b0 CAN transmit abort register (CABORT) [Address: 003E16] B Name Function1 R0: No transmit abort requested 0 Transmit abort control bit R1: Transmit abort requested W0: Clear transmit abort request W1: Transmit abort requested 1 2 3 4 5 6 7 Not used Undefined at read. 0 0 0 0 0 0 0 O O O O O O O X X X X X X X 0 O O2 At reset R W Note 1: R0/R1 denote read access, W0/W1 denote write access. Note 2: Setting this bit to “1” is enabled only when CTRM.3 (Figure 2.4.3) is set. Fig. 2.4.17 Structure of CAN transmit abort register (CABORT) CAN transmit/receive buffer registers 0 b7 b6 b5 b4 b3 b2 b1 b0 CAN transmit buffer register 0 (CTB0) [Address: 004016] CAN receive buffer register 0 (CRB0) [Address: 005016] B 0 1 2 3 4 5 6 7 Not used When these bits are read out, the values are "0". Don’t write to "1". Name Standard identifier bit 6 Standard identifier bit 7 Standard identifier bit 8 Standard identifier bit 9 Standard identifier bit 10 For CTB0: These bits represent part of the identifier field of a frame to be transmitted. For CRB0: These bits represent part of the identifier field of a frame received. Function At reset ? ? ? ? ? 0 0 0 R O O O O O O O O W O O O O O X X X Fig. 2.4.18 Structure of CAN transmit/receive buffer registers 0 (CTB0/CRB0) 2-44 7630 Group User’s Manual $33/,&$7,21 2.4 Controller Area Network (CAN) module CAN transmit/receive buffer registers 1 b7 b6 b5 b4 b3 b2 b1 b0 CAN transmit buffer register 1 (CTB1) [Address: 004116] CAN receive buffer register 1 (CRB1) [Address: 005116] B 0 1 2 3 4 5 6 7 IDE bit1 RTR2/SRR 3 bit Standard identifier bit 0 Standard identifier bit 1 Standard identifier bit 2 Standard identifier bit 3 Standard identifier bit 4 Standard identifier bit 5 For CTB1: These bits represent part of the identifier field of a frame to be transmitted. For CRB1: These bits represent part of the identifier field of a frame received. Name Function 0: Standard format 1: Extended format RTR bit (frames of standard format) or SRR bit (frames of extended format) At reset ? ? ? ? ? ? ? ? R O O O O O O O O W O O O O O O O O Note 1: Identifier extension bit Note 2: Remote transmission request bit Note 3: Substitute remote request bit Fig. 2.4.19 Structure of CAN transmit/receive buffer registers 1 (CTB1/CRB1) CAN transmit/receive buffer registers 2 b7 b6 b5 b4 b3 b2 b1 b0 CAN transmit buffer register 2 (CTB2) [Address: 004216] CAN receive buffer register 2 (CRB2) [Address: 005216] B 0 1 2 3 4 5 Not used 6 7 Name Extended identifier bit 14 Extended identifier bit 15 Extended identifier bit 16 Extended identifier bit 17 For CTB2: These bits represent part of the identifier field of a frame to be transmitted. For CRB2: These bits represent part of the identifier field of a frame received. Function At reset ? ? ? ? 0 0 0 0 R O O O O O O O O W O O O O X X X X When these bits are read out, the values are "0". Don’t write to "1". Fig. 2.4.20 Structure of CAN transmit/receive buffer registers 2 (CTB2/CRB2) 7630 Group User’s Manual 2-45 $33/,&$7,21 2.4 Controller Area Network (CAN) module CAN transmit/receive buffer registers 3 b7 b6 b5 b4 b3 b2 b1 b0 CAN transmit buffer register 3 (CTB3) [Address: 004316] CAN receive buffer register 3 (CRB3) [Address: 005316] B 0 1 2 3 4 5 6 7 Name Extended identifier bit 6 Extended identifier bit 7 Extended identifier bit 8 Extended identifier bit 9 Extended identifier bit 10 Extended identifier bit 11 Extended identifier bit 12 Extended identifier bit 13 For CTB3: These bits represent part of the identifier field of a frame to be transmitted. For CRB3: These bits represent part of the identifier field of a frame received. Function At reset ? ? ? ? ? ? ? ? R O O O O O O O O W O O O O O O O O Fig. 2.4.21 Structure of CAN transmit/receive buffer registers 3 (CTB3/CRB3) CAN transmit/receive buffer registers 4 b7 b6 b5 b4 b3 b2 b1 b0 CAN transmit buffer register 4 (CTB4) [Address: 004416] CAN receive buffer register 4 (CRB4) [Address: 005416] B 0 Name r1 bit (reserved bit 1) Function For CTB4: Set this bit to “0” (must be sent dominant; applicable for extended format only). 0: Data frame 1: Remote frame At reset ? R O W O 1 2 3 4 5 6 7 RTR1 bit Extended identifier bit 0 Extended identifier bit 1 Extended identifier bit 2 Extended identifier bit 3 Extended identifier bit 4 Extended identifier bit 5 ? ? ? O O O O O O O O O O O O O O For CTB4: These bits represent part of the identifier field of a frame to be transmitted. For CRB4: These bits represent part of the identifier field of a frame received. ? ? ? ? Note 1: Remote transmission request bit Fig. 2.4.22 Structure of CAN transmit/receive buffer registers 4 (CTB4/CRB4) 2-46 7630 Group User’s Manual $33/,&$7,21 2.4 Controller Area Network (CAN) module CAN transmit/receive buffer registers 5 b7 b6 b5 b4 b3 b2 b1 b0 CAN transmit buffer register 5 (CTB5) [Address: 004516] CAN receive buffer register 5 (CRB5) [Address: 005516] B 0 DLC bit 0 Name Function The data length code indicates the number of data bytes in a data frame: b3b2b1b0 At reset ? R O W O 1 2 3 4 5 6 7 DLC bit 1 DLC bit 2 DLC bit 3 r0 bit (reserved bit 0) 0000: Zero data bytes 0001: One data byte 0010: Two data bytes … 0111: Seven data bytes 1000: Eight data bytes For CTB5: Set this bit to “0” (must be sent dominant). ? ? ? ? ? O O O O O O O O O O O O O O Not used When these bits are read out, the value are "0". Don't write to "1". ? ? Fig. 2.4.23 Structure of CAN transmit/receive buffer registers 5 (CTB5/CRB5) CAN transmit/receive buffer registers 6 to D b7 b6 b5 b4 b3 b2 b1 b0 CAN transmit buffer registers 6 to D (CTB6 to CTBD) [Addresses: 004616 to 004D16] CAN receive buffer registers 6 to D (CRB6 to CRBD) [Addresses: 005616 to 005D 16] B 0 1 2 3 4 5 6 7 Data bit 0 Data bit 1 Data bit 2 Data bit 3 Data bit 4 Data bit 5 Data bit 6 Data bit 7 For CRBi: These bits represent the byte number (i – 6) of the data field of a frame received. (i = 6 to D16) For CTBi: These bits represent the byte number (i – 6) of the data field of a frame to be transmitted. Name Function At reset ? ? ? ? ? ? ? ? R O O O O O O O O W O O O O O O O O Fig. 2.4.24 Structure of CAN transmit/receive buffer registers 6 to D (CTB6–D/CRB6–D) 7630 Group User’s Manual 2-47 $33/,&$7,21 2.4 Controller Area Network (CAN) module 2.4.4 Operational modes The module features three operational modes which can be selected by the sleep control bit CTRM.0 and the reset/configuration control bit CTRM.1 of the CAN transmit/control register (Figure 2.4.3). Mode transitions may be carried out according to Figure 2.4.25. Normal (run) mode CTRM.1 = 0, CTRM.0 = 0 receiving idle transmitting M .1 CTR Reset Configuration mode CTRM.1 = 1 CTRM.0 = 0 =0 1 M .1 = C TR CTR M. 0 =0 CTR M.0 = 1 Sleep mode CTRM.1 = 1 CTRM.0 = 1 Fig. 2.4.25 Transitions among operational modes (1) Configuration mode This mode is used to initialize (refer to section 2.4.5) or reset (refer to section 2.4.6) the module. Entering the configuration mode initiates the following functions by the module: • Suspend communication functions • Set P31/CTX output to recessive (if P31 is configured as CTX output port; see CTRM.2 in Figure 2.4.3) • Unlock the following configuration register to enable initialization: (1) acceptance code and mask registers (CACi/CAMi, Figures 2.4.6 to 2.4.15), (2) CAN bus timing control registers (CBTCONi, Figures 2.4.4 and 2.4.5) • Set module to error active state and clear the internal error counters (refer to section 2.4.12) • Clear transmit request, transmit buffer control and transmit status bits of CTRM (Figure 2.4.3) • Clear receive buffer control and receive status bits of CREC (Figure 2.4.16) • Clear transmit abort bit of CABORT (Figure 2.4.17) The values of the remaining bits of CTRM, CREC and of other CAN module related configuration registers (PCON, CBTCON1, CBTCON2, CAC0 to CAC4, CAM0 to CAM4) retain the values they had before entering the configuration mode. The contents of the transmit and receive buffer registers CTBi/CRBi (Figures 2.4.19 to 2.4.24) are undefined in configuration mode. The module is set to configuration mode upon MCU reset. Note: Switching the module from normal (run) to configuration mode during an ongoing transmission suspends communication immediately; this causes a corrupted frame on the bus. To avoid the corrupt frame, either await the successful transmission (see section 2.4.9) or issue an abort transmission request (see section 2.4.10) before attempting the mode transition. (2) Normal (run) mode Entering this mode initiates the following functions by the module: • Release communication functions; the module becomes an active node on the network and may transmit and receive CAN frames. For details on the transmit and receive operations as well as corresponding interrupt functions see sections 2.4.8 to 2.4.11. 2-48 7630 Group User’s Manual $33/,&$7,21 2.4 Controller Area Network (CAN) module • Lock the following registers to prevent accidental modifications: (1) acceptance code and mask registers (CACi/CAMi, Figures 2.4.6 to 2.4.15), (2) CAN bus timing control registers (CBTCONi, Figures 2.4.4 and 2.4.5) • Release the internal fault-confinement logic, transmit-, and receive error counters; the module may leave the error active state depending on the error counts (refer to section 2.4.12). Ensure to initialize the module by using the above mentioned configuration mode before entering normal (run) mode; for details refer to section 2.4.5. Within normal (run) mode the module can be in three different sub-modes, depending on which type of communication functions are actually performed (see Figure 2.4.26): • Idle: The module’s receive and transmit sections are inactive. • Receiving: The module is receiving a frame sent by another node. • Transmitting: The module transmits a frame. Simultaneously, the module may receive its own frame; this is called auto-receive function, for details refer to section 2.4.8, (5). From CPU side, the sub-modes may be monitored by the receive- and transmit status bits CREC.1 (Figure 2.4.16) and CTRM.7 (Figure 2.4.3). Module idle start a transmission finish transmission CTRM.7 = 0 CREC.1 = 0 detect an SOF finish reception Module transmitting CTRM.7 = 1 CREC.1 = 0 Module receiving CTRM.7 = 0 CREC.1 = 1 loose arbitration Fig. 2.4.26 Transitions among module sub-modes (3) Sleep mode This mode enables reduced power consumption by stopping the clock of the module; consequently all functions (incl. communication) are suspended. Setting the sleep control bit CTRM.1 (Figure 2.4.3) switches the module to sleep mode. Upon entering this mode, the module’s clock supply stops immediately. CAN related registers retain their contents upon entering sleep mode. Enter or leave sleep mode via configuration mode only (refer to Figure 2.4.25). Warning: Switching the module from normal (run) mode straight to sleep mode (bypassing configuration mode) may cause erroneous frames being sent to the bus or a CTX terminal forcing the bus to dominant level permanently. 7630 Group User’s Manual 2-49 $33/,&$7,21 2.4 Controller Area Network (CAN) module 2.4.5 Module initialization Initializing the module comprises several steps. Before attempting to access the registers involved the following items must be considered: • Acceptance filter The CAN acceptance code registers CACi (Figures 2.4.6 to 2.4.10) and CAN acceptance mask registers CAMi (Figures 2.4.11 to 2.4.15) need to be initialized. For details on the acceptance filter see section 2.4.7. • Bit timing The time for the transmission of a single bit consists of four segments: • Synchronization segment (SS) • Propagation time segment (PTS) • Phase buffer segment 1 (PBS1) • Phase buffer segment 2 (PBS2) SS is of fixed length (one time-quantum), but the length of PTS, PBS1/2 must be programmed by the bus timing control registers CBTCONi (Figures 2.4.4 and 2.4.5). Figure 2.4.27 shows the segmentation of one bit-time and the possible range for each segment to be programmed. Note: The CAN specification defines the sum of all time quanta within one bit-time between 8 and 25. bit-time: tbt SS Tss PTS Tpts PBS1 Tpbs1 PBS2 Tpbs2 Segment Tss Tpts Tpbs1 Tpbs2 sample point Range in time quanta Min. 1 (fixed) 1 1 1 8 8 8 Max. Fig. 2.4.27 Segmentation of bit-time The sample point is the point within a bit-time where the bus level is known as the value of that respective bit. Its position is between phase buffer segment 1 and phase buffer segment 2. The sample point must be defined in common for all active nodes on the network. • Resynchronization jump width The resynchronization jump width can be programmed via CBTCON2 (Figure 2.4.5). Note: The CAN specification defines resynchronization jump width as min(4,Tpbs1). • Sampling The sampling control bit CBTCON1.4 (Figure 2.4.4) allows to decide the bit level based on either a single or three samples. With single sampling, the level is sampled at the defined sample point (refer to Figure 2.4.27). Triple sampling takes two additional samples two and four cycles of f(XIN) before the defined sample point; the bit level is decided on the majority of the three samples. Triple sampling implements a means of digital filtering being appropriate if the bus signal is contaminated by noise. • Baud rate The module contains a programmable prescaler which is clocked by the MCUs internal clock frequency fφ. This prescaler allows division ratios of 1 to 1/16 (refer to Figure 2.4.4). The baud rate can be calculated as follows, where p is the prescaler division ratio: f CAN f 1 φ = ----- = --------------------------------------------------------------------------t bt p ⋅ ( 1 + Tpts + T pbs1 + T pbs2 ) • Dominant polarity The polarity control register PCON (Figure 2.2.9) allows to select the dominant level either “high” or “low”. This setting depends on the transceiver; please refer to the specification of the device/circuit in use. 2-50 7630 Group User’s Manual $33/,&$7,21 2.4 Controller Area Network (CAN) module • Auto-receive function If receiving of CAN frames originating by the module itself are not required, the auto-receive disable bit CREC.6 (Figure 2.4.16) should be set. • CAN interrupts The module features six interrupts, each of them can be either enabled or disabled by the corresponding control bits of the interrupt control registers ICONA and ICONB; refer to section 2.4.11. • Enable CAN transmit pin Configure Port P3 1/CTX as CAN transmit output pin by setting the port double function control bit CTRM.2 (Figure 2.4.3) before starting the communication functions of the module. Example Figure 2.4.28 shows an example of the initialization sequence required. At first, the module is switched to configuration mode (for details refer to section 2.4.4) to enable altering the special function registers. After that, the related SFRs are initialized with the corresponding parameters (see below). Finally, the module is switched to normal (run) mode to enable the communication and to protect the critical SFRs from being altered accidentally. The following table shows the conditions being used below: Item Acceptance filtering Tpts Tpbs1 Tpbs2 Prescaler division ratio Resynchronisation jump width Sampling Dominant polarity Auto-receive CAN interrupts 1 4 4 1 4 single low disabled not defined here (should be initialized) These settings result in 10 time quanta per bit; the corresponding baudrate is 500kbps at f(XIN) = 10MHz (equivalent to fφ=5MHz). Setting Description Filtering disabled; accept all identifiers. These conditions result in CAN bus timing control register values of CBTCON1=00 16 and CBTCON2=DB16. 7630 Group User’s Manual 2-51 $33/,&$7,21 2.4 Controller Area Network (CAN) module Start of module initialization ; enter config mode (1) seb 1,CTRM (1) CTRM b7 b0 0 0 0 1 1 0 Module awake Switch to config mode and reset Select P31 as CTX output port ; Wake up (1) clb 0,CTRM ; Dominant ’L’ (1) clb 1,PCON ; Activate CTX (1) seb 2,CTRM ; Baud rate (2), (3) ldm #0,CBTCON1 ldm #0DBh,CBTCON2 ; no auto-receive (4) seb 6,CREC (3) CBTCON2 b7 cleared by module (2) CBTCON1 b7 b0 0 0 0 0 0 0 0 0 CAN baud rate prescaler =1 One sample per bit Propagation time segment = 1 b0 1 1 0 1 1 0 1 1 Phase buffer segment 1 = 4 Phase buffer segment 2 = 4 Sychronization jump width = 4 (4) CREC b7 b0 0 1 0 0 cleared by module ; acceptance filtering (5) ldm #0,CAM0 ldm #0,CAM1 ldm #0,CAM2 ldm #0,CAM3 ldm #0,CAM4 auto-receive interrupt disabled (5) CAM0 CAM1 CAM2 CAM3 CAM4 b7 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mask all identifier bits ; enter normal mode (6) clb 1,CTRM (6) CTRM b7 b0 0 0 0 1 0 0 End of module initialization Switch to normal mode Fig. 2.4.28 Module initialization sequence 2-52 7630 Group User’s Manual $33/,&$7,21 2.4 Controller Area Network (CAN) module 2.4.6 Module reset The sequence shown in Figure 2.4.29 initiates a module reset by switching the module from normal (run) to configuration mode and back to normal (run) mode again. For details on configuration and normal (run) mode refer to section 2.4.4. Start of module reset (1)(2) CTRM b7 b0 0 0 0 p 1 0 ; enter config mode (1) seb 1,CTRM Module in configuration mode No transmission request CPU access possible Module idle or receiving (2) Cleared by module: CTRM.3, CTRM.5, CTRM.7, CREC.0, CREC.1, CABORT.0 (2) CREC b7 b0 p 0 0 Receive buffer empty Module idle (2) CABORT b7 b0 0 No transmit abort request ; enter normal mode (3) clb 1,CTRM (3) CTRM b7 b0 0 0 0 p 0 0 End of module reset Module in normal mode ’p’: previous value of the bit retained Fig. 2.4.29 Module reset sequence Note: Do not reset the module starting from sleep mode. 7630 Group User’s Manual 2-53 $33/,&$7,21 2.4 Controller Area Network (CAN) module 2.4.7 Acceptance filtering The module contains a hardware filtering circuit to screen out the useless messages out of the message stream and thereby reduce CPU load. This filter probes the identifier field of any frame on the bus and decides which frames are relevant to the given node and which may be abandoned. (1) Register structure The hardware implements a single condition identifier filter by a set of acceptance code CACi (Figures 2.4.6 to 2.4.10) and acceptance mask CAMi (Figures 2.4.11 to 2.4.15) registers. These registers cover the entire 29-bit identifier scale (extended format); however 11-bit identifiers (standard format) can be handled as well. The registers (shown in Figure 2.4.30) can be modified in configuration mode (refer to section 2.4.5) only. name 7 Acceptance code registers: CAC0 CAC1 CAC2 CAC3 CAC4 CEID13 CEID 5 CEID12 CEID 4 CEID11 CEID 3 CEID10 CEID 2 CSID 5 CSID 4 CSID 3 CSID10 CSID 2 CSID 9 CSID 1 CEID17 CEID 9 CEID 1 CSID 8 CSID 0 CEID16 CEID 8 CEID 0 CEID15 CEID 7 CEID14 CEID 6 CSID 7 0 CSID 6 Address 003316 003416 003516 003616 003716 Select the bit pattern of identifiers which should pass acceptance filtering. 7 CAM0 CAM1 CAM2 CAM3 CAM4 MEID13 MEID5 MEID12 MEID4 MEID11 MEID3 MEID10 MEID2 MSID5 MSID4 MSID3 MSID10 MSID2 MSID9 MSID1 MEID17 MEID9 MEID1 MSID8 MSID0 MEID16 MEID8 MEID0 MEID15 MEID 7 MEID14 MEID 6 MSID 7 0 MSID 6 Acceptance mask registers: 003816 003916 003A16 003B16 003C16 0 : Mask identifier bit 1 : Compare identifier bit with acceptance code register bit Shaded bits of CAMi must be cleared. Fig. 2.4.30 Structure of acceptance mask/code registers (2) Operation Acceptance filtering starts after detecting the start-of-frame of a CAN message. The content of the acceptance mask registers define which identifier bits have to be subjected to comparison with the corresponding bits of the acceptance code registers. If the acceptance filter judges an incoming frame relevant, the frame is—depending on the availability of a receive buffer—either stored in a receive buffer or a CAN overrun interrupt (COVR) is issued by setting the corresponding interrupt request bit. For further details on the receive buffer system and the overrun interrupt refer to sections 2.4.8 and 2.4.11. (3) Schematic of acceptance filter The acceptance filter mechanism (see Figure 2.4.31) comprises one gate which compares the acceptance code register bit with the corresponding identifier bit of the frame being received, and one gate which tests the relevance of this bit for the acceptance filter process. When all acceptance bits are true, the module rates the frame relevant and attempts to store it to a receive buffer. 2-54 7630 Group User’s Manual $33/,&$7,21 2.4 Controller Area Network (CAN) module Acceptance mask bit 0 Acceptance code bit 0 Identifier bit 0 Acceptance bit 0 Acceptance bit 28 Acceptance bit N Acceptance mask bit N Acceptance code bit N Identifier bit N Acceptance mask bit 28 Acceptance code bit 28 Identifier bit 28 N = 1 to 27 Id match 29 Fig. 2.4.31 Acceptance filter logic 2.4.8 Message reception The module is equipped with two physical receive buffers. This double buffer architecture allows simultaneous CPU-processing of a previously received frame and reception/storage of a new frame by the module. To simplify the software handling both buffers are memory mapped to the same address range (005016 to 005D16). The module’s internal receive logic controls access to the buffers so that one buffer (later on called foreground buffer) can be read out by the CPU while the other buffer (background buffer) can be written to by the module. The user is able to switch back and forth between both buffers by one control bit; however the individual buffers can not be addressed directly. This architecture allows sequential handling of the incoming frames on an one-byone basis. The receive buffers support both standard and extended frame formats of data and remote type. The buffers hold the following information on the received frame: • Identifier (standard or extended), • Frame type (data frame or remote frame), • Data length (in case of a data frame), and • Data bytes (in case of a data frame). (1) Message storage As explained above, the module features two receive buffers; after initialization both buffers are empty (undefined). Upon successful reception of the first relevant (refer to section 2.4.7) frame the module will: 1. Store the frame in one of the buffers. 2. Switch the buffer to foreground to permit CPU access. 3. Flag the reception by special function bits and interrupt service request (details in section (2)). The foreground buffer holding the message received is now under (exclusive) control of the CPU, while the background buffer is still vacant. After having processed the buffer contents, the CPU should release the buffer and thereby return buffer control to the module. Following to release, the buffer content is not available to the CPU any more and can not be recaptured in any way. 7630 Group User’s Manual 2-55 $33/,&$7,21 2.4 Controller Area Network (CAN) module A second message can be stored to the background buffer while the CPU still deals with the foreground buffer; for an example see Figure 2.4.34: while the CPU still processes frame C, the module simultaneously receives frame D. The control of the buffers is done via the receive buffer control bit CREC.0 (Figure 2.4.16) as shown in Figure 2.4.32. In normal (run) mode, CREC.0 can be cleared by the CPU but can only be set by the CAN module. Set by CAN module Cleared by user s/w A B bus Receive buffer control bit CREC.0 Foreground receive buffer content CRB0 to CRBD undefined A undefined B Fig. 2.4.32 Receive buffer handling (2) Receive process The receive sequence is initialized by the start-of-frame of a new incoming message. The user software can check this status by the transmit status bit CTRM.7 and the receive status bit CREC.1. The module status changes from idle/transmitting to receiving. During the reception of a message, the receive status bit CREC.1 is kept high. It is cleared after the end of frame (for details refer to section (3) below). If the message is accepted and received without any errors, the module initiates the following actions: 1. Set CAN successful receive (CSR) interrupt request bit IREQA.4. 2. Enable CPU access to the buffer (i.e., switch it from background to foreground). 3. Set receive buffer control bit CREC.0. If the CPU still processes a previously received frame in the foreground buffer (and has not released the buffer yet), the actions 2 and 3 are postponed. In this case, the module will continuously monitor CREC.0 and wait for the flag being cleared by user s/w. After that, the module will execute the actions 2 and 3. The frame reception can be observed from CPU side either by polling of IREQA.4 or CREC.0 or by CSR interrupt service. After having processed the buffer contents, the receive buffer control bit should be cleared by the CPU, in order to give control of the buffer back to the module. This kind of handshaking enables the module to use the buffer to store the next frame to be received; consequently data read from the receive buffer address range is undefined until the next frame reception. Note: If the reception function is implemented based on CSR interrupt service, reconfirm the CREC.0 status after clearing it. If both buffers are already occupied before entering the CSR interrupt service routine, both buffers must be processed in one CSR interrupt service. However, it is recommended to optimize the timing of the interrupt system for minimum latency and short execution time to avoid the possibility of CAN overrun situations; see section (4). If the requirements to avoid overrun situations are fullfilled, one CSR interrupt service has to deal with one single frame only (because each frame reception triggers one CSR interrupt service request). Figure 2.4.33 shows the receive process flowcharts from CAN module and CPU side. Section (3) discusses the timing details on the module’s receive processing. 2-56 7630 Group User’s Manual $33/,&$7,21 2.4 Controller Area Network (CAN) module CAN module Receive process from user side and CAN module side Receiving new message? Yes Write 1 Set receive status bit No CREC: Acceptance filter passed successfully? Yes No Buffer available? Yes Receive/Store message to receive buffer No Set CAN overrun interrupt request bit Set CAN successful receive interrupt request bit Finish frame reception No Receive buffer control bit = 0? Yes Switch buffer from background to foreground User software Await CSR interrupt or poll receive buffer control bit Read/process receive buffer Clear receive buffer control bit Write 0 CREC: Receive buffer control bit = 1? Yes CSR interrupt request bit = 1? Yes No CREC: Read CREC: Write 1 Write 0 Set receive buffer control bit Clear receive status bit Read 1 The two actions in the ’Yes’ branch (switching buffer, set receive buffer full flag) will be postponed until the receive buffer full flag has been cleared (by user s/w). The module monitors this bit continuously. Write 1 No End or Return from interrupt service routine If both buffers are already occupied before the CSR interrupt acceptence, CREC.0 will be 1 and the CSR interrupt has not been requested again (request bit = 0). Under this condition, both buffers should be read out. If the receive processing scheme in use in based on polling CREC.0 only (not CSR interrupt service), CREC.0 must be sampled only once at the beginning of the routine. Register symbols: Read or write Read or write 0 Read or write 1 Reserved Fig. 2.4.33 Flowchart of the receive process 7630 Group User’s Manual 2-57 $33/,&$7,21 2.4 Controller Area Network (CAN) module (3) Timing of receive sequence The timing diagrams in Figure 2.4.34 shows the status of the internal special function bits and the contents of the foreground receive buffer during receive sequence. Of course this timing diagram depends on the application software and actual communication model (i.e., scheduling of messages on the bus); therefore the diagram should be considered an example. The time between the occurrence of the receive interrupt request and the clearing of this request bit depends on the interrupt system of the actual application. The latency of the interrupt depends on the execution time of all interrupt service routines of the application unless interrupt nesting is enabled. The conditions used in the timing diagram are: • Module in virgin condition (as after module reset) • Acceptance filtering disabled (mask all identifier bits) • Buffer content processing by CAN successful receive (CSR) interrupt service • Execution time of CSR service routine shorter than the frames on the bus • Interrupt system of the application optimised for minimum latency of interrupts Start of frame P32/CRX receive status bit CREC.1 CAN successful receive interrupt request bit IREQA.4 receive buffer control bit CREC.0 Ack End of frame tack–rsb = 9·tbt tack–csr ≈ 6·tbt tack–rbc ≈ 6·tbt P32/CRX receive status bit CREC.1 CAN successful receive interrupt request bit IREQA.4 receive buffer control bit CREC.0 foreground receive buffer contents CRB0 to CRBD A B C D E F A B C D E F : undefined foreground receive buffer Fig. 2.4.34 Receive sequence timing During a successful reception the module alters the special function bits CREC.1, IREQA.4 and CREC.0 according to the following sequence: 1. Set CREC.1 within the start-of-frame bit. 2. Set IREQA.4 and CREC.0 within the seventh bit-time of the end of frame field. 3. Clear CREC.1 after the second bit-time of the intermission field. (4) Avoiding CAN overrun interrupts The CAN overrun interrupt (COVR) is requested upon reception of a relevant frame when both receive buffers are preoccupied by previously received frames because the CPU has not released a buffer yet. The frame causing the CAN overrun interrupt can not be stored and hence is lost. 2-58 7630 Group User’s Manual $33/,&$7,21 2.4 Controller Area Network (CAN) module The timing diagram in Figure 2.4.35 shows one example for a condition leading to a COVR request. The conditions used in the timing diagram are: • Module in virgin condition (as after module reset) • Acceptance filtering disabled (mask all identifier bits) • Buffer content processing by CAN successful receive (CSR) interrupt service • Execution time of the CSR interrupt service routine longer than the frames on the bus • Interrupt system of the application optimised for minimum latency of interrupts P32/CRX receive status bit CREC.1 CAN successful receive interrupt request bit IREQA.4 receive buffer control bit CREC.0 foreground receive buffer contents CRB0 to CRBD CAN overrun interrupt request bit IREQA.5 A B C D E F 1/fφ A B C D F SOF P32/CRX CAN overrun interrupt request bit IREQA.5 Arbitration field control field tack–covr = 7·tbt : undefined foreground receive buffer : s/w clears CREC0 after end of frame C; module sets CREC0 one cycle later : CPU still processes frame C in foreground buffer, while the background buffer holds frame D; frame E can not be stored and is lost. Fig. 2.4.35 Receive sequence timing (overrun condition) To avoid an overrun condition, the time between a successful reception and the release of receive buffer by the CPU must be shorter than the shortest possible frame in the network. This can be accomplished by optimization of the applications interrupt system towards minimum latency and interrupt execution times. (5) Auto-receive function The auto-receive disable bit CREC.6 (Figure 2.4.16) allows to select two options regarding the handling of frames sent by the module: • Enabling auto-receive by clearing CREC.6 causes the module to subject a self-generated frame to the reception process described above; however, the following deviations apply: – Self-generated frames are not self-acknowledged. – CREC.1 remains “0” during the auto-receive process. The corresponding sub-mode according to Figure 2.4.26 is transmitting. A frame rated relevant by the acceptance filtering causes a successful receive interrupt request and possibly an overrun interrupt request (see section (4)). 7630 Group User’s Manual 2-59 $33/,&$7,21 2.4 Controller Area Network (CAN) module • Disabling auto-receive by setting CREC.6 causes the module to suspend all receive functions related to the receive control logic block (Figure 2.4.1) during the transmission process. The transmitting/receiving sub-mode of the normal mode shown in Figure 2.4.25 is disabled. Note: Disabling auto-receive does not affect the receive function related to the protocol controller block (required to monitor the bus level while transmitting). 2.4.9 Message transmission The module is equipped with one transmit buffer. Similar to the receive section, the architecture allows to transmit CAN frames on a one-by-one basis. Both standard and extended frame formats of data and remote type are supported. The programming sequence required to initiate a transmission comprises four steps, each step shall be described in detail below: 1. Check the module status (i.e., the availability of the transmit buffer). 2. Initialize the transmit buffer (the buffer content defines the frame to be transmitted). 3. Lock the transmit buffer (hands the buffer control to the module and protects the buffer from accidental modifications by the CPU). 4. Issue the transmit request (triggers the module to start the transmission). Once the transmission of a frame has been requested, the module takes care about bus arbitration, error handling and acknowledgement of the frame by other nodes. The frame is considered transmitted successfully if: • The frame could win arbitration, • no errors were detected during transmission, and • the frame gained acknowledgement by another node on the bus. In case of unsuccessful transmissions the module attempts to re-transmit the frame until transmission can be finished successfully or the transmit request is withdrawn by user software (refer to section 2.4.10). In case of an arbitration loss, the module transits to sub-mode receiving (refer to section 2.4.8 and Figure 2.4.26). The programming sequence and functionality is explained below and by the flow charts in Figure 2.4.38. (1) Check for availability of the transmit buffer Before the transmit buffer can be initialized, its availability must be checked; the transmit buffer control bit CTRM.5 must be “0” indicating the availability of the buffer and completion of the previous transmission. The user software can now initialize the transmit buffer. (2) Initialize the transmit buffer In the user software the identifier (standard or extended), the frame type (data or remote frame), length code/data bytes (in case of a data frame) have to be written to the transmit buffer (Figures 2.4.18 to 2.4.24). Only the transmit buffer registers relevant for the specific CAN frame need to be initialized (e.g. if only standard CAN frames are concerned, the transmit buffer registers CTB2 and CTB3 can be ignored). If the transmit buffer has been used for a previous transmission, the contents of the buffer are retained; therefore only the transmit buffer contents which need to be changed versus the previous frame have to be initialized. Figure 2.4.36 shows the transmit buffer register organisation. 2-60 7630 Group User’s Manual $33/,&$7,21 2.4 Controller Area Network (CAN) module Name CTB0 CTB1 CTB2 CTB3 CTB4 CTB5 CTB6 CTB7 CTB8 CTB9 CTBA CTBB CTBC CTBD EID13 EID5 EID12 EID4 EID11 EID3 EID10 EID2 r0 SID5 SID4 SID3 7 SID10 SID2 SID9 SID1 EID17 EID9 EID1 DLC3 SID8 SID0 EID16 EID8 EID0 DLC2 SID7 RTR/SRR 0 SID6 IDE EID14 EID6 r1 DLC0 Offset 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 EID15 EID7 RTR DLC1 Data byte 0 Data byte 1 Data byte 2 Data byte 3 Data byte 4 Data byte 5 Data byte 6 Data byte 7 Fig. 2.4.36 Transmit buffer organization Altogether the following items of the transmit buffer need to be initialized: • IDE bit CBT1.0: this bit represents the identifier extension (IDE) bit of a frame. • RTR/SRR bit CBT1.1: for standard format frames, this bit represents the remote transmission request (RTR) bit of the arbitration field; for extended format frames it represents the substitute remote request (SRR) bit of the arbitration field. • RTR bit CBT4.1: this bit represents the remote transmission request (RTR) bit of the arbitration field of an extended format frame; not relevant for standard format frames. • Reserved bit r0 CBT5.4: this bit represents the reserved bit r0 of the control field of a standard or extended format frame; should be set to “0”/sent dominant (refer to the CAN specification). • Reserved bit r1 CBT4.0: this bit represents the reserved bit r0 of the control field of an extended format frame; not relevant for standard format frames; should be set to “0”/sent dominant (refer to the CAN specification). • Identifier bits of CBT0 to CBT4: these bits represent the identifier of the arbitration field of a frame; CBT2 to CBT4 hold the extended identifier bits and are not relevant for standard format frames. • DLC bits of CBT5: these bits represent the data length code of the data field of a data frame; not relevant for remote frames. • Data bits of CBT6 to CBTD: these bits represent the data field of a data frame; not relevant for remote frames. For settings of the IDE-, RTR/SRR-, RTR-, r0- and r1 bits to be programmed refer to the table below: Frame format standard format (11-bit identifier) extended format (29-bit identifer) Frame type data frame remote frame data frame remote frame IDE 0 0 1 1 RTR/SRR 0 1 1 1 RTR X X 0 1 r0 0 r1 X 0 0 (3) Lock the transmit buffer Once the transmit buffer is initialized, the transmit buffer control bit of CTRM (Figure 2.4.3) should be set to “1”. This locks the transmit buffer thereby protects it from being altered accidentally. After locking, data read from the address range of the transmit buffer is undefined. The buffer remains locked until either the trans- 7630 Group User’s Manual 2-61 $33/,&$7,21 2.4 Controller Area Network (CAN) module mission process could be finished successfully, or a transmit abort is requested (see section 2.4.10); the buffer can not be unlocked by clearing the transmit buffer control bit from CPU side. (4) Issue transmission request Finally, the transmission can be started by setting the transmission control bit of CTRM (Figure 2.4.3). Setting this bit gives control of the buffer to the CAN module; the module attempts to transmit the frame defined by the transmit buffer contents following the rules of the CAN specification. After a successful transmission (without errors) the module will: • Clear the transmit buffer control bit CTRM.5. • Clear the transmit request bit CTRM.3. • Set the CAN successful transmit (CST) interrupt request bit IREQA.3. Note: The CAN successful receive interrupt (CSR) interrupt may also be requested unless disabled by the auto-receive interrupt disable bit of CREC (Figure 2.4.16); refer to section 2.4.8, • too. (5) Timing of transmit sequence The timing diagram in Figure 2.4.37 shows the status of the internal special function bits during transmit sequence if the module wins bus arbitration. Start of frame P32/CRX transmit status bit CTRM.7 Ack End of frame Intermission ttsb–sof = (0 ~ 1)·tbt tack–tsb ≈ 10·tbt transmit request bit CTRM.3 transmit buffer control bit CTRM.5 CAN successful transmit interrupt request bit IREQA.3 ttrb–sof,min = 30/f(XIN) tack–trb = (7 ~ 8)·tbt tack–tbc = ( 7 ~ 8)·tbt tack–cst = (6 ~ 7)·tbt Fig. 2.4.37 Transmit sequence timing (arbitration win) After a transmission has been requested by setting CTRM.3, the module attempts to start the transmission at the next possible time (depending on the bus condition). During a successful transmission process the module alters the special function bits as follows: 1. Set transmit status bit CTRM.7 shortly before the recessive to dominant edge of the start-of-frame field. 2. Set CAN successful transmit interrupt request bit IREQA.3 within the last bit-time of the end-of-frame field. 3. Clear transmit request bit CTRM.3 and transmit buffer control bit CTRM.5 within the first bit-time after the end-of-frame field. 4. Clear transmit status bit CTRM.7 within the first bit-time after the intermission field. Upon arbitration loss, the module changes to receiving state beginning with the next bit-time after the occurrence of arbitration loss. The transition from transmitting to receiving state is flagged by clearing of CTRM.7 and setting of CREC.1 (see Figure 2.4.26). 2.4.10 Abort transmission A low priority frame in the transmit buffer may not gain bus access if the bus carries heavy traffic by medium priority frames. The low priority frame blocks the transmit buffer and causes significant delay in scheduling of further even high priority frames to be sent. This scenario is known as priority inversion. 2-62 7630 Group User’s Manual $33/,&$7,21 2.4 Controller Area Network (CAN) module To overcome this situation, the module features an abort transmission request function. This function is controlled by the transmit abort control bit CABORT.0 (Figure 2.4.17); setting this bit withdraws the transmit request of the frame currently occupying the transmit buffer. Requesting transmit abort during the transmission process (CTRM.7 = 1) does not interrupt the process to avoid causing erroneous frames being sent. In result of the abort transmit request, the module will: 1. Clear the transmit buffer control bit CTRM.5 (thereby release the buffer). 2. Clear the transmit request bit CTRM.3. 3. Clear the transmit abort control bit CABORT.0. As the abort transmission request might fall together with an ongoing transmission, the buffer might not be available immediately after issuing the abort transmission request. Therefore the re-initialization of the buffer should not be started before having confirmed its availability via CTRM.5 (refer to section 2.4.9). 7630 Group User’s Manual 2-63 $33/,&$7,21 2.4 Controller Area Network (CAN) module Transmit process from user side and CAN module side No transmit buffer vacant (CTRM.5=0)? Yes Read 0 CTRM: initialize transmit buffer registers set transmit buffer control bit CTRM.5 Write 1 set transmit request bit CTRM.3 Write 1 CAN module CTRM: Await CAN successful transmission Read 1 transmit request CTRM.3=1? Yes No User software Write 1 set transmit status bit CTRM.7 CTRM: start transmission No bus arbitration win? Yes continue transmission no errors detected? Yes clear transmit request bit clear transmit buffer control bit CTRM.3,5 set CST interrupt request bit No Write 0 CTRM: Symbols: Write 0 Read or Write 0 Read or Write 1 Reserved Clear transmit status bit CTRM: CTRM: Fig. 2.4.38 Flowchart of transmit process 2-64 7630 Group User’s Manual $33/,&$7,21 2.4 Controller Area Network (CAN) module 2.4.11 CAN interrupts The module provides six interrupt sources with separate interrupt vectors; each interrupt is requested by setting the corresponding interrupt request bit. Vector Address Interrupt name Requested upon successful transmission of a CAN frame successful reception of a CAN frame detecting a relevent frame on the bus while no receive buffer is vacant state transition from error active to error passive state transition from error passive to bus off detecting a recessive to dominant edge on CRX Description High CAN successful transmit (CST) CAN successful receive (CSR) section 2.4.9 section 2.4.8 “Avoiding CAN overrun interrupts”, Figure 2.4.35 section 2.4.12 section 2.4.12 section 2.4.13 FFF316 FFF116 Low FFF216 FFF016 Request bit IREQA.3 IREQA.4 Control bit ICONA.3 ICONA.4 CAN overrun (COVR) FFEF16 FFEE16 IREQA.5 ICONA.5 CAN error passive (CERP) CAN bus off (CBOF) CAN wake up (CWKU) FFED16 FFEB16 FFE916 FFEC16 FFEA16 FFE816 IREQA.6 IREQA.7 IREQB.0 ICONA.6 ICONA.7 ICONB.0 2.4.12 Error condition As defined in the CAN specification, the module features internal transmit and receive error counters; these counters serve to define the state of the module between the options error active, error passive and bus off. In normal (run) mode, the error counters are increased upon detection of an error and decreased upon successful transmission or reception of CAN frames following the rules of the CAN specification. These counters are internal registers and not available to the CPU; the transitions from error active to error passive state and from error passive to bus off are flagged by a request of the corresponding error passive (CERP) and bus off (CBOF) interrupts. In normal (run) mode, the receive and transmit error counters are under control of the module an can not be altered or read by the CPU. Upon switching to configuration mode however, the counters are cleared and the module is put to error active state. As defined in the CAN specification, the module takes part in normal bus communication and flags errors detected by sending an active error flag. After the module has transit to error passive state the module continues communication but errors detected are flagged by a passive error flag. In bus off state, the module suspends the communication and does not influence the bus any more; the CTX pin is kept at recessive level. Please refer to the state diagram in Figure 2.4.39 and to the CAN specification for details on the conditions leading to state-transitions. Transmit or receive error count greater than 127 reset Error active Transmit and receive error count less than 128 Error passive Transmit error count greater than 255 128 occurrences of 11 recessive bits Bus off Fig. 2.4.39 Error state diagram 7630 Group User’s Manual 2-65 $33/,&$7,21 2.4 Controller Area Network (CAN) module 2.4.13 Wake-up via CAN The module features a function to wake-up the CPU on CAN traffic. This feature is implemented by an external interrupt function on the P32/CRX input port. The wake-up interrupt is requested upon a recessive to dominant edge (by start-of-frame of a message sent by another node) on the P32/CRX. The initialization required to use the wake-up function is: 1. Clear CWKU interrupt request bit IREQB.0. 2. Set CWKU interrupt control bit ICONB.0. 3. Put module to sleep mode by setting the sleep control bit CTRM.0 (Figure 2.4.3); see section 2.4.4. 4. Set the pull transistor enable bit PUP3.2; this activates the pull transistor towards the recessive level (depending on the dominant polarity selected by PCON.1). 5. Put MCU to low-power mode (wait or stop mode). The first frame sent by another node awakens the CPU by an CWKU interrupt request. The module should be put to normal (run) mode again as part of the CWKU interrupt service; also the pull transistor should be disabled as part of this interrupt service routine. Note: The frame triggering the wake-up function can not be received and is lost. 2-66 7630 Group User’s Manual APPLICATION 2.5 Serial I/O 2.5 Serial I/O 2.5.1 Memory map of serial I/O 001216 001316 002016 002116 002216 002316 002416 002516 002616 002716 Serial I/O shift register (SIO) Serial I/O control register (SIOCON) UART mode register (UMOD) UART baud rate generator (UBRG) UART control register (UCON) UART status register (USTS) UART transmit buffer register 1 (UTBR1) UART transmit buffer register 2 (UTBR2) UART receive buffer register 1 (URBR1) UART receive buffer register 2 (URBR2) Fig. 2.5.1 Memory map of serial I/O related registers 7630 Group User’s Manual 2-67 APPLICATION 2.5 Serial I/O 2.5.2 Related registers Serial I/O shift register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O shift register (SIO) [Address : 001216] B Function At reset R W 0 A shift register for serial transmission and reception. At transmitting : Set transmission data. 1 At receiving : Store received data. 2 3 4 5 6 7 ? ? ? ? ? ? ? ? Note: A content of the Transmit buffer register cannot be read out. A data cannot be written to the Receive buffer register. Fig. 2.5.2 Structure of Serial I/O shift register Serial I/O control register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O control register (SIOCON) [Address : 001316] B 0 1 Name Clock divider selection bits b2 b1 b0 Function 0 0 0 : φ divided by 4 0 0 1 : φ divided by 8 0 1 0 : φ divided by 16 0 1 1 : φ divided by 32 1 0 0 : φ divided by 64 1 0 1 : φ divided by 128 1 1 0 : φ divided by 256 1 1 1 : φ divided by 512 0 : I/O port (P20, P21, P22) 1 : SIN, SOUT, SCLK output pin 0 : I/O port (P23) 1 : SRDY output pin 0 : LSB first 1 : MSB first At reset R W 0 0 2 3 4 5 6 7 P20/SIN, P21/SOUT and P22/SCLK function selection bit P23/SRDY function selection bit Transmission order selection bit 0 0 0 0 0 0 Synchronization clock selection bit 0 : External clock 1 : Internal clock Not used (“0” when read.) Fig. 2.5.3 Structure of Serial I/O control register 2-68 7630 Group User’s Manual APPLICATION 2.5 Serial I/O UART mode register b7 b6 b5 b4 b3 b2 b1 b0 UART mode register (UMOD) [Address : 002016] B 0 1 2 3 4 5 6 7 Stop bits selection bit Parity selection bit Parity enable bit UART word length selection bits Name Not used (“0” when read, don't write “1”.) Clock divider selection bits b2 b1 Function At reset R W 0 0 0 0 0 0 0 0 0 0 : φ divided by 1 0 1 : φ divided by 8 1 0 : φ divided by 32 1 1 : φ divided by 256 0 : One stop bit 1 : Two stop bits 0 : Even parity 1 : Odd parity 0 : Parity checking disabled 1 : Parity checking enabled b7 b6 0 0 : 7 bits 0 1 : 8 bits 1 0 : 9 bits 1 1 : Not used Fig. 2.5.4 Structure of UART mode register UART baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 UART baud rate generator (UBRG) [Address : 002116] B Function At reset R W 0 A count value of baud rate generator is set. 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? Fig. 2.5.5 Structure of UART baud rate generator 7630 Group User’s Manual 2-69 APPLICATION 2.5 Serial I/O UART control register b7 b6 b5 b4 b3 b2 b1 b0 UART control register (UCON) [Address : 002216] B 0 1 Name Transmit enable bit Receive enable bit Transmission initialization bit 2 Function 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled 0 : No action 1 : Initialize the transmit enable bit and transmit status register flags. Stop transmission. 0 : No action 1 : Initialize the receive enable bit and receive status register flags. At reset R W 0 0 0 Receive initialization bit 3 0 4 Not used (“0” when read, don't write “1”.) 5 6 7 0 0 0 0 Fig. 2.5.6 Structure of UART control register UART status register b7 b6 b5 b4 b3 b2 b1 b0 UART status register (USTS) [Address : 002316] B 0 1 Name Transmission register empty flag Transmission buffer empty flag Function 0 : Register full 1 : Register empty 0 : Buffer full 1 : Buffer empty 0 : Buffer full 1 : Buffer empty 0 : No parity error detected 1 : Parity error detected 0 : No framing error detected 1 : Framing error detected 0 : No overrun detected 1 : Overrun detected 0 : No error detected 1 : Error detected At reset R W 1 1 1 0 0 0 0 0 2 Receive buffer full flag 3 4 5 6 7 Receive parity error flag Receive framing error flag Receive overrun flag Receive error sum flag Not used (“0” when read.) Fig. 2.5.7 Structure of UART status register 2-70 7630 Group User’s Manual APPLICATION 2.5 Serial I/O UART transmit buffer register 1 UART transmit buffer register 2 b7 b6 b5 b4 b3 b2 b1 b0 UART transmit buffer register 1 (UTBR1) [Address : 002416] UART transmit buffer register 2 (UTBR2) [Address : 002516] B 0 1 2 3 4 5 6 7 Function Transmit data is written to this buffer register (consisting of low-order and high-order byte). At reset R W ? ? ? ? ? ? ? ? Fig. 2.5.8 Structure of UART transmit buffer register 1, 2 UART receive buffer register 1 UART receive buffer register 2 b7 b6 b5 b4 b3 b2 b1 b0 UART receive buffer register 1 (URBR1) [Address : 002616] UART receive buffer register 2 (URBR2) [Address : 002716] B 0 1 2 3 4 5 6 7 Function Receive data is read from this buffer register (consisting of low-order and high-order byte). At reset R W ? ? ? ? ? ? ? ? Fig. 2.5.9 Structure of UART receive buffer register 1, 2 7630 Group User’s Manual 2-71 APPLICATION 2.5 Serial I/O 2.5.3 Serial I/O connection examples (1) Control of peripheral IC equipped with CS pin Figure 2.5.10 shows connection examples with peripheral ICs using clock synchronous serial I/O mode. (1) Only transmission (using the SIN pin as an I/O port) Port SCLK SOUT CS CLK DATA (2) Transmission and reception Port SCLK SOUT SIN CS CLK IN OUT 7630 group Peripheral IC (OSD controller etc.) 7630 group Peripheral IC (E2PROM etc.) (3) Connecting ICs Port SCLK SOUT SIN Port CS CLK IN OUT Peripheral IC 1 CS CLK IN OUT 7630 group Peripheral IC 2 Note: “Port” is an output port controlled by software. Fig. 2.5.10 Serial I/O connection examples (1) 2-72 7630 Group User’s Manual APPLICATION 2.5 Serial I/O (2) Connection with microcomputer Figure 2.5.11 shows connection examples with other microcomputers using serial I/O. (1) Selecting an internal clock (2) Selecting an external clock SCLK SOUT SIN CLK IN OUT SCLK SOUT SIN CLK IN OUT 7630 group Microcomputer 7630 group Microcomputer (3) Using the SRDY signal output function (Selecting an external clock) SRDY SCLK SOUT SIN RDY CLK IN OUT (4) Using UART UCTS UTxD URTS URxD Port RxD Port TxD 7630 group Microcomputer 7630 group Microcomputer (5) Using UART (URTS, UCTS not use) UTxD URxD URTS UCTS RxD TxD 7630 group Microcomputer Note: “Port” is an output port controlled by software. Fig. 2.5.11 Serial I/O connection examples (2) 7630 Group User’s Manual 2-73 APPLICATION 2.5 Serial I/O 2.5.4 Setting of serial I/O transfer data format A clock synchronous or clock asynchronous (UART) is selected as a data format. Figure 2.5.12 shows a setting of serial I/O transfer data format. 1ST-9DATA-1SP ST LSB MSB SP 1ST-8DATA-1SP ST LSB MSB SP 1ST-7DATA-1SP ST LSB MSB SP 1ST-9DATA-1PAR-1SP ST LSB MSB PAR SP 1ST-8DATA-1PAR-1SP ST LSB MSB PAR SP 1ST-7DATA-1PAR-1SP ST LSB MSB PAR SP UART 1ST-9DATA-2SP ST LSB MSB 2SP 1ST-8DATA-2SP ST LSB MSB 2SP 1ST-7DATA-2SP ST LSB MSB 2SP Serial I/O 1ST-9DATA-1PAR-2SP ST LSB MSB PAR 2SP 1ST-8DATA-1PAR-2SP ST LSB MSB PAR 2SP 1ST-7DATA-1PAR-2SP ST LSB MSB PAR 2SP Clock synchronous serial I/O LSB first MSB first ST : Start bit SP : Stop bit PAR : Parity bit Fig. 2.5.12 Setting of serial I/O transfer data format 2-74 7630 Group User’s Manual APPLICATION 2.5 Serial I/O 2.5.5 Serial I/O application examples (1) Output of serial data (control of a peripheral IC) Outline : 4 -byte data is transmitted and received using the clock synchronous serial I/O. The CS signal is output to a peripheral IC through the port P3 3. P33 SCLK SOUT CS CLK DATA CS CLK DATA 7630 group Peripheral IC Fig. 2.5.13 Connection diagram [Output of serial data] Specifications : • • • • • The Serial I/O is used(the clock synchronous serial I/O is selected). Synchronous clock frequency : 125 kHz (f(X IN) = 8 MHz is divided by 64) Transfer direction : LSB first. The Serial I/O interrupt is not used. ___ Port P33 is connected to the CS pin (“L” active) of the peripheral IC for transmission control (the output level of port P3 3 i s controlled by software). Figre 2.5.14 shows an output timing chart of serial data. CS CLK DATA D00 D01 D02 D03 Note: The SOUT pin is in high impedance state after completion of data transfer. Fig. 2.5.14 Timing chart [Output of serial data] 7630 Group User’s Manual 2-75 APPLICATION 2.5 Serial I/O Figure 2.5.15 shows a setting of serial I/O related registers, and Figure 2.5.16 shows a setting of serial I/O transmission data. Serial I/O control register [Address: 001316] b7 b0 SIOCON 1001011 Clock divider selection bits : φ divided by 32 P20/SIN, P21/SOUT, P22/SCLK function selection bit : Use the serial I/O P23/SRDY function selection bit : SRDY output disabled Transmission order selection bit : LSB first Synchronization clock selection bit : Internal clock Interrupt request register C [Address: 000416] b7 b0 IREQC 0 Serial I/O interrupt request bit Use this bit to check if transmission of 1 byte is complete. “1” : Transmit complete Interrupt control register C [Address: 000716] b7 b0 ICONC 0 Serial I/O interrupt enable bit : Interrupt disabled Port P3 [Address: 000E16] b7 b0 P3 0 Set to “0” before transmission starts. Port P3 direction register [Address: 000F16] b7 b0 P3D 1 P33 : Output mode Fig. 2.5.15 Setting of serial I/O related registers [Output of serial data] 2-76 7630 Group User’s Manual APPLICATION 2.5 Serial I/O Serial I/O shift register [Address: 001216] b7 b0 SIO Write data to be transmitted. Check whether transmission of the previous data has been completed before writing data (bit 4 of the Interrupt request register C is set to “1”). Fig. 2.5.16 Setting of serial I/O transmission data [Output of serial data] 7630 Group User’s Manual 2-77 APPLICATION 2.5 Serial I/O Control procedure : When the registers are set as shown in Figure 2.5.15, the Serial I/O transmits 1-byte data simply by writing data to the Serial I/O shift register. Thus, after setting the CS signal to “L”, write the transmission data to the Serial I/O shift register on 1-byte base, and return the CS signal to “H” when the desired number of bytes have been transmitted. Figure 2.5.17 shows a control procedure of serial I/O(clock synchronous serial I/O). RESET Initialization SIOCON [Address: 001316] ICONC [Address: 000716], bit 4 P3 [Address: 000E16], bit 3 P3D [Address: 000F16] X10010112 0 1 XXXX1XXX2 X : These bits are not used in this application. Please set these bits to “0” or “1” appropriately. • Set the Serial I/O control register. • Set the Interrupt control register C. • Set the CS signal output port (“H” level output). P3 [Address: 000E16], bit 3 0 • Set the CS signal output level to “L”. IREQC [Address: 000416], bit 4 0 • Set the Serial I/O interrupt request bit to “0”. SIO [Address: 001216] Transmission data • Write transmit data (start to transmit 1-byte data). IREQC [Address: 000416], bit 4? 1 N 0 • Check the completion of 1-byte data transmission. Complete to transmit data? Y P3 [Address: 000E16], bit 3 1 • Use any a counter to count the number of transmitted bytes. • Check whether the transmission of the target bytes has been completed. • Return the CS signal output level to “H” when transmission of the target bytes has been completed. Fig. 2.5.17 Control procedure of clock synchronous serial I/O [Output of serial data] 2-78 7630 Group User’s Manual APPLICATION 2.5 Serial I/O (2) Communication (transmit/receive) using asynchronous serial I/O (UART) 1 Point : 1 -word data is transmitted and received through asynchronous serial I/O. Figure 2.5.18 shows a connection diagram, and Figure 2.5.19 shows a timing chart. Transmitting side UCTS TxD Receiving side URTS RxD 7630 group 7630 group Fig. 2.5.18 Connection diagram [Communication using UART] Specifications : • The Serial I/O is used (UART is selected). • Transfer bit rate : 9600 bps (f(X IN) = 10.0 MHz is divided by 1024) _________ _________ • Communication control using port URTS a nd U CTS Set to “1” • Receiving side Receive enable bit URTS UCTS (Transmitting side) Set to “1” • Transmitting side Transmit enable bit A A Transmission buffer empty flag TxD RxD (Receiving side) ST D0 D1 D2 D3 D4 D5 D6 D7 2SP ST D0 1ST-8DATA-2SP A : Write transmit data to the UART transmit buffer register 1. Fig. 2.5.19 Timing chart [Communication using UART] 7630 Group User’s Manual 2-79 APPLICATION 2.5 Serial I/O Table 2.5.1 shows setting examples of UART baud rate generator (UBRG) values and transfer bit rate values, Figure 2.5.20 shows a setting of related registers on the transmitting side, and Figure 2.5.21 shows a setting of related registers on the receiving side. Table 2.5.1 Setting examples of Baud rate generator values and transfer bit rate values Transfer bit rate BRG count source at φ = 8MHz / 2 (bps) (Note 1) (Note 2) BRG setting value Actual time (bps) 75 φ/256 12 (0C16) 75.12 150 φ/256 5 (0516) 162.76 300 φ/32 25 (1916) 300.48 600 φ/32 12 (0C16) 600.96 1200 φ/32 5 (0516) 1302.08 2400 φ/8 12 (0C16) 2403.84 4800 φ/8 5 (0516) 5208.33 9600 φ/8 2 (0216) 10416.66 19200 φ 12 (0C16) 19230.76 31250 φ 7 (0716) 31250.00 62500 φ 3 (0316) 62500.00 76800 φ 2 (0216) 83333.33 Notes 1: Equation of transfer bit rate Transfer bit rate (bps) = at φ = 10MHz / 2 BRG setting value Actual time (bps) 15 (0F16) 76.29 7 (0716) 152.58 31 (1F16) 305.17 15 (0F16) 610.35 7 (0716) 1220.70 15 (0F16) 2441.40 7 (0716) 4882.81 3 (0316) 9765.62 15 (0F16) 19531.25 9 (0916) 31250.00 4 (0416) 62500.00 3 (0316) 78125.00 φ (BRG setting value + 1) ! 1 6 ! p V Notes 2: BRG count source (φ/pV) is selected by the Clock divider selection bits (bit 1 and 2 of the UART mode register [Address: 0020 16 ]). V The Value p i s decided by the Clock divider selection bits (bit 1 and 2 of the UART mode register [Address: 0020 16]). Refer to Table 2.5.2. Table 2.5.2 Clock divider selection for serial I/O Clock divider selection bits Clock divider p bit 2 bit 1 1 0 0 8 0 1 32 1 0 256 1 1 2-80 7630 Group User’s Manual APPLICATION 2.5 Serial I/O • Transmitting side CPU mode register [Address: 000016] b7 b0 CPUM 0 Internal system clock selection bit : φ = f(XIN) divided by 2 (high-speed mode) UART mode register [Address: 002016] b7 b0 UMOD 010 101 Clock divider selection bits : φ divided by 8 Stop bits selection bit : Two stop bits Parity enable bit : Parity disabled Word length selection bits : 8 bits UART control register [Address: 002216] b7 b0 UCON 0100 Transmit enable bit : Transmit disabled (Set this bit to “1” at starting communication.) Receive enable bit : Receive disabled Transmission initialization bit : Initialize the transmit enable bit and transmit status register flags. Receive initialization bit : No action UART baud rate generator [Address: 002116] b7 b0 UBRG 3 Set φ –1 Transfer bit rate ! 16 ! pV V The value p is decided by the Clock divider selection bits (bit 1 and bit 2 of the UART mode register [address: 002016]). Refer to Table 2.5.2. UART status register [Address: 002316] b7 b0 USTS Transmission register empty flag : This flag is set to “1” at transmit shift completed. Check a completion of transmitting 1-word data with this flag. Transmission buffer empty flag : This flag is set to “1” at transfer data from the Transmit buffer register to the Transmit shift register. Check whether the next transmission data is writable to the Transmit buffer register with this flag. Fig. 2.5.20 Setting of related registers on transmitting side [Communication using UART] 7630 Group User’s Manual 2-81 APPLICATION 2.5 Serial I/O • Receiving side CPU mode register [Address: 000016] b7 b0 CPUM 0 Internal system clock selection bit : φ = f(XIN) divided by 2 (high-speed mode) UART mode register [Address: 002016] b7 b0 UMOD 010 101 Clock divider selection bits : φ divided by 8 Stop bits selection bit : Two stop bits Parity enable bit : Parity checking disabled Word length selection bits : 8 bits UART control register [Address: 002216] b7 b0 UCON 1000 Transmit enable bit : Transmit disabled Receive enable bit : Receive disabled (Set this bit to “1” at starting communication.) Transmission initialization bit : No action Receive initialization bit : Initialize the receive eneble bit and receive status register flags. UART baud rate generator [Address: 002116] b7 b0 UBRG 3 Set φ –1 Transfer bit rate ! 16 ! pV V The value p is decided by the Clock divider selection bits (bit 1 and bit 2 of the UART mode register [address: 002016]). Refer to Table 2.5.2. UART status register [Address: 002316] b7 b0 USTS Receive buffer full flag : This flag is set to “1” at receive completed. Check whether the receive data is readable out from the Receive buffer register with this flag. Receive framing error flag : This flag is set to “1” at framing error detected. Receive overrun flag : This flag is set to “1” at overrun detected. Receive error sum flag : This flag is set to “1” at some error detected. Fig. 2.5.21 Setting of related registers on receiving side [Communication using UART] 2-82 7630 Group User’s Manual APPLICATION 2.5 Serial I/O Control procedure : Figure 2.5.22 shows a control procedure on the transmitting side, and Figure 2.5.23 shows a control procedure on the receiving side. • Transmitting side RESET Initialization CPUM [Address: 000016] UMOD [Address: 002016] UCON [Address: 002216] UBRG [Address: 002116] 00000X002 010X101X2 XXXX01002 4–1 • φ = f(XIN) divided by 2 (high-speed mode) • Transfer data format : 1ST-8DATA-2SP • Transmit initialization The Transmit enable bit is cleared to “0”. The Transmission register empty flag is set to “1”. The Transmission buffer empty flag is set to “1”. X : These bits are not used in this application. Please set these bits to “0” or “1” appropriately. UCON [Address: 002216], bit 0 1 • Transmit enable (Start of communication) UTBR1 [Address: 002416] The first byte of transmission data • Write the first byte of transmission data to the Transmit buffer register. The Transmit buffer empty flag is cleared to “0” by this writing. When the UCTS input level is “L”, start transmission (Note). 0 • Check whether the data has been transferred from the Transmit buffer register to the Transmit shift register with the Transmit buffer empty flag. USTS [Address: 002316], bit 1? 1 UTBR1 [Address: 002416] The second byte of transmission data • Write the second byte of transmission data to the Transmit buffer register. The Transmit shift register shift completion flag is clear to “0” by this writing. When the UCTS input level is “L”, start transmission (Note). • Check the shift completion of the Transmit shift register with the Transmit shift register shift completion flag. USTS [Address: 002316], bit 0? 1 UCON [Address: 002216], bit 2 0 0 • Transmit initialization (End of communication) The Transmit enable bit is cleared to “0”. The Transmission register empty flag is set to “1”. The Transmission buffer empty flag is set to “1”. Note: Controlled by the serial I/O logic. Fig. 2.5.22 Control procedure on transmitting side [Communication using UART] 7630 Group User’s Manual 2-83 APPLICATION 2.5 Serial I/O • Receiving side RESET Initialization CPUM [Address: 000016] UMOD [Address: 002016] UCON [Address: 002216] UBRG [Address: 002116] 00000X002 010X101X2 XXXX10002 4–1 • φ = f(XIN) divided by 2 (high-speed mode) • Transfer data format : 1ST-8DATA-2SP • Receive initialization The Receive enable bit is cleared to “0”. The Receive buffer full flag is set to “1”. The Receive parity error flag is cleared to “0”. The Receive framing error flag is cleared to “0”. The Receive overrun flag is cleared to “0”. The Receive error sum flag is cleared to “0”. • Receive enable (Start of communication) Output “L” from URTS. X : These bits are not used in this application. Please set these bits to “0” or “1” appropriately. UCON [Address: 002216], bit 1 1 USTS [Address: 002316], bit 2? 1 Read the received data from URBR1 [Address: 002616] 0 • Check the completion of receiving with the Receive buffer full flag. • Read the first byte of received data. The receive buffer full flag is cleared to “0” by reading data. USTS [Address: 002316], bit 6? 1 • Check the Receive error sum flag. 0 USTS [Address: 002316], bit 2? 1 Read the received data from URBR1 [Address: 002616] 0 • Check the completion of receiving with the Receive buffer full flag. • Read the second byte of received data. The receive buffer full flag is cleared to “0” by reading data. USTS [Address: 002316], bit 6? 0 1 • Check the Receive error sum flag. Processing for error UCON [Address: 002216], bit 3 1 • Receive initialization (End of communication) The Receive enable bit is cleared to “0”. The Receive buffer full flag is set to “1”. The Receive parity error flag is cleared to “0”. The Receive framing error flag is cleared to “0”. The Receive overrun flag is cleared to “0”. The Receive error sum flag is cleared to “0”. Fig. 2.5.23 Control procedure on receiving side [Communication using UART] 2-84 7630 Group User’s Manual APPLICATION 2.5 Serial I/O (3) Communication (transmit/receive) using asynchronous serial I/O (UART) 2 Point : 9 -bit data is transmitted and received through asynchronous serial I/O. Figure 2.5.24 shows a connection diagram, and Figure 2.5.25 shows a timing chart. Transmitting side UCTS TxD Receiving side URTS RxD 7630 group 7630 group Fig. 2.5.24 Connection diagram [Communication using UART] Specifications : • The Serial I/O is used (UART is selected). • Transfer bit rate : 9600 bps (f(X IN) = 10.0 MHz is divided by 1024) _________ _________ • Communication control using port URTS a nd U CTS Set to “1” Initialize to “0” • Receiving side Receive enable bit URTS UCTS (Transmitting side) Set to “1” Initialize to “0” • Transmitting side Transmit enable bit A Transmission register empty flag TxD RxD (Receiving side) ST D0 D1 D2 D3 D4 D5 D6 D7 D8 2SP 1ST-9DATA-2SP A : 9 bits data written to the UART transmit buffer registers is transferred to the Transfer shift register. Fig. 2.5.25 Timing chart [Communication using UART] 7630 Group User’s Manual 2-85 APPLICATION 2.5 Serial I/O Figure 2.5.26 shows a setting of related registers at a transmitting side, and Figure 2.5.27 shows a setting of related registers at a receiving side. • Transmitting side CPU mode register [Address: 000016] b7 b0 CPUM 0 Internal system clock selection bit : φ = f(XIN) divided by 2 (high-speed mode) UART mode register [Address: 002016] b7 b0 UMOD 100 101 Clock divider selection bits : φ divided by 8 Stop bits selection bit : Two stop bits Parity enable bit : Parity disabled Word length selection bits : 9 bits UART control register [Address: 002216] b7 b0 UCON 0100 Transmit enable bit : Transmit disabled (Set this bit to “1” at starting communication.) Receive enable bit : Receive disabled Transmission initialization bit : Initialize the transmit enable bit and transmit status register flags. Receive initialization bit : No action UART baud rate generator [Address: 002116] b7 b0 UBRG 3 Set φ –1 Transfer bit rate ! 16 ! pV V The value p is decided by the Clock divider selection bits (bit 1 and bit 2 of the UART mode register [address: 002016]). Refer to Table 2.5.2. UART status register [Address: 002316] b7 b0 USTS Transmission register empty flag : This flag is set to “1” at transmit shift completed. Check a completion of transmitting 1-word data with this flag. Transmission buffer empty flag : This flag is set to “1” at transfer data from the Transmit buffer register to the Transmit shift register. Fig. 2.5.26 Setting of related registers on transmitting side [Communication using UART] 2-86 7630 Group User’s Manual APPLICATION 2.5 Serial I/O • Receiving side CPU mode register [Address: 000016] b7 b0 CPUM 0 Internal system clock selection bit : φ = f(XIN) divided by 2 (high-speed mode) UART mode register [Address: 002016] b7 b0 UMOD 100 101 Clock divider selection bits : φ divided by 8 Stop bits selection bit : Two stop bits Parity enable bit : Parity checking disabled Word length selection bits : 9 bits UART control register [Address: 002216] b7 b0 UCON 1000 Transmit enable bit : Transmit disabled Receive enable bit : Receive disabled (Set this bit to “1” at starting communication.) Transmission initialization bit : No action Receive initialization bit : Initialize the receive eneble bit and receive status register flags. UART baud rate generator [Address: 002116] b7 b0 UBRG 3 Set φ –1 Transfer bit rate ! 16 ! pV V The value p is decided by the Clock divider selection bits (bit 1 and bit 2 of the UART mode register [address: 002016]). Refer to Table 2.5.2. UART status register [Address: 002316] b7 b0 USTS Receive buffer full flag : This flag is set to “1” at receive completed. Check whether the receive data is readable out from the Receive buffer register with this flag. Receive framing error flag : This flag is set to “1” at framing error detected. Receive overrun flag : This flag is set to “1” at overrun detected. Receive error sum flag : This flag is set to “1” at some error detected. Fig. 2.5.27 Setting of related registers on receiving side [Communication using UART] 7630 Group User’s Manual 2-87 APPLICATION 2.5 Serial I/O Control procedure : Figure 2.5.28 shows a control procedure on the transmitting side, and Figure 2.5.29 shows a control procedure on the receiving side. • Transmitting side RESET Initialization CPUM [Address: 000016] UMOD [Address: 002016] UCON [Address: 002216] UBRG [Address: 002116] 00000X002 100X101X2 XXXX01002 4–1 • φ = f(XIN) divided by 2 (high-speed mode) • Transfer data format : 1ST-9DATA-2SP • Transmit initialization The Transmit enable bit is cleared to “0”. The Transmission register empty flag is set to “1”. The Transmission buffer empty flag is set to “1”. X : These bits are not used in this application. Please set these bits to “0” or “1” appropriately. UCON [Address: 002216], bit 0 1 • Transmit enable (Start of communication) UTBR1 [Address: 002416] UTBR2 [Address: 002516], bit 0 Transmission data (9 bits) • Write 9 bits of transmission data to the Transmit buffer register. The Transmit shift register shift completion flag is cleared to “0” by this writing. When the UCTS input level is “L”, start transmission (Note). 0 • Check the shift completion of the Transmit shift register with the Transmit shift register shift completion flag. USTS [Address: 002316], bit 0? 1 UCON [Address: 002216], bit 2 0 • Transmit initialization (End of communication) The Transmit enable bit is cleared to “0”. The Transmission register empty flag is set to “1”. The Transmission buffer empty flag is set to “1”. Note: Controlled by the serial I/O logic. Fig. 2.5.28 Control procedure on transmitting side [Communication using UART] 2-88 7630 Group User’s Manual APPLICATION 2.5 Serial I/O • Receiving side RESET Initialization CPUM [Address: 000016] UMOD [Address: 002016] UCON [Address: 002216] UBRG [Address: 002116] 00000X002 100X101X2 XXXX10002 4–1 • φ = f(XIN) divided by 2 (high-speed mode) • Transfer data format : 1ST-9DATA-2SP • Receive initialization The Receive enable bit is cleared to “0”. The Receive buffer full flag is set to “1”. The Receive parity error flag is cleared to “0”. The Receive framing error flag is cleared to “0”. The Receive overrun flag is cleared to “0”. The Receive error sum flag is cleared to “0”. • Receive enable (Start of communication) Output “L” from URTS. X : These bits are not used in this application. Please set these bits to “0” or “1” appropriately. UCON [Address: 002216], bit 1 1 USTS [Address: 002316], bit 2? 1 Read the received data from URBR1 [Address: 002616] and URBR2 [Address: 002716] 0 • Check the completion of receiving with the Receive buffer full flag. • Read the received 9 bits data. The receive buffer full flag is cleared to “0” by reading data. USTS [Address: 002316], bit 6? 0 1 • Check the Receive error sum flag. Processing for error UCON [Address: 002216], bit 3 1 • Receive initialization (End of communication) The Receive enable bit is cleared to “0”. The Receive buffer full flag is set to “1”. The Receive parity error flag is cleared to “0”. The Receive framing error flag is cleared to “0”. The Receive overrun flag is cleared to “0”. The Receive error sum flag is cleared to “0”. Fig. 2.5.29 Control procedure on receiving side [Communication using UART] 7630 Group User’s Manual 2-89 APPLICATION 2.6 A-D converter 2.6 A-D converter 2.6.1 Memory map of A-D conversion 001416 001516 A-D conversion register (AD) A-D control register (ADCON) Fig. 2.6.1 Memory map of A-D conversion related registers 2-90 7630 Group User’s Manual APPLICATION 2.6 A-D converter 2.6.2 Related registers A-D conversion register b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion register (AD) [Address : 001416] B 0 1 2 3 4 5 6 7 Function The read only register where A-D conversion results are stored. At reset R W ? ? ? ? ? ? ? ? Fig. 2.6.2 Structure of A-D conversion register A-D control register b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (ADCON) [Address : 001516] B 0 1 Name Analog input pin selection bits b2 b1 b0 Function 0 0 0 : P00/AN0 0 0 1 : P01/AN1 0 1 0 : P02/AN2 0 1 1 : P03/AN3 1 0 0 : P04/AN4 1 0 1 : P05/AN5 1 1 0 : P06/AN6 1 1 1 : P07/AN7 0 : Conversion in progress 1 : Conversion completed (Note) 0 : Off 1 : On At reset R W 0 0 2 3 A-D conversion completion bit 4 VREF input switch bit 0 1 0 0 0 0 5 Not used (“0” when read, don't write “1”.) 6 7 Note: Don’t set this bit to “1” during A-D conversion. Fig. 2.6.3 Structure of A-D control register 7630 Group User’s Manual 2-91 APPLICATION 2.6 A-D converter 2.6.3 A-D conversion application example [Measurement of analog signals] Outline : A s ensor's analog output voltage is converted to digital values. Figure 2.6.4 shows a connection related registers. P01/AN1 Sensor Reference voltage VREF AVSS VSS 7630 group Fig. 2.6.4 Connection diagram [Measurement of analog signals] Specifications : • The analog input voltage injected from the sensor is converted into digital values (Note ). • The P01 /AN1 p in is used as an analog input pin. Note: [Example] When a reference voltage, 5.12 V is input to the VREF pin and a voltage, 4 V to the P01 /AN1 pin, the input voltage is converted to following value. (256 / 5.12 V) ! 4 V = 2 00 (C816) Figure 2.6.5 shows a setting of related registers. Port P0 direction register [Address: 000916] b7 b0 P0D 0 P01/AN1 pin : Input mode (used as the analog input pin) A-D control register [Address: 001516] b7 b0 ADCON 11001 Analog input pin selection bits : The P01/AN1 pin A-D conversion completion bit : Conversion completed Clear to “0” to start A-D conversion. Don't set this bit to “1” during A-D conversion. VREF input switch bit : On A-D conversion register [Address: 001416] b7 b0 AD The result of A-D conversion stored This register is read-only. Read the result of A-D conversion after the A-D conversion completion bit is set to “1”. This bit is cleared to “0” at this reading. Fig. 2.6.5 Setting of related registers [Measurement of analog signals] 2-92 7630 Group User’s Manual APPLICATION 2.6 A-D converter Control procedure : By setting the related registers as shown in Figure 2.6.6, the analog voltage input from the sensor are converted into digital values. X : These bits are not used in this application. Please set these bits to “0” or “1” appropriately. ADCON [Address: 001516] P0D [Address: 000916] ADCON [Address: 001516], bit 3 XXX110012 XXXXXX0X2 0 • Select the P01/AN1 pin as an analog input pin. • P01/AN1 pin : Input mode • Start A-D conversion. ADCON [Address: 001516], bit 3? 0 • Check the completion of A-D conversion with the A-D conversion completion bit. 1 Read out AD [Address: 001416] • Read out the conversion result. The A-D conversion completion bit is cleared to “0” at this reading. Fig. 2.6.6 Control procedure [Measurement of analog signals] 2.6.4 Conversion time On A-D conversion process takes 53 to 54 cycles of the internal system clock φ. 2.6.5 Notes on use (1) Analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01µF to 1µF. Further, be sure to verify the operation of application products on the user side. Reason An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. This may cause the A-D conversion precision to be worse. (2) Reference voltage input pin (VREF ) Apply a voltage of 2V to VCC to the reference voltage input pin VREF during A-D conversion. Note that if the reference voltage is lowered below the above value, the A-D conversion precision will be degraded. (3) Oscillation frequency during A-D conversion The comparator is configured by capacity coupling, so the charge is lost if the clock input oscillation frequency is low. Set f(XIN ) at 500kHz or more during A-D conversion. (4) Set the analog input pin to input mode Clear the bit of the Port P0 direction register [Address: 000916 ] which correponds to the used analog input pin to “0” (input mode). 7630 Group User’s Manual 2-93 APPLICATION 2.7 Watchdog timer 2.7 Watchdog timer The watchdog timer can detect a runaway program using either 7-bit or 11-bit timer prescaler. 2.7.1 Related register Watchdog timer register (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer register (WDT) [Address : 002E16] Name B 0 Not used (“1” when read.) 1 2 3 4 5 Stop instruction disable bit 6 0 : Stop instruction enabled 1 : Stop instruction disabled Executed two NOP instructions instead of STP instruction (Note 2) Function At reset R W 1 1 1 1 1 1 0 7 Upper byte count source selection 0 : Underflow of the low order counter bit 1 : φ divided by 256 0 Note 1: Writing to this register reloads the watchdog timer counters with the following initial values irrespective of the value written. After reload, the watchdog timer counts down. • The high-order counter WDH (7-bit counter) is set to “7F16”. • The low-order counter WDL (4-bit counter) is set to “F16”. The time-out period of the watchdog timer is nV cycles of the internal system clock φ . V • n = 524288 when the Upper byte count source selection bit is “0”. • n = 32768 when the Upper byte count source selection bit is “1”. On a watchdog timer underflow, the watchdog timer interrupt (non-maskable) occurs. Set the watchdog timer counters to the default values prevent from underflow by writing to this register in main processing. Once the watchdog timer has been started, it cannot be stopped except by reset. Note 2: Once the Stop instruction is disabled, it cannot be enabled again except by reset. Fig. 2.7.1 Structure of Watchdog timer register 2-94 7630 Group User’s Manual APPLICATION 2.7 Watchdog timer 2.7.2 Watchdog timer cycle The watchdog timer cycle varies depending on the internal clock φ and the frequency division ratio of the prescaler selected. Table 2.7.1 shows the watchdog timer cycle. Table 2.7.1 Watchdog timer cycle Internal clock selection bit f(XIN) (bit 6 of CPU mode register[address: 000016]) 0 ( φ = f (X IN)/2 = 5 MHz) 10 MHz 1 (φ = f (X IN)/8 = 1.25 MHz) 0 ( φ = f (X IN)/2 = 4 MHz) 8 MHz 1 ( φ = f (X IN)/8 = 1 MHz) Upper byte count source selection bit (bit 7 of Watchdog timer register[address: 002E16]) 0 1 0 1 0 1 0 1 Period Approx. Approx. Approx. Approx. Approx. Approx. Approx. Approx. 104.9 6.6 419.4 26.2 131.1 8.2 524.3 32.8 ms ms ms ms ms ms ms ms 2.7.3 Watchdog timer procedure Figure 2.7.2 shows the set-up procedure of watchdog timer. RESET Initialization CPUM [Address: 000016] WDT [Address: 002E16] 00000X002 X0XXXXXX2 X : These bits are not used in this application. Please set these bits to “0” or “1” appropriately. • φ = f(XIN) divided by 2 (high-speed mode) • The watchdog timer starts counting down. Main processing WDT [Address: 002E16] X0XXXXXX2 • The watchdog timer counters are set to the initial values by this writing: WDH is set to “7F16”. WDL is set to “F16”. Watchdog timer interrupt processing routine • If a microcomputer runs away because of noise or others, the watchdog timer is not initialized, and underflows. Then the watchdog timer occurs, reset the software. Software reset Fig. 2.7.2 Set-up procedure of watchdog timer 7630 Group User’s Manual 2-95 APPLICATION 2.8 Reset 2.8 Reset Figure 2.8.1 shows an example of power on reset circuit. VCC 1 Power source M51953AL GND 3 5 Output 4 Delay capacity RESET 0.1 µF VSS 7630 group Fig. 2.8.1 Example of Power on reset circuit Figure 2.8.2 shows system example which switch the microcomputer to the RAM backup mode by detecting a drop of the system power source voltage with the INT interrupt. System power source voltage +5V VCC + 7 VCC1 M51953AL 2 1 RESET VCC2 V1 GND 4 5 3 6 RESET INT Cd VSS 7630 group Fig. 2.8.2 RAM back-up system 2-96 7630 Group User’s Manual APPLICATION 2.9 Oscillation circuit 2.9 Oscillation Circuit 2.9.1 Memory map of oscillation circuit related registers 000016 002E16 CPU mode register (CPUM) Watchdog timer register (WDT) Fig. 2.9.1 Memory map of oscillation circuit related registers 7630 Group User’s Manual 2-97 APPLICATION 2.9 Oscillation circuit 2.9.2 Related registers CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) [Address : 000016] B 0 1 2 Stack page selection bit Name Processor mode bits b1 b0 Function 0 0 : Single chip mode 0 1 : Not available 1 0 : Not available 1 1 : Not available 0 : In page 0 1 : In page 1 At reset R W 0 0 1 0 0 0 1 0 3 Not used (“0” when read, don't write “1”.) 4 5 6 Internal clock selection bit 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode) 7 Not used (“0” when read, don't write “1”.) Fig. 2.9.2 Structure of CPU mode register Watchdog timer register (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer register (WDT) [Address : 002E16] B Name 0 Not used (“1” when read.) 1 2 3 4 5 Stop instruction disable bit 6 0 : Stop instruction enabled 1 : Stop instruction disabled Executed two NOP instructions instead of STP instruction (Note 2) Function At reset R W 1 1 1 1 1 1 0 7 Upper byte count source selection 0 : Underflow of the low order counter bit 1 : φ divided by 256 0 Note 1: Writing to this register reloads the watchdog timer counters with the following initial values irrespective of the value written. After reload, the watchdog timer counts down. • The high-order counter WDH (7-bit counter) is set to “7F16”. • The low-order counter WDL (4-bit counter) is set to “F16”. The time-out period of the watchdog timer is nV cycles of the internal system clock φ . V • n = 524288 when the Upper byte count source selection bit is “0”. • n = 32768 when the Upper byte count source selection bit is “1”. On a watchdog timer underflow, the watchdog timer interrupt (non-maskable) occurs. Set the watchdog timer counters to the default values prevent from underflow by writing to this register in main processing. Once the watchdog timer has been started, it cannot be stopped except by reset. Note 2: Once the Stop instruction is disabled, it cannot be enabled again except by reset. Fig. 2.9.3 Structure of Watchdog timer register 2-98 7630 Group User’s Manual APPLICATION 2.9 Oscillation circuit 2.9.3 Application examples A s examples of application, switching procedures to Stop and Wait modes are shown below. (1) Ordinary mode → S top mode (2) Ordinary mode → W ait mode (1) Switing procedure from Ordinary mode to Stop mode Figure 2.9.4 shows the switching procedure to Stop mode. Step 1: Set the Timer 1 interrupt and Timer 2 interrupt for stabilizing oscillation. Set to the Timer 1 interrupt and Timer 2 interrupt disabled. b7 b0 00 Interrupt control register B (ICONB) [Address: 000616] Timer 1 interrupt enable bit: Interrupt disabled Timer 2 interrupt enable bit: Interrupt disabled Set the the Timer 1 and Timer 2. b7 b0 FF16 Timer 1 (T1) [Address: 001616] Set the count data (Note 1). b7 b0 FF16 Timer 2 (T2) [Address: 001716] Set the count data (Note 1). Note 1: Set enough count data for stabilizing oscillation. For the oscillation stabilizing time, ask the oscillator maker for information. Step 2: Set the external interrupt source used for return from the stop mode (Note 2). Note 2: Refer to “2.2 Interrupt”. Step 3: Execute the STP instruction to switch procedure to the stop mode. Fig. 2.9.4 Switching procedure to Stop mode (2) Switching procedure from Ordinary mode to Wait mode Figure 2.9.5 shows the switching procedure to Wait mode. Step 1: Set the interrupt source used for return from the wait mode (Note). Note: Refer to “2.2 Interrupt”. Step 2: Execute the WIT instruction to switch procedure to the wait mode. Fig. 2.9.5 Switching procedure to Wait mode 7630 Group User’s Manual 2-99 APPLICATION 2.10 Development support tools 2.10 Development support tools (M37630T-RFS) The M37630T-RFS is a conversion board to use M37630E4FS as emulator MCU. When an emulator is connected to the socket on the top surface, user program debugging can be performed efficiently by using a real-time trace function, etc. Since address bus signals, data bus signals, SYNC, RD, WR and f signals are output from the socket, emulator can monitor all bus information in the microcomputer. For details of development support systems for the M37630T-RFS, refer to the “DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTER” data book. Figure 2.10.1 shows an example of configuration example of using M37630T-RFS. M37630E4FS M38000T-FPD or M38000TL-FPD or M38000TL2-FPD Emulation Pod Probe M37630T-RFS PCA4628B ei d . V TQSOCKET044SAF V TQSOCKET044SAG V TQPACK044SA Soldering Foot pattern(44P6N-A) No.1 pin of MCU User’s target V TQSOCKET044SAF, TQSOCKET044SAG and TQPACK044SA are the products made by Tokyo Eletec Co. Ltd. Fig. 2.10.1 Configuration example of using M37630T-RFS 3-100 7630 Group User’s Manual APPLICATION 2.11 Built-in PROM version 2.11 Built-in PROM version In contrast with the mask ROM version, a microcomputer incorporating a programmable ROM is called built-in PROM version. There are two types of built-in PROM version as shown below. q One Time PROM version Writing to the built-in PROM can be performed only once. Neither erase nor rewrite operation is enabled. q Built-in EPROM version The built-in EPROM version is a programmable microcomputer with a window and can perform write, erase, and rewrite operations. The built-in PROM version has the EPROM mode for writing to the built-in PROM in addition to the same functions as those of the mask ROM version. For an outline of performance and a functional block diagram of the built-in PROM version, refer to “ 1. Hardware”. 2.11.1 Product expansion T he 7630 group supports the built-in PROM versions shown in Table 2.11.1. Table 2.11.1 7630 group’s built-in PROM version supporting products Product name M37630E4T-XXXFP M37630E4FP M37630E4FS (P)ROM size (bytes) 16252 RAM size (bytes) 512 I/O Ports I/O ports: 35 Input ports: 1 Package 44P6N-A 80D0 Remarks One Time PROM version One Time PROM version (blank) EPROM version 7630 Group User’s Manual 2-101 APPLICATION 2.11 Built-in PROM version 2.11.2 Pin configuration The pin configurations of the built-in PROM versions are shown in Figure 2.11.1. PIN CONFIGURATION (TOP VIEW) P16/PWM P15/CNTR1 P14/CNTR0 P13/TX0 P12/INT1 P11/INT0 P07/AN7 P06/AN6 P05/AN5 P04/AN4 P03/AN3 33 31 30 27 24 32 29 28 26 25 23 P17 P20/SIN1 P21/SOUT1 P22/SCLK1 P23/SRDY1 VSS P24/URXD P25/UTXD P26/URTS P27/UCTS P30 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 M37630E4T-XXXFP 17 16 15 14 13 12 P02/AN2 P01/AN1 P00/AN0 VREF AVSS VCC XOUT XIN VSS RESET P47/KW7 10 53 54 60 59 55 61 56 57 58 62 63 64 P17 P20/SIN1 P21/SOUT1 P22/SCLK1 P23/SRDY1 reserved reserved VSS reserved reserved reserved P24/URXD P25/UTXD P26/URTS P27/UCTS P30 52 51 50 49 48 47 46 45 44 43 42 41 NC NC reserved reserved P16/PWM P15/CNTR1 P14/CNTR0 P13/TX0 P12/INT1 P11/INT0 reserved reserved reserved reserved P07/AN7 P06/AN6 P05/AN5 P04/AN4 P03/AN3 reserved reserved NC NC NC P31/CTX P32/CRX P33 P34 P40/KW0 P41/KW1 P42/KW2 P43/KW3 P44/KW4 P45/KW5 P46/KW6 Package type 44P6N-A 11 4 1 2 5 7 3 6 8 9 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 M37630E4FS reserved P02/AN2 P01/AN1 P00/AN0 reserved reserved VREF AVSS VCC XOUT XIN VSS RESET reserved reserved P47/KW7 11 12 13 14 15 16 17 18 19 20 NC NC reserved reserved P31/CTX P32/CRX P33 P34 reserved reserved reserved reserved P40/KW0 P41/KW1 P42/KW2 P43/KW3 P44/KW4 P45/KW5 P46/KW6 reserved reserved NC NC NC Package type 80D0 10 21 22 23 24 1 2 3 4 5 6 7 8 9 NC: No Connection Fig. 2.11.1 Pin configuration of 7630 group’s built-in PROM versions 2-102 7 630 Group User’s Manual APPLICATION 2.11 Built-in PROM version 2.11.3 Programming adapter To write or read data into/from the internal PROM, use the dedicated programming adapter and generalpurpose PROM programmer as shown in Table 2.11.2. Table 2.11.2 Programming adapter Microcomputer M37630E4FS M37630E4FP (one-time blank) Programming adapter PCA7431 PCA7430 (1) Write and read In PROM mode, operation is the same as that of the M5M27C101, but programming conditions of PROM programmer are not set automatically because there are no internal device ID codes. Accurately set the following conditions for data write/read. Take care not to apply 21 V to VPP p in, or the product may be permanently damaged. q P rogramming voltage : 12.5 V q S etting of programming adapter switch : Refer to Table 2.11.3. q S etting of PROM programmer address : Refer to Table 2.11.4. Table 2.11.3 Setting of programming adapter switch Programming adapter PCA7431, PCA7430 SW 1 CMOS SW 2 CMOS Table 2.11.4 Setting of PROM programmer address Microcomputer PROM programmer start address M37630E4FS M37630E4FP Address : C080 16 PROM programmer completion address Address : FFFB 16 (2) Erasing Contents of the windowed EPROM are erased through an ultraviolet light source of the wavelength 2537 Angstrom. At least 15 W-sec/cm are required to erase EPROM contents. 7630 Group User’s Manual 2-103 APPLICATION 2.11 Built-in PROM version 2.11.4 Notes on use The notes on using the built-in PROM version are shown below. (1) All built-in PROM version products s Precautions at write operation q Be careful not to apply an overvoltage to pins because a high voltage is used for a write operation. Exercise special care when turning on the power supply. q For writing the contents of the PROM, use a dedicated programming adapter. This permits using a general-purpose PROM programmer for writing data. For details of dedicated programming adapters, refer to “ 2.11.3 Programming adapter ”. s Precautions at read operation q When reading the contents of the PROM, use a dedicated programming adapter, so that reading can be performed by a general-purpose PROM programmer. For details of dedicated programming adapters, refer to “ 2.11.3 Programming adapter ”. (2) One Time PROM version s Precautions before use q The PROM of the One Time PROM version is not tested or screened in the assembly process and the following processes. To ensure proper operation after programming, the procedure shown in Figure 2.11.2 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (Leave at 150°C for 40 hours) Verification with PROM programmer Functional check in target device Caution: The screening temperature is far higher than the storage temperature. Never expose to 150°C exceeding 100 hours. Fig. 2.11.2 Programming and testing of One Time PROM version 2-104 7 630 Group User’s Manual APPLICATION 2.11 Built-in PROM version (3) Built-in EPROM version s Precautions on erasing q Sunlight and fluorescent light include light that may erase the information written in the built-in PROM. When using the built-in EPROM version in the read mode, be sure to cover the transparent glass portion with a seal. q This seal to cover the transparent glass portion is prepared on our side. Be careful that the seal does not touch the microcomputer lead wires when covering the glass portion with the seal because this seal is made of metal (aluminum). q Before erasing data, clean the transparent glass. If any finger stain or seal adhesive is stuck to the transparent glass, this prevents ultraviolet rays’ passing, thereby affecting the erase characteristic adversely. s Precautions on mounting q M37630E4FS(Package type 80D0) has the "reserved" pins. It uses those pins at emulator MCU mode. Please open these pins described in “ 2.11.2 Pin configuration” as “reserved”. 7630 Group User’s Manual 2-105 CHAPTER 3 APPENDIX 3.1 Electrical characteristics 3.2 Standard characteristics 3.3 Notes on use 3.4 Countermeasures against noise 3.5 List of registers 3.6 Mask ROM ordering method 3.7 Mark specification form 3.8 Package outline 3.9 List of instruction codes 3.10 Machine instructions 3.11 SFR memory map 3.12 Pin configuration APPENDIX 3.1 Electrical characteristics 3.1 Electrical characteristics 3.1.1 Absolute maximum ratings Table 3.1.1 Absolute maximum ratings Symbol VCC VI VO Pd Topr Tstg Parameter Power source voltage Input voltag Output voltage Power dissipation Operating temperature Storage temperature P00–P07, P11–P17, P20–P27, ____________ P30–P34, P40–P47, RESET, XIN P00–P07, P12–P17, P20–P27, P30–P34, P40–P47, XOUT Conditions All voltages with respect to VSS and output transistors are “off”. Ta = 25°C Ratings –0.3 to 7.0 –0.3 to VCC+0.3 –0.3 to VCC+0.3 500 –40 to 85 –60 to 150 Unit V V V mW °C °C 3-2 7630 Group User’s Manual APPENDIX 3.1 Electrical characteristics 3.1.2 Recommended operating conditions Table 3.1.2 Recommended operating conditions (Vcc = 4.0V to 5.5V, V SS = A V SS = 0 V, Ta = –40 °C to 85 °C, unless otherwise noted) Symbol VCC VSS VIH VIL ∑IOH(peak) ∑IOH(avg) ∑IOL(peak) ∑IOL(avg) IOH(peak) IOH(avg) IOL(peak) IOL(avg) IIO ∑IIO f(CNTR) Power source voltage “H” input voltage “L” input voltage “H” sum peak output current “H” sum average output current “L” sum peak output current “L” sum average output current “H” peak output current “H” average output current “L” peak output current “L” average output current Input current at overvoltage condition (VI > VCC) Total input current at overvoltage condition (VI > VCC) Timer input frequency (based on 50% duty) P11–P17, P20–P27, P30–P34, P40–P47 P11–P17, P20–P27, P30–P34, P40–P47 P14/CNTR0, P15/CNTR1 (except bi-phase counter mode) P13/TX0, P14/CNTR0 (bi-phase counter mode) P00–P07, P11–P17, P20–P27, ______ P30–P34, P40–P47, RESET, XIN P00–P07, P11–P17, P20–P27, ______ P30–P34, P40–P47, RESET, XIN P00–P07, P12–P17, P20–P27, P30–P34, P40–P47 Parameter Min. 4 0.8VCC 0 Limits Typ. 5 0 Max. 5.5 VCC 0.2VCC –80 –40 80 40 –10 –5 10 5 1 16 f(XIN)/16 f(XIN)/32 10 Unit V V V V mA mA mA mA mA mA mA mA mA mA MHz MHz MHz f(XIN) Clock input oscillation frequency 7630 Group User’s Manual 3-3 APPENDIX 3.1 Electrical characteristics 3.1.3 Electrical characteristics Table 3.1.3 Electrical characteristics (Vcc = 4.0V to 5.5V, Vss = AVss = 0V, Ta = –40 °C to 85 °C, unless otherwise noted) Symbol VOH VOL VT+–VT– Parameter “H” output voltage P00–P07, P12–P17, P20–P27, P30–P34, P40–P47 “L” output voltage P00–P07, P12–P17, P20–P27, P30–P34, P40–P47 Hysteresis P11/INT0, P12/INT1, P13/TX0, P14/CNTR0, P15/CNTR1, P20/SIN, P22/SCLK, P26/URTS, ____________ P27/UCTS, P32/CRX, RESET “H” input current P00–P07, P11–P17, P20–P27, ____________ P30–P34, P40–P47, RESET “H” input current XIN “H” input current P32, P40–P47, “L” input current P00–P07, P11–P17, P20–P27, ____________ P30–P34, P40–P47, RESET “L” input current XIN “L” input current P00–P07,P11–P17, P20–P27,P30–P34, ____________ P40–P47,RESET RAM hold voltage Power source current Test conditions IOH = –5mA IOL = 5mA Min. 0.8 • VCC Limits Typ. Max. Unit V 2 V 0.5 V IIH IIH IIH IIL IIL IIL VI = VCC VI = VCC VI = VSS Pull–Down=“On” VI = VSS VI = VSS VI = VSS Pull–Up=“On” When clock stopped High-speed mode, f(XIN) = 8MHz, VCC = 5V, Output transistors “off”, CAN module running, ADC running High-speed mode, f(XIN) = 8MHz, VCC = 5V, Output transistors “off”, CAN module stopped, ADC running Middle-speed mode, f(XIN) = 8MHz, VCC = 5V, Output transistors “off”, CAN module running, ADC running, Middle-speed mode,wait mode, f(XIN) = 8MHz, VCC = 5V, Output transistors “off”, CAN module stopped, ADC running Stop mode,f(XIN)=0MHz, Ta = 25°C, VCC = 5V Stop mode,f(XIN)=0MHz, Ta = 85°C, VCC = 5V 4 20 5 µA µA µA µA µA 200 –5 –4 -200 2 -20 µA V VRAM ICC 11 18 mA 9 16 mA 6 11 mA 2 mA 0.1 1 µA µA 10 3-4 7630 Group User’s Manual APPENDIX 3.1 Electrical characteristics 3.1.4 A-D converter characteristics Table 3.1.4 A-D converter characteristics (Vcc = 4.0V to 5.5V, Vss = AVss = 0V, Ta = –40 °C to 85 °C, unless otherwise noted) Symbol – – tCONV VREF IREF RLADDER IIAN Resolution Absolute accuracy Conversion time Reference input voltage Reference input current Ladder resistor value Analog input current Parameter Test conditions Min. Limits Typ. ±1 High- speed mode Middle-speed mode VCC = VREF = 5.12V VI = VSS to VCC 106 424 2.0 150 35 0.5 Max. 8 ±2.5 108 432 VCC 200 5 Unit Bits LSB tc(XIN) tc(XIN) V µA kΩ µA 3.1.5 Timing requirements Table 3.1.5 Timing requirements (Vcc = 4.0V to 5.5V, Vss = AVss = 0V, Ta = –40 °C to 85 °C, unless otherwise noted) Symbol ____________ Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, input “H” pulse width CNTR0, CNTR1 input “L” pulse width CNTR0, input “L” pulse width Lag of CNTR0 and TX0 input edges TX0 input cycle time TX0 input “H” pulse width TX0 input “L” pulse width INT0, INT1 input “H” pulse width INT0, INT1 input “L” pulse width Serial I/O clock input cycle time Serial I/O clock input “H” pulse width Serial I/O clock input “L” pulse width Serial I/O clock input set up time Serial I/O clock input hold time tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tL(CNTR0–TX0) tC(TX0) tWH(TX0) tWL(TX0) tWH(INT) tWL(INT) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(SIN–SCLK) tH(SCLK–SIN) (except bi-phase counter mode) (bi-phase counter mode) (except bi-phase counter mode) (bi-phase counter mode) (except bi-phase counter mode) (bi-phase counter mode) (bi-phase counter mode) (bi-phase counter mode) (bi-phase counter mode) (bi-phase counter mode) Min. 2 100 37 37 1600 2000 800 1000 800 1000 500 3200 1600 1600 460 460 8tc(XIN) 4tc(XIN) 4tc(XIN) 200 150 Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7630 Group User’s Manual 3-5 APPENDIX 3.1 Electrical characteristics 3.1.6 Switching characteristics Table 3.1.6 Switching characteristics (Vcc = 4.0V to 5.5V, Vss = AVss = 0V, Ta = –40 °C to 85 °C, unless otherwise noted) Symbol tWH(SCLK) tWL(SCLK) tD(SCLK–SOUT) tV(SCLK–SOUT) tR(SCLK) tR(CMOS) tF(CMOS) Parameter Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time Serial I/O output valid time Serial I/O clock output rise time CMOS output rise time CMOS output fall time Test conditions Fig. 3.1.1 Min. 0.5 • tC(SCLK) – 50 0.5 • tC(SCLK) – 50 0 10 10 Limits Typ. Max. Unit ns ns ns ns ns ns ns 50 50 50 50 50 Measurement output pin 100 pF CMOS output Fig. 3.1.1 Circuit for measuring output switching characteristics 3-6 7630 Group User’s Manual APPENDIX 3.1 Electrical characteristics tC(TX0) tWH(TX0) tWL(TX0) 0.2VCC TX0 0.8VCC tC(CNTR) tWH(CNTR) tWL(CNTR) 0.2VCC CNTR0, CNTR1 0.8VCC tWH(INT) tWL(INT) 0.2VCC INT0, INT1 0.8VCC tWL(RESET) RESET 0.2VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC XIN 0.8VCC tC(SCLK) tF tWL(SCLK) 0.2VCC tR 0.8VCC tWH(SCLK) SCLK tsu(SIN–SCLK) tH(SCLK–SIN) SIN tD(SCLK–SOUT) 0.8VCC 0.2VCC tV(SCLK–SOUT) SOUT Fig. 3.1.2 Timing diagram 7630 Group User’s Manual 3-7 APPENDIX 3.2 Standard characteristics 3.2 Standard characteristics 3.2.1 Power source current standard characteristics Figure 3.2.1 to Figure 3.2.4 show the power source current standard characteristics vs. V CC and f(XIN) is both high and middle speed mode. [Measuring condition: 25°C, f(XIN) = 10MHz, in high-speed mode] 18 CAN runs, all peripherials run. 16 Power source current ICC [mA] 14 12 10 8 6 4 2 0 3.5 4 4.5 5 5.5 6 6.5 In wait mode CAN stops, all peripherials run. Power source voltage VCC [V] Fig. 3.2.1 Icc-Vcc standard characteristics (in high-speed mode) [Measuring condition: 25°C, f(XIN) = 10MHz, in middle-speed mode] 18 16 Power source current ICC [mA] 14 12 10 8 6 4 2 0 3.5 4 4.5 5 5.5 6 6.5 CAN stops, all peripherials run. In wait mode CAN runs, all peripherials run. Power source voltage VCC [V] Fig. 3.2.2 Icc-Vcc standard characteristics (in middle-speed mode) 3-8 7630 Group User’s Manual APPENDIX 3.2 Standard characteristics [Measuring condition: 25°C, VCC = VREF = 5 V, in high-speed mode] 14 CAN runs, all peripherials run. 12 10 8 6 4 In wait mode 2 0 2 4 6 8 10 12 CAN stops, all peripherials run. Power source current ICC [mA] Clock input oscillation frequency f(XIN) [MHz] Fig. 3.2.3 Power source current standard characteristics (in high-speed mode) [Measuring condition: 25°C, VCC = VREF = 5 V, in middle-speed mode] 14 12 10 8 6 4 CAN stops, all peripherials run. 2 In wait mode 0 2 4 6 8 10 12 CAN runs, all peripherials run. Power source current ICC [mA] Clock input oscillation frequency f(XIN) [MHz] Fig. 3.2.4 Power source current standard characteristics (in middle-speed mode) 7630 Group User’s Manual 3-9 APPENDIX 3.2 Standard characteristics 3.2.2 Output current standard characteristics Figures 3.2.5 and Figure 3.2.6 show the output current standard characteristics. [Port P20 IOH–VOH characteristic (P-channel drive)] (Pins with same characteristic: P0, P12–P17, P2, P30–P34, P4) –40 –35 “H” output current IOH [mA] –30 –25 VCC = 5.5V, Ta = 25°C VCC = 5.0V, Ta = 25°C –20 –15 –10 –5 0 0.0 VCC = 4.0V, Ta = 25°C 1.0 2.0 3.0 4.0 5.0 6.0 “H” output voltage VOH [V] Fig. 3.2.5 Output current standard characteristics (P-channel) [Port P20 IOL–VOL characteristic (N-channel drive)] (Pins with same characteristic: P0, P12–P17, P2, P30–P34, P4) 40 35 “L” output current IOL [mA] 30 VCC = 5.5V, Ta = 25°C 25 20 15 10 5 0 0.0 VCC = 5.0V, Ta = 25°C VCC = 4.0V, Ta = 25°C 1.0 2.0 3.0 4.0 5.0 6.0 “L” output voltage VOL [V] Fig. 3.2.6 Output current standard characteristics (N-channel) 3-10 7630 Group User’s Manual APPENDIX 3.2 Standard characteristics 3.2.3 Input current standard characteristics Figure 3.2.7 and Figure 3.2.8 show the input current standard characteristics. [Port P40 IIL characteristic (at pull-up)] (Pins with same characteristic: P0, P12–P17, P2, P30–P34, P4) –0.16 –0.14 Supply current IIL [mA] –0.12 –0.10 VCC = 5.5V, Ta = 25°C VCC = 5.0V, Ta = 25°C –0.08 –0.06 VCC = 4.0V, Ta = 25°C –0.04 –0.02 0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 Supply voltage VI [V] Fig. 3.2.7 Pull-up transistor standard characteristics IIL-V I [Port P40 IIL characteristic (at pull-down)] (Pins with same characteristic: P4) 0.16 0.14 Supply current IIL [mA] 0.12 0.10 0.08 0.06 VCC = 5.5V, Ta = 25°C VCC = 5.0V, Ta = 25°C VCC = 4.0V, Ta = 25°C 0.04 0.02 0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 Supply voltage VI [V] Fig. 3.2.8 Pull-down transistor standard characteristics IIL-V I 7630 Group User’s Manual 3-11 APPENDIX 3.2 Standard characteristics 3.2.4 A-D conversion standard characteristics Figure 3.2.9 shows the A-D conversion standard characteristics. The lower-side line on the graph indicates the absolute precision error (ERROR). It represents the deviation from the ideal value. For example, the conversion of output code from 0 to 1 occurs ideally at the point of AN0 = 1 0 mV, but the measured value is –2 mV. Accordingly, the measured point of conversion is represented as “10 – (–2) = 12 [mV]”. The upper-side line on the graph indicates the width of input voltages (1 LSB WIDTH) equivalent to output codes. For example, the measured width of the input voltage for output code 7 is 19 mV, so the differential nonlinear error is represented as “19 – 20 = –1 [mV] (–0.05 LSB)”. A-D CONVERTER STEP WIDTH MEASUREMENT VCC = 5.12 V, VREF = 5.12 V XIN = 10 MHz, Analog port P00 Temp. = 25 deg. 1LSB WIDTH 30 20 30 20 (+1LSB) 10 0 –10 –20 (–1LSB) –30 128 1LSB WIDTH [mV] ERROR [mV] 10 0 –10 –20 –30 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 Absolute precision error STEP No. 30 20 30 20 (+1LSB) 10 0 –10 –20 (–1LSB) –30 256 1LSB WIDTH [mV] ERROR [mV] 10 0 –10 –20 –30 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 STEP No. Measured when a power source voltage is stable in the single-chip mode and the high-speed mode Fig. 3.2.9 A-D conversion standard characteristics 3-12 7630 Group User’s Manual APPENDIX 3.3 Notes on use 3.3 Notes on use 3.3.1 Notes on interrupts (1) Switching an external interrupt detection edge When the external interrupt detection edge must be switched, make sure the following sequence. Reason The interrupt circuit recognizes the switching of the detection edge as the change of external input signals. This may cause an unnecessary interrupt. Clear an interrupt enable bit to “0” (interrupt disabled) Switch the detection edge Clear an interrupt request bit to “0” (no interrupt request issued) Set the interrupt enable bit to “1” (interrupt enabled) (2) Check of interrupt request bit When executing the B BC o r B BS i nstruction to an interrupt request bit of an interrupt request register immediately after this bit is set to “0” by using a data transfer instruction5, execute one or more instructions before executing the BBC o r B BS i nstruction. 5 data transfer instructions: LDM , LDA , STA , STX , and S TY i nstruction Reason If the B BC o r B BS i nstruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0” is read. (3) Stack operation of the program status register If the current program status register is stored on the stack after executing the PHP instruction, the P LP i nstruction has to be entered to get the old program status register back. Before the P LP i nstruction can be executed the S EI instruction has to be executed. Clear the interrupt request bit to “0” (no interrupt issued) NOP (one or more instructions) Execute the BBC or BBS instruction SEI instruction (all interrupt disabled) PLP instruction (pull program status register form stack) 3.3.2 Notes on A-D converter (1) Analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the user side. Reason An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. This may cause the A-D conversion precision to be worse. 7630 Group User’s Manual 3-13 APPENDIX 3.3 Notes on use (2) AV SS p in AV SS pin is the A-D converter power source pin. Regardless of using the A-D conversion function or not, connect AV SS t o the V SS l ine. Reason If the AV SS p in is opened, the microcomputer may have a failure because of noise or others. (3) Clock frequency during an A-D conversion The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. Thus, make sure the following during an A-D conversion. • f(X IN) is 500 kHz or more. • Do not execute the S TP i nstruction and W IT i nstruction. ____________ 3.3.3 Notes on RESET pin ____________ ____________ In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the V SS p in. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following : • Make the length of the wiring which is connected to a capacitor as short as possible. • Be sure to check the operation of application products on the user side. Reason ____________ If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause a microcomputer failure. 3.3.4 Notes on input and output pins (1) Notes in stand-by state In stand-by state 51 for low-power dissipation, do not make input levels of an input port and an I/O port “undefined,” especially for I/O ports of the P-channel and the N-channel open-drain. Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor. When determining a resistance value, note the following: • External circuit • Variation of output levels during the ordinary operation When using built-in pull-up or pull-down resistor, note on varied current values. • When setting as an input port : Fix its input level. • When setting as an output port : Prevent current from flow to the external. 51 s tand-by state : The stop mode by executing the STP instruction or the wait mode by executing the WIT i nstruction Reason Even when setting as an output port with its direction register, in the following state : • P-channel......when the content of the data register (port latch) is “0” •N-channel......when the content of the data register (port latch) is “1” the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Note that the level becomes “undefined” depending on external circuits. Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input port and an I/O port are “undefined.” This may cause power source current. 3-14 7630 Group User’s Manual APPENDIX 3.3 Notes on use (2) Modifying output data with bit managing When the data register (port latch) of an I/O port is modified with the bit managing instruction52, the value of the unspecified bit may be changed. Reason The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an I/O port, the following is executed to all bits of the data register. • As for a bit which is set for an input port: The pin state is read in the CPU, and is written to this bit after bit managing. • As for a bit which is set for an output port: The bit value is read in the CPU, and is written to this bit after bit managing. Note the following : • Even when a port which is set as an output port is changed for an input port, its data register holds the output data. • As for a bit of which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its data register contents. 52 b it managing instructions : S EB, a nd C LB i nstructions 3.3.5 Notes on programming (1) Initialization of processor status register Flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. Reason After a reset, the contents of the processor status register (PS) are undefined except for the I flag which is “1”. (2) How to reference the processor status register To reference the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S)+1. If necessary, execute the PLP instruction to return the PS to its original status. A N OP i nstruction must be executed after every P LP i nstruction. PLP instruction execution Reset Initializing of flags Main program (S) (S) + 1 Stored PS NOP Fig. 3.3.1 Stack memory contents after instruction execution 7630 Group User’s Manual 3-15 APPENDIX 3.3 Notes on use (3) Detection of BRK instruction interrupt source It can be detected that the B RK i nstruction interrupt event or the least priority interrupt event by referring the stored B flag state. Refer to the stored B flag state in the interrupt routine. 7 4 0 1 = B flag PS (S) PCL(Low-order of program counter) (S) + 1 PCH(High-order of program counter) Fig. 3.3.2 Interrupt routine (4) Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal notation, set the decimal mode flag (D) to “1” with the S ED i nstruction. After executing the A DC o r S BC i nstruction, execute another instruction before executing the S EC, C LC , or C LD i nstruction. (5) Notes on status flags in decimal mode When decimal mode is selected, the values of three of the flags in the status register (the N, V, and Z flags) are invalid after a ADC or SBC instruction is executed. The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be initialezed to “1” before each calculation. Set D flag to “1” ADC or SBC instruction NOP instruction SEC, CLC, or CLD instruction ( 6) JPM instruction When using the J MP i nstruction in indirect addressing mode, do not specify the last address on a page as an indirect address. 3-16 7630 Group User’s Manual APPENDIX 3.4 Countermeasures against noise 3.4 Countermeasures against noise Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.4.1 Shortest wiring length The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. ____________ (1) Wiring for the RESET input pin ____________ Make the length of wiring which is connected to the RESET input pin as short as possible. Especially, connect ____________ a capacitor across the RESET input pin and the VSS pin with the shortest possible wiring (within 20mm). Reason ____________ The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having ____________ a shorter pulse width than the standard is input to the RESET input pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise Reset circuit VSS RESET VSS Reset circuit VSS RESET VSS N.G. 7630 group O.K. 7630 group ____________ Fig. 3.4.1 Wiring for the RESET input pin (2) Wiring for clock input/output pins • Make the length of wiring which is connected to clock I/O pins as short as possible. • Make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an oscillator and the V SS pin of a microcomputer as short as possible. • Separate the V SS pattern only for oscillation from other V SS p atterns. Reason If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. Noise XIN XOUT VSS XIN XOUT VSS N.G. O.K. Fig. 3.4.2 Wiring for clock I/O pins 7630 Group User’s Manual 3-17 APPENDIX 3.4 Countermeasures against noise (3) Wiring for the V PP p in of the One Time PROM version and the EPROM version Connect an approximately 5 k Ω r esistor to the V PP p in the shortest possible in series. When not connecting the resistor, make the length of wiring for the V PP p in the shortest possible. Note: Even when a circuit which included an approximately 5 kΩ r esistor is used in the Mask ROM version, the microcomputer operates correctly. Reason The V PP p in of the One Time PROM and the EPROM version is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the V PP pin is low to allow the electric current for writing flow into the PROM. Because of this, noise can enter easily. If noise enters the V PP p in, abnormal instruction codes or data are read from the built-in PROM, which may cause a program runaway. 3.4.2 Connection of a bypass capacitor across the V SS l ine and the V CC l ine Connect an approximately 0.1 µF bypass capacitor across the VSS l ine and the VCC l ine as follows: • Connect a bypass capacitor across the VSS pin and the V CC p in at equal length. • Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. • Use lines with a larger diameter than other signal lines for V SS l ine and VCC l ine. • Connect the power source wiring via a bypass capacitor to the VSS p in and the V CC p in. Approximately 5kΩ P11/VPP 7630 group Fig. 3.4.3 Wiring for the V PP pin of the One Time PROM and the EPROM version VCC VCC VSS VSS N.G. O.K. Fig. 3.4.4 Bypass capacitor across the V SS l ine and the VCC l ine 3.4.3 Wiring to analog input pins • Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. • Connect an approximately 1000 pF capacitor across the VSS p in and the analog input pin. Besides, connect the capacitor to the VSS p in as close as possible. Also, connect the capacitor across the analog input pin and the VSS pin at equal length. Noise (Note) Microcomputer Analog input pin Thermistor N.G. O.K. VSS Note: The resistor is used for dividing resistance with a thermistor. Fig. 3.4.5 Analog signal line and a resistor and a capacitor 3-18 7630 Group User’s Manual APPENDIX 3.4 Countermeasures against noise Reason Signals which is input in an analog input pin (such as an A-D converter/comparator input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. If a capacitor between an analog input pin and the VSS pin is grounded at a position far away from the VSS pin, noise on the GND line may enter a microcomputer through the capacitor. 3.4.4 Consideration for oscillator Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. Microcomputer Mutual inductance M Large current GND XIN XOUT VSS Fig. 3.4.6 Wiring for a large current signal line (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. N.G. Do not cross CNTR XIN XOUT VSS Fig. 3.4.7 Wiring to a signal line where potential levels change frequently 7630 Group User’s Manual 3-19 APPENDIX 3.4 Countermeasures against noise (3) Oscillator protection using VSS p attern As for a two-sided printed circuit board, print a V SS p attern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the VSS pattern to the microcomputer V SS p in with the shortest possible wiring. Besides, separate this V SS p attern from other V SS patterns. An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example XIN XOUT VSS Separate the VSS line for oscillation from other VSS lines Fig. 3.4.8 V SS p attern on the underside of an oscillator 3.4.5 Setup for I/O ports Setup I/O ports using hardware and software as follows: • Connect a resistor of 100 Ω o r more to an I/O port in series. • As for an input port, read data several times by a program for checking whether input levels are equal or not. • As for an output port, since the output data may reverse because of noise, rewrite data to its data register at fixed periods. • Rewrite data to direction registers and pull-up control registers (only the product having it) at fixed periods. When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise pulse. O.K. Data bus Direction register Noise Noise N.G. Port latch I/O port pins Fig. 3.4.9 Setup for I/O ports 3-20 7630 Group User’s Manual APPENDIX 3.4 Countermeasures against noise 3.4.6 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. • Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1 ≥ ( Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. • Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set. • Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. • Decrements the SWDT contents by 1 at each interrupt processing. • Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count). • Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less. Main routine (SWDT) ← N CLI Interrupt processing routine (SWDT) ← (SWDT) – 1 Interrupt processing Main processing ≠N (SWDT)= N ? =N Interrupt processing routine errors (SWDT) ≤ 0 ? ≤0 >0 RTI Main routine errors Return Fig. 3.4.10 Watchdog timer by software 7630 Group User’s Manual 3-21 APPENDIX 3.5 List of registers 3.5 List of registers CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) [Address : 000016] B 0 1 2 Stack page selection bit Name Processor mode bits b1 b0 Function 0 0 : Single chip mode 0 1 : Not available 1 0 : Not available 1 1 : Not available 0 : In page 0 1 : In page 1 At reset R W 0 0 1 0 0 0 1 0 3 Not used (“0” when read, don't write “1”.) 4 5 6 Internal clock selection bit 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode) 7 Not used (“0” when read, don't write “1”.) Fig. 3.5.1 Structure of CPU mode register Interrupt request register A b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register A (IREQA) [Address : 000216] B 0 1 Name Not used (“0” when read.) External interrupt INT0 request bit 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested Function At reset R W 0 0 0 0 0 0 0 0 V V V V V V V 2 External interrupt INT1 request bit 3 4 CAN successful transmission interrupt request bit CAN successful receive interrupt request bit 5 CAN overrun interrupt request bit 6 7 CAN error passive interrupt request bit CAN bus off interrupt request bit V Can be cleared to “0” by software, but cannot be set to “1”. Fig. 3.5.2 Structure of Interrupt request register A 3-22 7630 Group User’s Manual APPENDIX 3.5 List of registers Interrupt request register B b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register B (IREQB) [Address : 000316] B Name Function 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested At reset R W V V V V V V V V CAN wake-up 0 interrupt request bit 1 Timer X interrupt request bit 0 0 0 0 0 0 0 0 2 Timer Y interrupt request bit 3 4 5 6 7 Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit V Can be cleared to “0” by software, but cannot be set to “1”. Fig. 3.5.3 Structure of Interrupt request register B Interrupt request register C b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register C (IREQC) [Address : 000416] B Name Function 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested At reset R W V V V V V V V UART receive complete (receive 0 buffer full) interrupt request bit 1 register empty) interrupt request bit 2 UART transmit buffer empty interrupt request bit 3 4 UART receive error interrupt request bit Serial I/O interrupt request bit UART transmit complete (transmit 0 0 0 0 0 0 0 0 5 AD conversion complete interrupt request bit 6 7 Key-on wake-up interrupt request bit Not used (“0” when read.) V Can be cleared to “0” by software, but cannot be set to “1”. Fig. 3.5.4 Structure of Interrupt request register C 7630 Group User’s Manual 3-23 APPENDIX 3.5 List of registers Interrupt control register A b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register A (ICONA) [Address : 000516] B Name Function At reset R W 0 Not used (“0” when read.) 1 External interrupt INT0 enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 0 0 0 0 0 0 0 2 External interrupt INT1 enable bit 3 4 CAN successful transmission interrupt enable bit CAN successful receive interrupt enable bit 5 CAN overrun interrupt enable bit 6 7 CAN error passive interrupt enable bit CAN bus off interrupt enable bit Fig. 3.5.5 Structure of Interrupt control register A Interrupt control register B b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register B (ICONB) [Address : 000616] B 0 1 Name CAN wake-up interrupt enable bit Timer X interrupt enable bit Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 0 0 0 0 0 2 Timer Y interrupt enable bit 3 4 5 6 7 Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit Fig. 3.5.6 Structure of Interrupt control register B 3-24 7630 Group User’s Manual APPENDIX 3.5 List of registers Interrupt control register C b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register C (ICONC) [Address : 000716] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled At reset R W UART receive complete (receive 0 buffer full) interrupt enable bit 1 0 0 0 0 0 0 0 0 UART transmit complete (transmit 0 : Interrupt disabled register empty) interrupt enable bit 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 2 UART transmit buffer empty interrupt enable bit 3 4 UART receive error interrupt enable bit Serial I/O interrupt enable bit 5 AD conversion complete interrupt enable bit 6 7 Key-on wake-up interrupt enable bit Not used (“0” when read.) Fig. 3.5.7 Structure of Interrupt control register C Port Pi register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi register (Pi) (i = 0, 1, 2, 3, 4) [Address : 000816, 000A16, 000C16, 000E16, 001016] B 0 1 2 3 4 5 6 7 Port Pi0 Port Pi1 Port Pi2 Port Pi3 Port Pi4 Port Pi5 Port Pi6 Port Pi7 Name Function • In output mode Write Port latch Read • In input mode Write : Port latch Read : Value of pins At reset R W 0 0 0 0 0 0 0 0 Note: The bits corresponding to P10, P35, P36 and P37 are reserved (“0” when read, don't write “1”). Fig. 3.5.8 Structure of Port Pi register (i = 0, 1, 2, 3, 4) 7630 Group User’s Manual 3-25 APPENDIX 3.5 List of registers Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4) [Address : 000916, 000B16, 000D16, 000F16, 001116] B 0 1 2 3 4 5 6 7 Name Port Pi direction register Function 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode At reset R W 0 0 0 0 0 0 0 0 Note: The direction control bits corresponding to P10, P11, P35, P36 and P37 are reserved (“0” when read, don't write “1”). Fig. 3.5.9 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4) Serial I/O shift register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O shift register (SIO) [Address : 001216] B Function At reset R W 0 A shift register for serial transmission and reception. At transmitting : Set transmission data. 1 At receiving : Store received data. 2 3 4 5 6 7 ? ? ? ? ? ? ? ? Note: A content of the Transmit buffer register cannot be read out. A data cannot be written to the Receive buffer register. Fig. 3.5.10 Structure of Serial I/O shift register 3-26 7630 Group User’s Manual APPENDIX 3.5 List of registers Serial I/O control register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O control register (SIOCON) [Address : 001316] B 0 1 Name Clock divider selection bits b2 b1 b0 Function 0 0 0 : φ divided by 4 0 0 1 : φ divided by 8 0 1 0 : φ divided by 16 0 1 1 : φ divided by 32 1 0 0 : φ divided by 64 1 0 1 : φ divided by 128 1 1 0 : φ divided by 256 1 1 1 : φ divided by 512 0 : I/O port (P20, P21, P22) 1 : SIN, SOUT, SCLK output pin 0 : I/O port (P23) 1 : SRDY output pin 0 : LSB first 1 : MSB first At reset R W 0 0 2 3 4 5 6 7 P20/SIN, P21/SOUT and P22/SCLK function selection bit P23/SRDY function selection bit Transmission order selection bit 0 0 0 0 0 0 Synchronization clock selection bit 0 : External clock 1 : Internal clock Not used (“0” when read.) Fig. 3.5.11 Structure of Serial I/O control register A-D conversion register b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion register (AD) [Address : 001416] B 0 1 2 3 4 5 6 7 Function The read only register where A-D conversion results are stored. At reset R W ? ? ? ? ? ? ? ? Fig. 3.5.12 Structure of A-D conversion register 7630 Group User’s Manual 3-27 APPENDIX 3.5 List of registers A-D control register b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (ADCON) [Address : 001516] B 0 1 Name Analog input pin selection bits b2 b1 b0 Function 0 0 0 : P00/AN0 0 0 1 : P01/AN1 0 1 0 : P02/AN2 0 1 1 : P03/AN3 1 0 0 : P04/AN4 1 0 1 : P05/AN5 1 1 0 : P06/AN6 1 1 1 : P07/AN7 0 : Conversion in progress 1 : Conversion completed (Note) 0 : Off 1 : On At reset R W 0 0 2 3 A-D conversion completion bit 4 VREF input switch bit 0 1 0 0 0 0 5 Not used (“0” when read, don't write “1”.) 6 7 Note: Don’t set this bit to “1” during A-D conversion. Fig. 3.5.13 Structure of A-D control register Timer 1, Timer 3 b7 b6 b5 b4 b3 b2 b1 b0 Timer 1 (T1) [Address : 001616] Timer 3 (T3) [Address : 001816] B Function At reset R W 0 q Set “0016” to “FF16” as Timer 1 or Timer 3 count value. 1 q The timer value is written to timer and latch at the same time. 2 3 4 5 6 7 q To get the actual Timer 1 or Timer 3 value read out the 1 1 1 1 1 1 1 1 corresponding timer register. Fig. 3.5.14 Structure of Timer 1, Timer 3 3-28 7630 Group User’s Manual APPENDIX 3.5 List of registers Timer 2 b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2) [Address : 001716] B Function At reset R W 0 q Set “0016” to “FF16” as Timer 2 count value. 1 q The timer value is written to Timer 2 and latch at the same time 2 3 4 5 6 7 1 0 0 0 0 0 0 0 or to the latch only (Note). q To get the actual Timer 2 value read out the Timer 2 register. Note: Depinding on the Timer 2 write control bit (bit 2 of the Timer 123 mode register [address: 001916] ). Fig. 3.5.15 Structure of Timer 2 Timer 123 mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer 123 mode register (T123M) [Address : 001916] B 0 1 Name PWM polarity selection bit PWM output enable bit Function 0 : Start on “H” level output 1 : Start on “L” level output 0 : PWM output disabled 1 : PWM output enabled 0 : Latch and counter 1 : Latch only 0 : Timer 1 underflow 1 : Pre-divider output 0 : Timer 1 underflow 1 : Pre-divider output At reset R W 0 0 0 0 0 0 1 0 2 Timer 2 write control bit 3 4 Timer 2 count source selection bit Timer 3 count source selection bit 5 Not used (“0” when read, don't write “1”.) 6 7 Pre-divider division ratio bits 0 0 : φ divided by 1 (Note) 0 1 : φ divided by 8 (Note) 1 0 : φ divided by 32 (Note) 1 1 : φ divided by 128 (Note) b7 b6 Note: The internal system clock φ is divided f(XIN) by 2 or by 8. The division ratio is decided by the Internal system clock selection bit (bit 6 of the CPU mode register [address: 000016] ). Fig. 3.5.16 Structure of Timer 123 mode register 7630 Group User’s Manual 3-29 APPENDIX 3.5 List of registers Timer XL, Timer XH, Timer YL, Timer YH b7 b6 b5 b4 b3 b2 b1 b0 Timer XL (TXL), Timer XH (TXH) [Address : 001A16, 001B16] Timer YL (TYL), Timer YH (TYH) [Address : 001C16, 001D16] B 0 1 2 3 4 5 6 7 Function q Set “000016” to “FFFF16” as timer count value. q Write access At reset R W 1 1 1 1 1 1 1 1 The timer value is written to Timer X or Timer Y and latch at the same timer or to the latch only (Note). Write first low byte (TXL, TYL) and then high byte (TXH, TYH). q Read access To get the actual Timer X or Timer Y value read out the corresponding timer register. A measurement value is read out in pulse period and pulse width measurement mode. Read first high byte (TXH, TYH) and then low byte (TXL, TYL). Note: Depinding on the Timer X or Timer Y data write control bit (bit 0 of the Timer X or Timer Y mode register [address: 001E16, 001F16] ). Fig. 3.5.17 Structure of Timer XL, Timer XH, Timer YL, Timer YH Timer X mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register (TXM) [Address : 001E16] B 0 Name Timer X data write control bit Function 0 : Data is written to latch and timer. 1 : Data is written to latch only. At reset R W 0 0 0 0 0 0 1 2 Not used (“0” when read, don't write “1”.) 3 4 5 CNTR0 polarity selection bit Timer X mode bits b5 b4 0 0 : Timer mode 0 1 : Bi-phase counter mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode 0 : For event counter mode, rising edge active For interrupt request, falling edge active For pulse width measurement mode, measure “H” period 1 : For event counter mode, falling edge active For interrupt request, rising edge active For pulse width measurement mode, measure “L” period 6 0 7 Timer X stop control bit 0 : Timer counting 1 : Timer stopped 0 Fig. 3.5.18 Structure of Timer X mode register 3-30 7630 Group User’s Manual APPENDIX 3.5 List of registers Timer Y mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer Y mode register (TYM) [Address : 001F16] B Name b1 b0 Function 0 0 : φ divided by 4 (Note) 0 1 : φ divided by 16 (Note) 1 0 : φ divided by 64 (Note) 1 1 : φ divided by 128 (Note) 0 0 : φ divided by 2 (Note) 0 1 : φ divided by 8 (Note) 1 0 : φ divided by 32 (Note) 1 1 : φ divided by 64 (Note) b5 b4 b3 b2 At reset R W Timer X count source selection 0 bits 1 2 Timer Y count source selection bits 3 4 5 CNTR1 polarity selection bit Timer Y operation mode bits 0 0 0 0 0 0 0 0 1 1 0 : Timer mode 1 : Pulse period measurement mode 0 : Event counter mode 1 : H/L pulse width measurement mode 6 0 : For event counter mode, rising edge active For interrupt request, falling edge active For pulse period measurement mode, refer to falling edge 1 : For event counter mode, falling edge active For interrupt request, rising edge active For pulse period measurement mode, refer to rising edge 0 7 Timer Y stop control bit 0 : Timer counting 1 : Timer stopped 0 Note: The internal system clock φ is divided f(XIN) by 2 or by 8. The division ratio is decided by the Internal system clock selection bit (bit 6 of the CPU mode register [address: 000016] ). Fig. 3.5.19 Structure of Timer Y mode register UART mode register b7 b6 b5 b4 b3 b2 b1 b0 UART mode register (UMOD) [Address : 002016] B 0 1 2 3 4 5 6 7 Stop bits selection bit Parity selection bit Parity enable bit UART word length selection bits Name Not used (“0” when read, don't write “1”.) Clock divider selection bits b2 b1 Function At reset R W 0 0 0 0 0 0 0 0 0 0 : φ divided by 1 0 1 : φ divided by 8 1 0 : φ divided by 32 1 1 : φ divided by 256 0 : One stop bit 1 : Two stop bits 0 : Even parity 1 : Odd parity 0 : Parity checking disabled 1 : Parity checking enabled b7 b6 0 0 : 7 bits 0 1 : 8 bits 1 0 : 9 bits 1 1 : Not used Fig. 3.5.20 Structure of UART mode register 7630 Group User’s Manual 3-31 APPENDIX 3.5 List of registers UART baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 UART baud rate generator (UBRG) [Address : 002116] B Function At reset R W 0 A count value of baud rate generator is set. 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? Fig. 3.5.21 Structure of UART baud rate generator UART control register b7 b6 b5 b4 b3 b2 b1 b0 UART control register (UCON) [Address : 002216] B 0 1 Name Transmit enable bit Receive enable bit Transmission initialization bit 2 Function 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled 0 : No action 1 : Initialize the transmit enable bit and transmit status register flags. Stop transmission. 0 : No action 1 : Initialize the receive enable bit and receive status register flags. At reset R W 0 0 0 Receive initialization bit 3 0 4 Not used (“0” when read, don't write “1”.) 5 6 7 0 0 0 0 Fig. 3.5.22 Structure of UART control register 3-32 7630 Group User’s Manual APPENDIX 3.5 List of registers UART status register b7 b6 b5 b4 b3 b2 b1 b0 UART status register (USTS) [Address : 002316] B 0 1 Name Transmission register empty flag Transmission buffer empty flag Function 0 : Register full 1 : Register empty 0 : Buffer full 1 : Buffer empty 0 : Buffer full 1 : Buffer empty 0 : No parity error detected 1 : Parity error detected 0 : No framing error detected 1 : Framing error detected 0 : No overrun detected 1 : Overrun detected 0 : No error detected 1 : Error detected At reset R W 1 1 1 0 0 0 0 0 2 Receive buffer full flag 3 4 5 6 7 Receive parity error flag Receive framing error flag Receive overrun flag Receive error sum flag Not used (“0” when read.) Fig. 3.5.23 Structure of UART status register UART transmit buffer register 1 UART transmit buffer register 2 b7 b6 b5 b4 b3 b2 b1 b0 UART transmit buffer register 1 (UTBR1) [Address : 002416] UART transmit buffer register 2 (UTBR2) [Address : 002516] B 0 1 2 3 4 5 6 7 Function Transmit data is written to this buffer register (consisting of low-order and high-order byte). At reset R W ? ? ? ? ? ? ? ? Fig. 3.5.24 Structure of UART transmit buffer register 1, 2 7630 Group User’s Manual 3-33 APPENDIX 3.5 List of registers UART receive buffer register 1 UART receive buffer register 2 b7 b6 b5 b4 b3 b2 b1 b0 UART receive buffer register 1 (URBR1) [Address : 002616] UART receive buffer register 2 (URBR2) [Address : 002716] B 0 1 2 3 4 5 6 7 Function Receive data is read from this buffer register (consisting of low-order and high-order byte). At reset R W ? ? ? ? ? ? ? ? Fig. 3.5.25 Structure of UART receive buffer register 1, 2 Port Pi pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi pull-up control register (PUPi) (i = 0, 2) [Address : 002816, 002A16] B 0 1 Name Pi0 pull-up transistor control bit Pi1 pull-up transistor control bit 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up Function At reset R W 0 0 0 0 0 0 0 0 2 Pi2 pull-up transistor control bit 3 4 5 6 7 Pi3 pull-up transistor control bit Pi4 pull-up transistor control bit Pi5 pull-up transistor control bit Pi6 pull-up transistor control bit Pi7 pull-up transistor control bit Fig. 3.5.26 Structure of Port Pi pull-up control register (i = 0, 2) 3-34 7630 Group User’s Manual APPENDIX 3.5 List of registers Port P1 pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Port P1 pull-up control register (PUP1) [Address : 002916] B Name Function At reset R W 0 Not used (“0” when read, don't write “1”.) 1 2 3 4 5 6 7 P12 pull-up transistor control bit P13 pull-up transistor control bit P14 pull-up transistor control bit P15 pull-up transistor control bit P16 pull-up transistor control bit P17 pull-up transistor control bit 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 0 0 0 0 0 0 0 Fig. 3.5.27 Structure of Port P1 pull-up control register Port P3 pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Port P3 pull-up control register (PUP3) [Address : 002B16] B 0 1 2 3 4 Name P30 pull-up transistor control bit P31 pull-up transistor control bit P32 pull-up/down transistor control bit P33 pull-up transistor control bit P34 pull-up transistor control bit 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up/down 1 : Pull-up/down (Note) 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up Function At reset R W 0 0 0 0 0 0 0 0 5 Not used (“0” when read, don't write “1”.) 6 7 Note: Enables the pull-transistor towards the CAN module recessive level. This level depends on the CAN module dominant level control bit (bit 1 of the Polarity control register [address: 002F16] ). Fig. 3.5.28 Structure of Port P3 pull-up control register 7630 Group User’s Manual 3-35 APPENDIX 3.5 List of registers Port P4 pull-up/down control register b7 b6 b5 b4 b3 b2 b1 b0 Port P4 pull-up/down control register (PUP4) [Address : 002C16] B 0 1 2 3 4 5 6 7 Name P40 pull-up/down transistor control bit P41 pull-up/down transistor control bit P42 pull-up/down transistor control bit P43 pull-up/down transistor control bit P44 pull-up/down transistor control bit P45 pull-up/down transistor control bit P46 pull-up/down transistor control bit P47 pull-up/down transistor control bit Function 0 : No pull-up/down 1 : Pull-up/down (Note) 0 : No pull-up/down 1 : Pull-up/down (Note) 0 : No pull-up/down 1 : Pull-up/down (Note) 0 : No pull-up/down 1 : Pull-up/down (Note) 0 : No pull-up/down 1 : Pull-up/down (Note) 0 : No pull-up/down 1 : Pull-up/down (Note) 0 : No pull-up/down 1 : Pull-up/down (Note) 0 : No pull-up/down 1 : Pull-up/down (Note) At reset R W 0 0 0 0 0 0 0 0 Note: Enables the pull-transistor towards the passive polarity of key-on wake-up interrupt. This level depends on the Key-on wake-up polarity control bit (bit 0 of the Polarity control register [address: 002F16] ). Fig. 3.5.29 Structure of Port P4 pull-up/down control register Interrupt polarity selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt polarity selection register (IPOL) [Address : 002D16] B Name Function At reset R W 0 Not used (“0” when read, don't write “1”.) 0: Falling edge active 1 INT0 interrupt edge selection bit (Note) 1: Rising edge active 0: Falling edge active 2 INT1 interrupt edge selection bit (Note) 1: Rising edge active 3 Not used (“0” when read, don't write “1”.) 4 5 6 7 0 0 0 0 0 0 0 0 Note: To use the external interrupt functions, the pull-up transistor corresponding to the selected active level must be enabled by the corresponding pull-up transistor control bits of the Port P1 pull-up control register). Fig. 3.5.30 Structure of Interrupt polarity selection register 3-36 7630 Group User’s Manual APPENDIX 3.5 List of registers Watchdog timer register (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer register (WDT) [Address : 002E16] B Name 0 Not used (“1” when read.) 1 2 3 4 5 Stop instruction disable bit 6 0 : Stop instruction enabled 1 : Stop instruction disabled Executed two NOP instructions instead of STP instruction (Note 2) Function At reset R W 1 1 1 1 1 1 0 7 Upper byte count source selection 0 : Underflow of the low order counter bit 1 : φ divided by 256 0 Note 1: Writing to this register reloads the watchdog timer counters with the following initial values irrespective of the value written. After reload, the watchdog timer counts down. • The high-order counter WDH (7-bit counter) is set to “7F16”. • The low-order counter WDL (4-bit counter) is set to “F16”. The time-out period of the watchdog timer is nV cycles of the internal system clock φ . V • n = 524288 when the Upper byte count source selection bit is “0”. • n = 32768 when the Upper byte count source selection bit is “1”. On a watchdog timer underflow, the watchdog timer interrupt (non-maskable) occurs. Set the watchdog timer counters to the default values prevent from underflow by writing to this register in main processing. Once the watchdog timer has been started, it cannot be stopped except by reset. Note 2: Once the Stop instruction is disabled, it cannot be enabled again except by reset. Fig. 3.5.31 Structure of Watchdog timer register Polarity control register b7 b6 b5 b4 b3 b2 b1 b0 Polarity control register (PCON) [Address : 002F16] B 0 1 Name Key-on wake-up polarity control bit CAN module dominant level control bit (Note) Function 0: Low level active (P4 pull-up) 1: High level active (P4 pull-down) 0: Low level dominant (P32 pull-up) 1: High level dominant (P32 pull-down) At reset R W 0 0 ? ? ? ? ? ? 2 3 4 Not used (undefined when read.) 5 6 7 Note: The selected dominant level also controls the polarity of the pull-transistor enabled by the P32 pull-up/down transistor control bit (bit 2 of the Port P3 pull-up control register), the transistor pulling toward the recessive level is selected. Fig. 3.5.32 Structure of Polarity control register 7630 Group User’s Manual 3-37 $33(1',; 3.5 List of registers CAN transmit control register b7 b6 b5 b4 b3 b2 b1 b0 CAN transmit control register (CTRM) [Address: 003016] B 0 Name Sleep control bit Function1 0: CAN module in normal mode 1: CAN module in sleep mode 0: CAN module in normal mode 1 Reset/configuration control bit 1: CAN module in configuration mode (plus reset when write) 0: P31/CTX serves as I/O port 1: P31/CTX serves as CTX output port R0: No transmission requested 3 Transmit request bit R1: Transmission requested W0: No operation W1: Request transmission 4 Reserved “0” when read. R0: CPU access possible 5 Transmit buffer control bit R1: CPU access not possible W0: No operation W1: Lock transmit buffer 6 7 Reserved Transmit status bit “0” when read. 0: CAN module idle or receiving 1: CAN module transmitting 0 0 O O X X 0 O O 0 O X 0 O O 1 O O At reset 0 R O W O 2 Port double function control bit 0 O O Note 1: R0/R1 denote read access, W0/W1 denote write access. Fig. 3.5.33 Structure of CAN transmit control register (CTRM) CAN bus timing control register 1 b7 b6 b5 b4 b3 b2 b1 b0 CAN bus timing control register 1 (CBTCON1) [Address: 003116] B 0 1 2 3 4 5 6 7 Propagation time duration control bits Sampling control bit Name b3b2b1b0 Function 0000: Divided by 1 0001: Divided by 2 At reset 0 0 0 0 0 0 0 0 R O O O O O O O O W1 O O O O O O O O Prescaler division ratio selection bits 0010: Divided by 3 … 1101: Divided by 14 1110: Divided by 15 1111: Divided by 16 0: One sample per bit 1: Three samples per bit b7b6b5 000: One time quantum 001: Two time quanta … 110: Seven time quanta 111: Eight time quanta Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 3.5.34 Structure of CAN bus timing control register 1 (CBTCON1) 3-38 7630 Group User’s Manual $33(1',; 3.5 List of registers CAN bus timing control register 2 b7 b6 b5 b4 b3 b2 b1 b0 CAN bus timing control register 2 (CBTCON2) [Address: 003216] B 0 1 2 3 4 5 6 Synchronization jump width control bits Phase buffer segment 2 duration control bits Phase buffer segment 1 duration control bits Name b2b1b0 Function 000: One time quantum 001: Two time quanta … 110: Seven time quanta 111: Eight time quanta b5b4b3 At reset 0 0 0 0 0 0 0 R O O O O O O O W1 O O O O O O O 000: One time quantum 001: Two time quanta … 110: Seven time quanta 111: Eight time quanta b7b6 00: One time quantum 01: Two time quanta 10: Three time quanta 11: Four time quanta 7 0 O O Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 3.5.35 Structure of CAN bus timing control register 2 (CBTCON2) CAN acceptance code register 0 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance code register 0 (CAC0) [Address: 003316] B 0 1 2 3 4 5 6 7 Not used Undefined at read. Name Standard identifier bit 6 Standard identifier bit 7 Standard identifier bit 8 Standard identifier bit 9 Standard identifier bit 10 These bits (except when masked by the acceptance mask register 0, Figure 3.5.41) form the acceptance filtering condition for incoming CAN frames. They must be initialized with the identifier pattern of CAN frames to be received. Function At reset ? ? ? ? ? ? ? ? R O O O O O O O O W1 O O O O O X X X Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 3.5.36 Structure of CAN acceptance code register 0 (CAC0) 7630 Group User’s Manual 3-39 $33(1',; 3.5 List of registers CAN acceptance code register 1 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance code register 1 (CAC1) [Address: 003416] B 0 Not used 1 2 3 4 5 6 7 Standard identifier bit 0 Standard identifier bit 1 Standard identifier bit 2 Standard identifier bit 3 Standard identifier bit 4 Standard identifier bit 5 These bits (except when masked by the acceptance mask register 1, Figure 3.5.42) form the acceptance filtering condition for incoming CAN frames. They must be initialized with the identifier pattern of CAN frames to be received. Undefined at read. ? ? ? ? ? ? ? O O O O O O O X O O O O O O Name Function At reset ? R O W1 X Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 3.5.37 Structure of CAN acceptance code register 1 (CAC1) CAN acceptance code register 2 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance code register 2 (CAC2) [Address: 003516] B 0 1 2 3 4 5 Not used 6 7 Undefined at read. ? ? O O X X Name Extended identifier bit 14 Extended identifier bit 15 Extended identifier bit 16 Extended identifier bit 17 These bits (except when masked by the acceptance mask register 2, Figure 3.5.43) form the acceptance filtering condition for incoming CAN frames. They must be initialized with the identifier pattern of CAN frames to be received. Function At reset ? ? ? ? ? ? R O O O O O O W1 O O O O X X Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 3.5.38 Structure of CAN acceptance code register 2 (CAC2) 3-40 7630 Group User’s Manual $33(1',; 3.5 List of registers CAN acceptance code register 3 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance code register 3 (CAC3) [Address: 003616] B 0 1 2 3 4 5 6 7 Name Extended identifier bit 6 Extended identifier bit 7 Extended identifier bit 8 Extended identifier bit 9 Extended identifier bit 10 Extended identifier bit 11 Extended identifier bit 12 Extended identifier bit 13 These bits (except when masked by the acceptance mask register 3, Figure 3.5.44) form the acceptance filtering condition for incoming CAN frames. They must be initialized with the identifier pattern of CAN frames to be received. Function At reset ? ? ? ? ? ? ? ? R O O O O O O O O W1 O O O O O O O O Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 3.5.39 Structure of CAN acceptance code register 3 (CAC3) CAN acceptance code register 4 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance code register 4 (CAC4) [Address: 003716] B 0 Not used 1 2 3 4 5 6 7 Extended identifier bit 0 Extended identifier bit 1 Extended identifier bit 2 Extended identifier bit 3 Extended identifier bit 4 Extended identifier bit 5 These bits (except when masked by the acceptance mask register 4, Figure 3.5.45) form the acceptance filtering condition for incoming CAN frames. They must be initialised with the identifier pattern of CAN frames to be received. Undefined at read. ? ? ? ? ? ? ? O O O O O O O X O O O O O O Name Function At reset ? R O W1 X Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 3.5.40 Structure of CAN acceptance code register 4 (CAC4) 7630 Group User’s Manual 3-41 $33(1',; 3.5 List of registers CAN acceptance mask register 0 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance mask register 0 (CAM0) [Address: 003816] B 0 1 2 3 4 5 6 7 These bits must be set to "0". Name Standard identifier mask bit 6 Standard identifier mask bit 7 Standard identifier mask bit 8 Standard identifier mask bit 9 Standard identifier mask bit 10 0: Mask identifier bit (don’t care) 1: Compare identifier bit Function These bits mask the corresponding bits of the acceptance code register 0, Figure 3.5.36 from the acceptance filtering. At reset ? ? ? ? ? ? ? ? R O O O O O O O O W1 O O O O O O O O Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 3.5.41 Structure of CAN acceptance mask register 0 (CAM0) CAN acceptance mask register 1 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance mask register 1 (CAM1) [Address: 003916] B 0 These bits must be set to "0". 1 2 3 4 5 6 7 Standard identifier mask bit 0 Standard identifier mask bit 1 Standard identifier mask bit 2 Standard identifier mask bit 3 Standard identifier mask bit 4 Standard identifier mask bit 5 ? ? ? ? ? ? ? O O O O O O O O O O O O O O Name Function At reset ? R O W1 O 0: Mask identifier bit (don’t care) 1: Compare identifier bit These bits mask the corresponding bit of the acceptance code register 1, Figure 3.5.37 from the acceptance filtering. Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 3.5.42 Structure of CAN acceptance mask register 1 (CAM1) 3-42 7630 Group User’s Manual $33(1',; 3.5 List of registers CAN acceptance mask register 2 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance mask register 2 (CAM2) [Address: 003A16] B 0 1 2 3 4 5 These bits must be set to "0". 6 7 ? ? O O O O Name Extended identifier mask bit 14 Extended identifier mask bit 15 Extended identifier mask bit 16 Function At reset ? ? ? ? ? ? R O O O O O O W1 O O O O O O 0: Mask identifier bit (don’t care) 1: Compare identifier bit These bits mask the corresponding bits of the acceptance code register 2, Figure Extended identifier mask bit 17 3.5.38 from the acceptance filtering. Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 3.5.43 Structure of CAN acceptance mask register 2 (CAM2) CAN acceptance mask register 3 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance mask register 3 (CAM3) [Address: 003B16] B 0 1 2 3 4 5 6 7 Name Extended identifier mask bit 6 Extended identifier mask bit 7 Extended identifier mask bit 8 Extended identifier mask bit 9 Extended identifier mask bit 10 Extended identifier mask bit 11 These bits mask the corresponding bits of the acceptance code register 3, Figure Extended identifier mask bit 12 3.5.39 from the acceptance filtering. Extended identifier mask bit 13 0: Mask identifier bit (don’t care) 1: Compare identifier bit Function At reset ? ? ? ? ? ? ? ? R O O O O O O O O W1 O O O O O O O O Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 3.5.44 Structure of CAN acceptance mask register 3 (CAM3) 7630 Group User’s Manual 3-43 $33(1',; 3.5 List of registers CAN acceptance mask register 4 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance mask register 4 (CAM4) [Address: 003C16] B 0 These bits must be set to "0". 1 2 3 4 5 6 7 Extended identifier mask bit 0 Extended identifier mask bit 1 Extended identifier mask bit 2 Extended identifier mask bit 3 Extended identifier mask bit 4 Extended identifier mask bit 5 ? ? ? ? ? ? ? O O O O O O O O O O O O O O Name Function At reset ? R O W1 O 0: Mask identifier bit (don’t care) 1: Compare identifier bit These bits mask the corresponding bits of the acceptance code register 4, Figure 3.5.40 from the acceptance filtering. Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). Fig. 3.5.45 Structure of CAN acceptance mask register 4 (CAM4) CAN receive control register b7 b6 b5 b4 b3 b2 b1 b0 CAN receive control register (CREC) [Address: 003D16] B Name Function1 R0: Receive buffer empty (undefined) 0 Receive buffer control bit R1: Receive buffer full W0: Release (clear) receive buffer W1: No operation 1 2 3 Reserved 4 5 6 7 Auto-receive disable bit2 Reserved 0: Auto-receive enabled 1: Auto-receive disabled When these bits are read out, the values are "0". Don’t write to "1" Receive status bit 0: CAN module idle or transmitting 1: CAN module receiving 0 0 0 0 0 0 0 O O O O O O O X X X X X O X 0 O O At reset R W When these bits are read out, the values are "0". Don’t write to "1". Note 1: R0/R1 denote read access, W0/W1 denote write access. Note 2: Suppresses reception of self-initiated/transmitted frames; for details see section 2.4.8, (5). Fig. 3.5.46 Structure of CAN receive control register (CREC) 3-44 7630 Group User’s Manual $33(1',; 3.5 List of registers CAN transmit abort register b7 b6 b5 b4 b3 b2 b1 b0 CAN transmit abort register (CABORT) [Address: 003E16] B Name Function1 R0: No transmit abort requested 0 Transmit abort control bit R1: Transmit abort requested W0: Clear transmit abort request W1: Transmit abort requested 1 2 3 4 5 6 7 Not used Undefined at read. 0 0 0 0 0 0 0 O O O O O O O X X X X X X X 0 O O2 At reset R W Note 1: R0/R1 denote read access, W0/W1 denote write access. Note 2: Setting this bit to “1” is enabled only when CTRM.3 (Figure 3.4.21) is set. Fig. 3.5.47 Structure of CAN transmit abort register (CABORT) CAN transmit/receive buffer registers 0 b7 b6 b5 b4 b3 b2 b1 b0 CAN transmit buffer register 0 (CTB0) [Address: 004016] CAN receive buffer register 0 (CRB0) [Address: 005016] B 0 1 2 3 4 5 6 7 Not used When these bits are read out, the values are "0". Don’t write to "1". Name Standard identifier bit 6 Standard identifier bit 7 Standard identifier bit 8 Standard identifier bit 9 Standard identifier bit 10 For CTB0: These bits represent part of the identifier field of a frame to be transmitted. For CRB0: These bits represent part of the identifier field of a frame received. Function At reset ? ? ? ? ? 0 0 0 R O O O O O O O O W O O O O O X X X Fig. 3.5.48 Structure of CAN transmit/receive buffer registers 0 (CTB0/CRB0) 7630 Group User’s Manual 3-45 $33(1',; 3.5 List of registers CAN transmit/receive buffer registers 1 b7 b6 b5 b4 b3 b2 b1 b0 CAN transmit buffer register 1 (CTB1) [Address: 004116] CAN receive buffer register 1 (CRB1) [Address: 005116] B 0 1 2 3 4 5 6 7 IDE bit1 RTR2/SRR 3 bit Standard identifier bit 0 Standard identifier bit 1 Standard identifier bit 2 Standard identifier bit 3 Standard identifier bit 4 Standard identifier bit 5 For CTB1: These bits represent part of the identifier field of a frame to be transmitted. For CRB1: These bits represent part of the identifier field of a frame received. Name Function 0: Standard format 1: Extended format RTR bit (frames of standard format) or SRR bit (frames of extended format) At reset ? ? ? ? ? ? ? ? R O O O O O O O O W O O O O O O O O Note 1: Identifier extension bit Note 2: Remote transmission request bit Note 3: Substitute remote request bit Fig. 3.5.49 Structure of CAN transmit/receive buffer registers 1 (CTB1/CRB1) CAN transmit/receive buffer registers 2 b7 b6 b5 b4 b3 b2 b1 b0 CAN transmit buffer register 2 (CTB2) [Address: 004216] CAN receive buffer register 2 (CRB2) [Address: 005216] B 0 1 2 3 4 5 Not used 6 7 Name Extended identifier bit 14 Extended identifier bit 15 Extended identifier bit 16 Extended identifier bit 17 For CTB2: These bits represent part of the identifier field of a frame to be transmitted. For CRB2: These bits represent part of the identifier field of a frame received. Function At reset ? ? ? ? 0 0 0 0 R O O O O O O O O W O O O O X X X X When these bits are read out, the values are "0". Don’t write to "1". Fig. 3.5.50 Structure of CAN transmit/receive buffer registers 2 (CTB2/CRB2) 3-46 7630 Group User’s Manual $33(1',; 3.5 List of registers CAN transmit/receive buffer registers 3 b7 b6 b5 b4 b3 b2 b1 b0 CAN transmit buffer register 3 (CTB3) [Address: 004316] CAN receive buffer register 3 (CRB3) [Address: 005316] B 0 1 2 3 4 5 6 7 Name Extended identifier bit 6 Extended identifier bit 7 Extended identifier bit 8 Extended identifier bit 9 Extended identifier bit 10 Extended identifier bit 11 Extended identifier bit 12 Extended identifier bit 13 For CTB3: These bits represent part of the identifier field of a frame to be transmitted. For CRB3: These bits represent part of the identifier field of a frame received. Function At reset ? ? ? ? ? ? ? ? R O O O O O O O O W O O O O O O O O Fig. 3.5.51 Structure of CAN transmit/receive buffer registers 3 (CTB3/CRB3) CAN transmit/receive buffer registers 4 b7 b6 b5 b4 b3 b2 b1 b0 CAN transmit buffer register 4 (CTB4) [Address: 004416] CAN receive buffer register 4 (CRB4) [Address: 005416] B 0 Name r1 bit (reserved bit 1) Function For CTB4: Set this bit to “0” (must be sent dominant; applicable for extended format only). 0: Data frame 1: Remote frame At reset ? R O W O 1 2 3 4 5 6 7 RTR1 bit Extended identifier bit 0 Extended identifier bit 1 Extended identifier bit 2 Extended identifier bit 3 Extended identifier bit 4 Extended identifier bit 5 ? ? ? O O O O O O O O O O O O O O For CTB4: These bits represent part of the identifier field of a frame to be transmitted. For CRB4: These bits represent part of the identifier field of a frame received. ? ? ? ? Note 1: Remote transmission request bit Fig. 3.5.52 Structure of CAN transmit/receive buffer registers 4 (CTB4/CRB4) 7630 Group User’s Manual 3-47 $33(1',; 3.5 List of registers CAN transmit/receive buffer registers 5 b7 b6 b5 b4 b3 b2 b1 b0 CAN transmit buffer register 5 (CTB5) [Address: 004516] CAN receive buffer register 5 (CRB5) [Address: 005516] B 0 DLC bit 0 Name Function The data length code indicates the number of data bytes in a data frame: b3b2b1b0 At reset ? R O W O 1 2 3 4 5 6 7 DLC bit 1 DLC bit 2 DLC bit 3 r0 bit (reserved bit 0) 0000: Zero data bytes 0001: One data byte 0010: Two data bytes … 0111: Seven data bytes 1000: Eight data bytes For CTB5: Set this bit to “0” (must be sent dominant). ? ? ? ? ? O O O O O O O O O O O O O O Not used When these bits are read out, the value are "0". Don't write to "1". ? ? Fig. 3.5.53 Structure of CAN transmit/receive buffer registers 5 (CTB5/CRB5) CAN transmit/receive buffer registers 6 to D b7 b6 b5 b4 b3 b2 b1 b0 CAN transmit buffer registers 6 to D (CTB6 to CTBD) [Addresses: 004616 to 004D16] CAN receive buffer registers 6 to D (CRB6 to CRBD) [Addresses: 005616 to 005D 16] B 0 1 2 3 4 5 6 7 Data bit 0 Data bit 1 Data bit 2 Data bit 3 Data bit 4 Data bit 5 Data bit 6 Data bit 7 For CRBi: These bits represent the byte number (i – 6) of the data field of a frame received. (i = 6 to D16) For CTBi: These bits represent the byte number (i – 6) of the data field of a frame to be transmitted. Name Function At reset ? ? ? ? ? ? ? ? R O O O O O O O O W O O O O O O O O Fig. 3.5.54 Structure of CAN transmit/receive buffer registers 6 to D (CTB6–D/CRB6–D) 3-48 7630 Group User’s Manual APPENDIX 3.6 Mask ROM ordering method 3.6 Mask ROM ordering method GZZ-SH52-70B Mask ROM number Note : Please fill in all items marked g. Receipt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37630M4T-XXXFP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature g Customer ) Date issued Date: g 1. Confirmation Specify the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM EPROM type (indicate the type used) Issuance signature Company name TEL ( Submitted by Supervisor (hexadecimal notation) 27512 EPROM address 000016 Product name 000F16 001016 C07F16 C08016 FFFB16 FFFC16 FFFF16 ASCII code : ‘M37630M4T-’ In the address space of the microcomputer, the internal ROM area is from address C08016 to FFFB16 . The reset vector is stored in addresses FFFA16 and FFFB16 . data ROM (16K-132) bytes (1) Set the data in the unused area (the shaded area of the diagram) to “FF16”. (2) The ASCII codes of the product name “M37630M4T–” must be entered in addresses 000016 to 000F16. And set the data “FF 16” in addresses 000A16 to 000F16 . The ASCII codes and addresses are listed to the right in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘6’ = 3616 ‘3’ = 3316 ‘0’ = 3016 ‘M’ = 4D16 ‘4’ = 3416 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F 16 ‘T’ = 54 16 ‘–’ = 2D 16 FF 16 FF 16 FF 16 FF 16 FF 16 FF 16 (1/2) 7630 Group User’s Manual 3-49 APPENDIX 3.6 Mask ROM ordering method GZZ-SH52-70B Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37630M4T-XXXFP MITSUBISHI ELECTRIC We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27512 *= $0000 .BYTE ‘M37630M4T–’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (44P6N) and attach it to the mask ROM confirmation form. g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator External clock input At what frequency? Quartz crystal Other ( f(XIN) = ) MHz g 4. Comments (2/2) 3-50 7630 Group User’s Manual APPENDIX 3.7 Mark specification form 3.7 Mark specification form 44P6N (44-PIN QFP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark 33 23 34 Mitsubishi lot number (6-digit, or 7-digit) 22 Mitsubishi IC catalog name 44 12 1 11 B. Customer’s Parts Number + Mitsubishi IC Catalog Name 33 23 34 22 Customer’s Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name and Mitsubishi lot number Note 4 : If the Mitsubishi logo is not required, check the box below. Mitsubishi logo is not required 44 12 1 11 Notes 1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s parts number can be up to 7 characters: Only 0 to 9, A to Z, +, -, /, (, ), &, ©, . ( period), and , (comma) are usable. C. Special Mark Required 33 23 34 22 Notes1 : If the special mark is to be printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit, or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer’s trade mark logo must be used in the special mark, check the box below. Please submit a clean original of the logo. For the new special character fonts, a clean font original (ideally logo drawing) must be submitted. Special logo required 44 12 1 11 The standard Mitsubishi font is used for all characters except for a logo. 7630 Group User’s Manual 3-51 APPENDIX 3.8 Package outline 3.8 Package outline 44P6N-A EIAJ Package Code QFP44-P-1010-0.80 HD D 44 34 Plastic 44pin 10!10mm body QFP JEDEC Code – Weight(g) 0.59 Lead Material Alloy 42 MD e 1 33 b2 I2 Recommended Mount Pad HE E Symbol 11 23 12 22 A L1 F A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME A1 e y b L Detail F Dimension in Millimeters Min Nom Max 3.05 – – 0 0.1 0.2 2.8 – – 0.3 0.35 0.45 0.13 0.15 0.2 9.8 10.0 10.2 9.8 10.0 10.2 0.8 – – 12.5 12.8 13.1 12.5 12.8 13.1 0.4 0.6 0.8 1.4 – – 0.1 – – 0° 10° – – – 0.5 1.3 – – – – 10.6 10.6 – – A2 80D0 EIAJ Package Code – JEDEC Code – Weight(g) c Glass seal 80pin QFN 21.0±0.2 3.32MAX 1.78TYP 41 40 18.4±0.15 0.8TYP 0.6TYP 64 65 0.8TYP 1.2TYP 25 80 24 1 INDEX 0.5TYP 1.2TYP 3-52 7630 Group User’s Manual 0.8TYP 12.0±0.15 15.6±0.2 ME APPENDIX 3.9 List of instruction codes 3.9 List of instruction codes D3 – D0 Hexadecimal notation 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 D7 – D 4 0 1 2 3 BBS 0, A BBC 0, A BBS 1, A BBC 1, A BBS 2, A BBC 2, A BBS 3, A BBC 3, A BBS 4, A BBC 4, A BBS 5, A BBC 5, A BBS 6, A BBC 6, A BBS 7, A BBC 7, A 4 5 ORA ZP ORA ZP, X AND ZP AND ZP, X EOR ZP EOR ZP, X ADC ZP ADC ZP, X STA ZP STA ZP, X LDA ZP LDA ZP, X CMP ZP CMP ZP, X SBC ZP SBC ZP, X 6 ASL ZP ASL ZP, X ROL ZP ROL ZP, X LSR ZP LSR ZP, X ROR ZP ROR ZP, X STX ZP STX ZP, Y LDX ZP LDX ZP, Y DEC ZP DEC ZP, X INC ZP INC ZP, X 7 BBS 0, ZP BBC 0, ZP BBS 1, ZP BBC 1, ZP BBS 2, ZP BBC 2, ZP BBS 3, ZP BBC 3, ZP BBS 4, ZP BBC 4, ZP BBS 5, ZP BBC 5, ZP BBS 6, ZP BBC 6, ZP BBS 7, ZP BBC 7, ZP 8 9 ORA IMM ORA ABS, Y AND IMM AND ABS, Y EOR IMM EOR ABS, Y ADC IMM ADC ABS, Y — STA ABS, Y LDA IMM LDA ABS, Y CMP IMM CMP ABS, Y SBC IMM SBC ABS, Y A ASL A DEC A ROL A INC A LSR A — ROR A — B SEB 0, A CLB 0, A SEB 1, A CLB 1, A SEB 2, A CLB 2, A SEB 3, A CLB 3, A SEB 4, A CLB 4, A SEB 5, A CLB 5, A SEB 6, A CLB 6, A SEB 7, A CLB 7, A C D ORA ABS E ASL ABS F SEB 0, ZP 0000 BRK ORA JSR IND, X ZP, IND ORA IND, Y AND IND, X AND IND, Y EOR IND, X EOR IND, Y CLT JSR SP SET — PHP — 0001 1 BPL JSR ABS BMI — BIT ZP — COM ZP — TST ZP — STY ZP STY ZP, X LDY ZP LDY ZP, X CPY ZP — CPX ZP — CLC — BIT ABS LDM ZP JMP ABS — JMP IND — STY ABS — LDY ABS ORA ASL CLB ABS, X ABS, X 0, ZP AND ABS ROL ABS SEB 1, ZP 0010 2 PLP 0011 3 SEC AND ROL CLB ABS, X ABS, X 1, ZP EOR ABS LSR ABS SEB 2, ZP 0100 4 RTI STP PHA 0101 5 BVC — CLI EOR LSR CLB ABS, X ABS, X 2, ZP ADC ABS ROR ABS SEB 3, ZP 0110 6 RTS MUL ADC IND, X ZP, X ADC IND, Y STA IND, X STA IND, Y LDA IND, X — RRF ZP — LDX IMM PLA 0111 7 BVS SEI ADC ROR CLB ABS, X ABS, X 3, ZP STA ABS STA ABS, X LDA ABS STX ABS — LDX ABS SEB 4, ZP CLB 4, ZP SEB 5, ZP 1000 8 BRA DEY TXA 1001 9 BCC LDY IMM BCS CPY IMM BNE CPX IMM BEQ TYA TXS 1010 A TAY TAX 1011 B JMP LDA IND, Y ZP, IND CMP IND, X CMP IND, Y WIT CLV TSX LDY LDA LDX CLB ABS, X ABS, X ABS, Y 5, ZP CPY ABS — CPX ABS — CMP ABS DEC ABS SEB 6, ZP 1100 C INY DEX 1101 D — CLD — CMP DEC CLB ABS, X ABS, X 6, ZP SBC ABS INC ABS SEB 7, ZP 1110 E DIV SBC IND, X ZP, X SBC IND, Y — INX NOP 1111 F SED — SBC INC CLB ABS, X ABS, X 7, ZP 3-byte instruction 2-byte instruction 1-byte instruction 7630 Group User’s Manual 3-53 APPENDIX 3.10 Machine instructions 3.10 Machine instructions Addressing mode Symbol Function Details IMP OP n ADC (Note 1) (Note 8) When T = 0 A←A+M+C When T = 1 M(X) ← M(X) + M + C Adds the carry, accumulator and memory contents. The results are entered into the accumulator. Adds the contents of the memory in the address indicated by index register X, the contents of the memory specified by the addressing mode and the carry. The results are entered into the memory at the address indicated by index register X. “AND’s” the accumulator and memory contents. The results are entered into the accumulator. “AND’s” the contents of the memory of the address indicated by index register X and the contents of the memory specified by the addressing mode. The results are entered into the memory at the address indicated by index register X. Shifts the contents of accumulator or contents of memory one bit to the left. The low order bit of the accumulator or memory is cleared and the high order bit is shifted into the carry flag. Branches when the contents of the bit specified in the accumulator or memory is “0”. IMM # OP n 69 2 A # OP n 2 BIT, A, R # OP n ZP BIT, ZP, R # OP n 2 # # OP n 65 3 ASL C← 7 0 ←0 BBC Ai or Mi = 0? BBS Ai or Mi = 1? BCC (Note 5) BCS (Note 5) BEQ (Note 5) BIT C = 0? C = 1? Z = 1? V A M BMI (Note 5) BNE (Note 5) BPL (Note 5) BRA (Note 6) BRK N = 1? Z = 0? N = 0? PC ← PC ± offset B←1 PC ← PC+2 M(S) ← PCH S←S–1 M(S) ← PCL S←S–1 M(S) ← PS S←S–1 I←1 PCL ← ADL PCH ← ADH 3-54 V When T = 1 M(X) ← M(X) V AND (Note 1) When T = 0 A←A M M 29 2 2 25 3 2 0A 1 1 06 5 2 13 4 2 + 20i (Note 4) 03 4 2 + 20i (Note 4) 17 5 3 + 20i (Note 6) 07 5 3 + 20i (Note 6) Branches when the contents of the bit specified in the accumulator or memory is “1”. Branches when the contents of carry flag is “0”. Branches when the contents of carry flag is “1”. Branches when the contents of zero flag is “1”. “AND’s” the contents of accumulator and memory. The results are not entered anywhere. Branches when the contents of negative flag is “1”. Branches when the contents of zero flag is “0”. 24 3 2 Branches when the contents of negative flag is “0”. Jumps to address specified by adding offset to the program counter. Executes a software interrupt. 00 7 1 7630 Group User’s Manual APPENDIX 3.10 Machine instructions Addressing mode ZP, X OP n 75 4 ZP, Y # OP n 2 ABS # OP n 6D 4 ABS, X # OP n 3 7D 5 ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 5 T • 4 B • 3 D • 2 I • 1 Z Z 0 C C # OP n 3 79 5 # OP n 3 # OP n 61 6 # OP n 2 71 6 # OP n 2 NV NV 35 4 2 2D 4 3 3D 5 3 39 5 3 21 6 2 31 6 2 N • • • • • Z • 16 6 2 0E 6 3 1E 7 3 N • • • • • Z C • • • • • • • • • • • • • • • • 90 2 2 • • • • • • • • B0 2 2 • • • • • • • • F0 2 2 • • • • • • • • 2C 4 3 M7 M6 • • • • Z • 30 2 2 • • • • • • • • D0 2 2 • • • • • • • • 10 2 2 • • • • • • • • 80 3 2 • • • • • • • • • • • 1 • 1 • • 7630 Group User’s Manual 3-55 APPENDIX 3.10 Machine instructions Addressing mode Symbol Function Details IMP OP n BVC (Note 5) BVS (Note 5) CLB V = 0? Branches when the contents of overflow flag is “0”. Branches when the contents of overflow flag is “1”. Clears the contents of the bit specified in the accumulator or memory to “0”. Clears the contents of the carry flag to “0”. 18 1 1 1B 1 + 20i 1 1F 5 + 20i 2 IMM # OP n A # OP n BIT, A, R # OP n ZP BIT, ZP, R # OP n # # OP n V = 1? Ai or Mi ← 0 C←0 D←0 I←0 T←0 V←0 When T = 0 A–M When T = 1 M(X) – M M←M X–M CLC CLD Clears the contents of decimal mode flag to “0”. Clears the contents of interrupt disable flag to “0”. Clears the contents of index X mode flag to “0”. Clears the contents of overflow flag to “0”. D8 1 1 CLI 58 2 1 CLT 12 1 1 CLV B8 1 1 CMP (Note 3) Compares the contents of accumulator and memory. Compares the contents of the memory specified by the addressing mode with the contents of the address indicated by index register X. Forms a one’s complement of the contents of memory, and stores it into memory. Compares the contents of index register X and memory. Compares the contents of index register Y and memory. Decrements the contents of the accumulator or memory by 1. Decrements the contents of index register X CA 1 by 1. Decrements the contents of index register Y by 1. Divides the 16-bit data that is the contents of M (zz + x + 1) for high byte and the contents of M (zz + x) for low byte by the accumulator. Stores the quotient in the accumulator and the 1’s complement of the remainder on the stack. “Exclusive-ORs” the contents of accumulator and memory. The results are stored in the accumulator. “Exclusive-ORs” the contents of the memory specified by the addressing mode and the contents of the memory at the address indicated by index register X. The results are stored into the memory at the address indicated by index register X. Increments the contents of accumulator or memory by 1. Increments the contents of index register X by 1. Increments the contents of index register Y by 1. E8 1 1 88 1 1 C9 2 2 C5 3 2 COM 44 5 2 CPX E0 2 2 E4 3 2 CPY Y–M A ← A – 1 or M←M–1 X←X–1 Y←Y–1 A ← (M(zz + X + 1), M(zz + X)) / A M(S) ← 1’s complememt of Remainder S←S–1 When T = 0 – A←AVM When T = 1 – M(X) ← M(X) V M C0 2 2 C4 3 2 DEC 1A 1 1 C6 5 2 DEX DEY 1 DIV EOR (Note 1) 49 2 2 45 3 2 INC A ← A + 1 or M←M+1 X←X+1 Y←Y+1 3A 1 1 E6 5 2 INX INY C8 1 1 3-56 7630 Group User’s Manual APPENDIX 3.10 Machine instructions Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n ABS, X # OP n ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n 2 # 7 Processor status register 6 5 T • 4 B • 3 D • 2 I • 1 Z • 0 C • # OP n # OP n # OP n # OP n # OP n 50 2 NV • • 70 2 2 • • • • • • • • • • • • • • • • • • • • • • • 0 • • • • 0 • • • • • • • • 0 • • • • 0 • • • • • • 0 • • • • • • D5 4 2 CD 4 3 DD 5 3 D9 5 3 C1 6 2 D1 6 2 N • • • • • Z C N • • • • • Z • EC 4 3 N • • • • • Z C CC 4 3 N • • • • • Z C D6 6 2 CE 6 3 DE 7 3 N • • • • • Z • N • • • • • Z • N • • • • • Z • E2 16 2 NV • • • • Z C 55 4 2 4D 4 3 5D 5 3 59 5 3 41 6 2 51 6 2 N • • • • • Z • F6 6 2 EE 6 3 FE 7 3 N • • • • • Z • N • • • • • Z • N • • • • • Z • 7630 Group User’s Manual 3-57 APPENDIX 3.10 Machine instructions Addressing mode Symbol Function Details IMP OP n JMP If addressing mode is ABS PCL ← ADL PCH ← ADH If addressing mode is IND PCL ← M (AD H, ADL) PCH ← M (ADH, AD L + 1) If addressing mode is ZP, IND PCL ← M(00, AD L) PCH ← M(00, AD L + 1) M(S) ← PCH S←S–1 M(S) ← PCL S←S–1 After executing the above, if addressing mode is ABS, PCL ← ADL PCH ← ADH if addressing mode is SP, PCL ← ADL PCH ← FF If addressing mode is ZP, IND, PCL ← M(00, AD L) PCH ← M(00, AD L + 1) When T = 0 A←M When T = 1 M(X) ← M M ← nn X←M Y←M 7 0→ 0 →C Jumps to the specified address. IMM # OP n A # OP n BIT, A, R # OP n ZP BIT, ZP, R # OP n # # OP n JSR After storing contents of program counter in stack, and jumps to the specified address. LDA (Note 2) Load accumulator with contents of memory. Load memory indicated by index register X with contents of memory specified by the addressing mode. Load memory with immediate value. A9 2 2 A5 3 2 LDM 3C 4 3 LDX Load index register X with contents of memory. Load index register Y with contents of memory. Shift the contents of accumulator or memory to the right by one bit. The low order bit of accumulator or memory is stored in carry, 7th bit is cleared. Multiplies the accumulator with the contents of memory specified by the zero page X addressing mode and stores the high byte of the result on the stack and the low byte in the accumulator. No operation. EA 1 1 A2 2 2 A6 3 2 LDY A0 2 2 A4 3 2 LSR 4A 1 1 46 5 2 MUL M(S) · A ← A ! M(zz + X) S←S–1 NOP PC ← PC + 1 When T = 0 A←AVM When T = 1 M(X) ← M(X) V M ORA (Note 1) “Logical OR’s” the contents of memory and accumulator. The result is stored in the accumulator. “Logical OR’s” the contents of memory indicated by index register X and contents of memory specified by the addressing mode. The result is stored in the memory specified by index register X. 09 2 2 05 3 2 3-58 7630 Group User’s Manual APPENDIX 3.10 Machine instructions Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n 4C 3 ABS, X # OP n 3 ABS, Y IND ZP, IND # OP n 3 B2 4 IND, X IND, Y REL SP # OP n # 7 Processor status register 6 5 T • 4 B • 3 D • 2 I • 1 Z • 0 C • # OP n # OP n 6C 5 # OP n 2 # OP n # OP n NV • • 20 6 3 02 7 2 22 5 2 • • • • • • • • B5 4 2 AD 4 3 BD 5 3 B9 5 3 A1 6 2 B1 6 2 N • • • • • Z • • • • • • • • • B6 4 2 AE 4 3 BE 5 3 N • • • • • Z • B4 4 2 AC 4 3 BC 5 3 N • • • • • Z • 56 6 2 4E 6 3 5E 7 3 0 • • • • • Z C 62 14 2 N • • • • • Z • • • • • • • • • 15 4 2 0D 4 3 1D 5 3 19 5 3 01 6 2 11 6 2 N • • • • • Z • 7630 Group User’s Manual 3-59 APPENDIX 3.10 Machine instructions Addressing mode Symbol Function Details IMP OP n PHA M(S) ← A S←S–1 Saves the contents of the accumulator in memory at the address indicated by the stack pointer and decrements the contents of stack pointer by 1. Saves the contents of the processor status register in memory at the address indicated by the stack pointer and decrements the contents of the stack pointer by 1. Increments the contents of the stack pointer by 1 and restores the accumulator from the memory at the address indicated by the stack pointer. Increments the contents of stack pointer by 1 and restores the processor status register from the memory at the address indicated by the stack pointer. Shifts the contents of the memory or accumulator to the left by one bit. The high order bit is shifted into the carry flag and the carry flag is shifted into the low order bit. Shifts the contents of the memory or accumulator to the right by one bit. The low order bit is shifted into the carry flag and the carry flag is shifted into the high order bit. Rotates the contents of memory to the right by 4 bits. 48 3 IMM # OP n 1 A # OP n BIT, A, R # OP n ZP BIT, ZP, R # OP n # # OP n PHP M(S) ← PS S←S–1 08 3 1 PLA S←S+1 A ← M(S) 68 4 1 PLP S←S+1 PS ← M(S) 28 4 1 ROL 7 ← 0 ←C ← 2A 1 1 26 5 2 ROR 7 C→ 0 → 6A 1 1 66 5 2 RRF 7 → S←S+1 PS ← M(S) S←S+1 PCL ← M(S) S←S+1 PCH ← M(S) S←S+1 PCL ← M(S) S←S+1 PCH ← M(S) PC ← PC+1 0 → 82 8 2 RTI Returns from an interrupt routine to the main routine. 40 6 1 RTS Returns from a subroutine to the main routine. ne. 60 6 1 SBC (Note 1) (Note 8) When T = 0 A←A–M–C When T = 1 M(X) ← M(X) – M – C Subtracts the contents of memory and complement of carry flag from the contents of accumulator. The results are stored into the accumulator. Subtracts contents of complement of carry flag and contents of the memory indicated by the addressing mode from the memory at the address indicated by index register X. The results are stored into the memory of the address indicated by index register X. Sets the specified bit in the accumulator or memory to “1”. Sets the contents of the carry flag to “1”. 38 1 1 E9 2 2 E5 3 2 SEB Ai or Mi ← 1 C←1 D←1 I←1 T←1 0B 1 + 20i 1 0F 5 + 20i 2 SEC SED Sets the contents of the decimal mode flag to “1”. Sets the contents of the interrupt disable flag to “1”. Sets the contents of the index X mode flag to “1”. F8 1 1 SEI 78 2 1 SET 32 1 1 3-60 7630 Group User’s Manual APPENDIX 3.10 Machine instructions Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n ABS, X # OP n ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 5 T • 4 B • 3 D • 2 I • 1 Z • 0 C • # OP n # OP n # OP n # OP n # OP n NV • • • • • • • • • • N • • • • • Z • (Value saved in stack) 36 6 2 2E 6 3 3E 7 3 N • • • • • Z C 76 6 2 6E 6 3 7E 7 3 N • • • • • Z C • • • • • • • • (Value saved in stack) • • • • • • • • F5 4 2 ED 4 3 FD 5 3 F9 5 3 E1 6 2 F1 6 2 NV • • • • Z C • • • • • • • • • • • • • • • 1 • • • • 1 • • • • • • • • 1 • • • • 1 • • • • • 7630 Group User’s Manual 3-61 APPENDIX 3.10 Machine instructions Addressing mode Symbol Function Details IMP OP n STA M←A Stores the contents of accumulator in memory. IMM # OP n A # OP n BIT, A, R # OP n ZP BIT, ZP, R # OP n 2 # # OP n 85 3 STP (Note 7) STX M←X M←Y X←A Y←A M = 0? X←S A←X S←X A←Y Stops the oscillator. 42 2 1 Stores the contents of index register X in memory. Stores the contents of index register Y in memory. Transfers the contents of the accumulator to index register X. Transfers the contents of the accumulator to index register Y. Tests whether the contents of memory are “0” or not. Transfers the contents of the stack pointer to BA 1 index register X. Transfers the contents of index register X to the accumulator. Transfers the contents of index register X to the stack pointer. Transfers the contents of index register Y to the accumulator. Stops the internal clock. 8A 1 1 AA 1 1 86 3 2 STY 84 3 2 TAX TAY A8 1 1 TST 64 3 2 TSX TXA 1 TXS 9A 1 1 TYA 98 1 1 WIT Notes 1 2 3 4 5 C2 2 1 : The number of cycles “n” is increased by 3 when T is 1. : The number of cycles “n” is increased by 2 when T is 1. : The number of cycles “n” is increased by 1 when T is 1. : The number of cycles “n” is increased by 1 when branching has occurred. : The number of cycles “n” is increased by 1 when branching to the same page area has occurred. The number of cycles “n” is increased by 2 when branching to the differrent page area has occurred. 6 : The number of cycles “n” is increased by 1 when branching to the differrent page area has occurred. 7 : The number of cycles “n” is 2 when the STP instruction is disabled. 8 : V flag is invalid in decimal operation mode. 3-62 7630 Group User’s Manual APPENDIX 3.10 Machine instructions Addressing mode ZP, X OP n 95 4 ZP, Y # OP n 2 ABS # OP n 8D 4 ABS, X # OP n 3 9D 5 ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 5 T • 4 B • 3 D • 2 I • 1 Z • 0 C • # OP n 3 99 5 # OP n 3 # OP n 81 6 # OP n 2 91 6 # OP n 2 NV • • • • • • • • • • 96 4 2 8E 4 3 • • • • • • • • 94 4 2 8C 4 3 • • • • • • • • N • • • • • Z • N • • • • • Z • N • • • • • Z • N • • • • • Z • N • • • • • Z • • • • • • • • • N • • • • • Z • • • • • • • • • Symbol IMP IMM A BIT, BIT, A A, R Contents Implied addressing mode Immediate addressing mode Accumulator or Accumulator addressing mode Accumulator bit relative addressing mode Accumulator bit addressing mode Zero page addressing mode Zero page bit relative addressing mode Zero page bit addressing mode Zero page X addressing mode Zero page Y addressing mode Absolute addressing mode Absolute X addressing mode Absolute Y addressing mode Indirect absolute addressing mode Zero page indirect absolute addressing mode Indirect X addressing mode Indirect Y addressing mode Relative addressing mode Special page addressing mode Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag X-modified arithmetic mode flag Overflow flag Negative flag + – V – V – ← X Y S PC PS PCH PCL ADH ADL FF nn M V Symbol Contents Addition Subtraction Logical OR Logical AND Logical exclusive OR Negation Shows direction of data flow Index register X Index register Y Stack pointer Program counter Processor status register 8 high-order bits of program counter 8 low-order bits of program counter 8 high-order bits of address 8 low-order bits of address FF in Hexadecimal notation Immediate value Memory specified by address designation of any addressing mode Memory of address indicated by contents of index register X Memory of address indicated by contents of stack pointer Contents of memory at address indicated by ADH and ADL, in ADH is 8 high-order bits and ADL is 8 low-order bits. Contents of address indicated by zero page ADL 1 bit of accumulator 1 bit of memory Opcode Number of cycles Number of bytes ZP BIT, ZP, R BIT, ZP ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP C Z I D B T V N M(X) M(S) M(AD H, ADL) M(00, AD L) Ai Mi OP n # 7630 Group User’s Manual 3-63 APPENDIX 3.11 SFR memory map 3.11 SFR memory map 000016 CPU mode register 000116 Not used 000216 Interrupt request register A 000316 Interrupt request register B 000416 Interrupt request register C 000516 Interrupt control register A 000616 Interrupt control register B 000716 Interrupt control register C 000816 Port P0 register 000916 Port P0 direction register 000A16 Port P1 register 000B16 Port P1 direction register 000C16 Port P2 register 000D16 Port P2 direction register 000E16 Port P3 register 000F16 Port P3 direction register 001016 Port P4 register 001116 Port P4 direction register 001216 Serial I/O shift register 001316 Serial I/O control register 001416 A-D conversion register 001516 A-D control register 001616 Timer 1 001716 Timer 2 001816 Timer 3 001916 Timer 123 mode register 001A16 Timer XL 001B16 Timer XH 001C16 Timer YL 001D16 Timer YH 001E16 Timer X mode register 001F16 Timer Y mode register 002016 UART mode register 002116 UART baud rate generator 002216 UART control register 002316 UART status register 002416 UART transmit buffer register 1 002516 UART transmit buffer register 2 002616 UART receive buffer register 1 002716 UART receive buffer register 2 002816 Port P0 pull-up control register 002916 Port P1 pull-up control register 002A16 Port P2 pull-up control register 002B16 Port P3 pull-up control register 002C16 Port P4 pull-up/down control register 002D16 Interrupt polarity selection register 002E16 Watchdog timer register 002F16 Polarity control register CPUM IREQA IREQB IREQC ICONA ICONB ICONC P0 P0D P1 P1D P2 P2D P3 P3D P4 P4D SIO SIOCON AD ADCON T1 T2 T3 T123M TXL TXH TYL TYH TXM TYM UMOD UBRG UCON USTS UTBR1 UTBR2 URBR1 URBR2 PUP0 PUP1 PUP2 PUP3 PUP4 IPOL WDT PCON 003016 CAN transmit control register 003116 CAN bus timing control register 1 003216 CAN bus timing control register 2 003316 CAN acceptance code register 0 003416 CAN acceptance code register 1 003516 CAN acceptance code register 2 003616 CAN acceptance code register 3 003716 CAN acceptance code register 4 003816 CAN acceptance mask register 0 003916 CAN acceptance mask register 1 003A16 CAN acceptance mask register 2 003B16 CAN acceptance mask register 3 003C16 CAN acceptance mask register 4 003D16 CAN receive control register 003E16 CAN transmit abort register 003F16 Reserved 004016 CAN transmit buffer register 0 004116 CAN transmit buffer register 1 004216 CAN transmit buffer register 2 004316 CAN transmit buffer register 3 004416 CAN transmit buffer register 4 004516 CAN transmit buffer register 5 004616 CAN transmit buffer register 6 004716 CAN transmit buffer register 7 004816 CAN transmit buffer register 8 004916 CAN transmit buffer register 9 004A16 CAN transmit buffer register A 004B16 CAN transmit buffer register B 004C16 CAN transmit buffer register C 004D16 CAN transmit buffer register D 004E16 Reserved 004F16 Reserved 005016 CAN receive buffer register 0 005116 CAN receive buffer register 1 005216 CAN receive buffer register 2 005316 CAN receive buffer register 3 005416 CAN receive buffer register 4 005516 CAN receive buffer register 5 005616 CAN receive buffer register 6 005716 CAN receive buffer register 7 005816 CAN receive buffer register 8 005916 CAN receive buffer register 9 005A16 CAN receive buffer register A 005B16 CAN receive buffer register B 005C16 CAN receive buffer register C 005D16 CAN receive buffer register D 005E16 Reserved 005F16 Reserved CTRM CBTCON1 CBTCON2 CAC0 CAC1 CAC2 CAC3 CAC4 CAM0 CAM1 CAM2 CAM3 CAM4 CREC CABORT CTB0 CTB1 CTB2 CTB3 CTB4 CTB5 CTB6 CTB7 CTB8 CTB9 CTBA CTBB CTBC CTBD CRB0 CRB1 CRB2 CRB3 CRB4 CRB5 CRB6 CRB7 CRB8 CRB9 CRBA CRBB CRBC CRBD 3-64 7630 Group User’s Manual APPENDIX 3.12 Pin configuration 3.12 Pin configuration 33 31 30 27 24 32 29 28 26 25 23 P16/PWM P15/CNTR1 P14/CNTR0 P13/TX0 P12/INT1 P11/INT0 P07/AN7 P06/AN6 P05/AN5 P04/AN4 P03/AN3 P17 P20/SIN1 P21/SOUT1 P22/SCLK1 P23/SRDY1 VSS P24/URXD P25/UTXD P26/URTS P27/UCTS P30 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 M37630M4T-XXXFP M37630E4T-XXXFP M37630E4T-XXXFP 18 17 16 15 14 13 12 P02/AN2 P01/AN1 P00/AN0 VREF AVSS VCC XOUT XIN VSS RESET P47/KW7 10 P31/CTX P32/CRX P33 P34 P40/KW0 P41/KW1 P42/KW2 P43/KW3 P44/KW4 P45/KW5 P46/KW6 Package type 44P6N-A 7630 Group User’s Manual 11 4 1 2 5 7 3 6 8 9 3-65 MITSUBISHI SEMICONDUCTORS USER’S MANUAL 7630 Group JAN. Second Edition 1999 Editioned by Committee of editing of Mitsubishi Semiconductor USER’S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©1999 MITSUBISHI ELECTRIC CORPORATION U ser’s Manual 7630 Group © 1999 MITSUBISHI ELECTRIC CORPORATION. New publication, effective Jan. 1999. Specifications subject to change without notice.