Datasheet
80KSW0005
10-Quad
RapidIO® Switch
1 Device Overview
The CPS-10Q (80KSW0005) is a serial RapidIO switch whose functionality is
central to routing packets for distribution among DSPs, processors, FPGAs,
other switches, or any other sRIO-based devices. The CPS-10Q supports serial
RapidIO packet switching (unicast, multicast, and an optional broadcast) from
any of its 16 input ports to any of its 16 output ports.
2 Features
u
Interfaces - sRIO
– 40 bidirectional serial RapidIO (sRIO) lanes v 1.3
– Port Speeds selectable: 3.125Gbps, 2.5Gbps, or 1.25Gbps
– All lanes support short haul or long haul reach for each PHY speed
– Configurable port count to up to 16 ports
– Two enhanced quads can be configured as 4 1x ports or 1 4x ports
– Supports standard 4 levels of priority
– Error handling support: It allows error detection, logging and
response from all major functional blocks on the device.
u
Performance
– 100 Gbps of peak switching bandwidth
– Non-blocking data flow architecture within each sRIO priority
– low latency for all packet length and load condition
– Internal queuing buffer and retransmit buffer
– Standard receiver based physical layer flow control
u
Features
– Configurable for cut-thru and store-and-forward modes
– Device configurable through any of sRIO ports, I2C, or JTAG
– Packet Trace function: It allows copying or filtering packets on a peru
Interfaces - I2C
– Provides I2C port for maintenance and error reporting
– Master or Slave Operation
– Master allows power-on configuration from external ROM
– Master mode configuration with external image compressing and
checksum
–
–
–
–
–
–
–
–
–
–
–
–
port basis. Each port provides the ability to match the first 160 bits of
any packet against up to 4 programmable comparison values to copy
the packet to a programmable output trace port or drop it.
Supports up to 40 simultaneous multicast masks per each port
Support Broadcast
Port Loopback Debug Feature
Software assisted error recovery, supporting hot swap
Ports may be individually turned off to reduce power
PMON counters for monitor and diagnostics per port
Serdes physical diagnostic registers
Embedded PRBS generation and detection with programmable polynomial cover error rate under all conditions
0.13um technology
Low power dissipation
Full JTAG Boundary Scan support (IEEE1149.1 & 1149.6)
Package: FCBGA 676-ball grid array, 27mm x 27mm, 1.0mm ball
pitch
3 Block Diagram
Ln0
Ln39
Ln1
sRIO Q0
Ln2
Standard
(1 port)
Ln3
Serial RapidIO Switch
CPS-10Q
sRIO Q9
Ln38
Enhanced
(1 or 4 ports)
Ln37
Ln4
Ln36
Ln35
Ln5
sRIO Q1
sRIO Q8
Ln34
Ln6
Standard
(1 port)
Standard
(1 port)
Ln33
Ln9
sRIO Q2
sRIO Q7
Ln30
Ln10
Standard
(1 port)
Standard
(1 port)
Ln29
Ln13
sRIO Q3
sRIO Q6
Ln26
Ln14
Standard
(1 port)
Standard
(1 port)
Ln25
Ln7
Ln31
Ln8
Ln11
Maintenance
&
Error
Management
Ln16
Ln17
sRIO Q4
sRIO Q5
Ln18
Enhanced
(1 or 4 ports)
Standard
(1 port)
Ln19
Ln28
Ln27
Ln12
Ln15
Ln32
JTAG
Configuration
Figure 1 Block diagram
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Ln24
Ln23
Ln22
Ln21
Ln20
I2C
January 18, 2011
DSC 5697
CPS-10Q
CPS-10Q Datasheet
4 Device Description
The CPS-10Q is optimized for cost-effective high performance RapidIO switching, typically used in embedded applications. Typical applications
include backplane switching and intensive signal processing where the switch is key to switching on the data path. These applications include wireless
infrastructure base station and RNCs, radar and sonar, and medical imaging. It can serve equally as backplane or linecard switch, supporting up to 16
ports. It is an end-point free (switch) device in an sRIO network.
The CPS-10Q receives packets from up to 16 ports. The device offers full support for normal switching as well as enhanced functions:
1) Normal Switching: All packets are switched in accordance with standard serial RapidIO specifications, with packet destination IDs determining
how the packet is routed.
Three major options exist within this category:
a. Multicast: If a Multicast ID is received, the CPS-10Q performs a multicast as defined in the sRIO multicast registers.
b. Unicast: specified by sRIO.
c. Maintenance packets: As specified by sRIO.
The CPS-10Q supports a peak throughput of 100 Gbps which is the line rate for 10 ports in 4x configuration, each at 10 Gbps (3.125 Gbps minus the
sRIO-defined 8b/10b encoding), and switches dynamically in accordance with the packet headers and priorities.
2) Enhanced functions
Enhanced features are provided for support of system debug. These features which are optional for the user consist of two major functions:
a. Packet Trace: The Packet Trace feature provides at-speed checking of the first 160 bits (header plus a portion of any payload) of every incoming packet against user-defined comparison register values. The trace feature is available on all serial RapidIO ports, each acting independently from one another. If the trace feature is enabled for a given port, every incoming packet is checked for a match against up to 4
comparison registers. In the event of a match, either of two possible user defined actions may take place:
i) not only does the packet route normally through the switch to its appropriate destination port, but this same packet is replicated and sent to
a “trace port.” The trace port itself may be any of the standard serial RapidIO ports. The port used for the trace port is defined by the user
through simple register configuration.
ii) the packet is dropped.
If there is no match, the packets route normally through the switch with no action taken.
The Packet Trace feature can be used during system bring-up and prototyping to identify particular packet types of interest to the user. It might
be used in security applications, where packets must be checked for either correct or incorrect tags in either of the header or payload. Identified (match) packets are then routed to the trace port for receipt by a host processor, which can perform an intervention at the software level.
b. Port Loopback: The CPS-10Q offers internal loopback for each port that may be used for system debug of the high speed sRIO ports. By
enabling loopback on a given port, packets sent to the port’s receiver are immediately looped back at the physical layer to the transmitter bypassing the higher logical or transport layers.
c. Broadcast: Each multicast mask can be configured so that the source port is included among the destination ports of that multicast operation.
The CPS-10Q can be programmed through any one or combination of sRIO, I2C, or JTAG. Note that any sRIO port may be used for programming.
The device can also configure itself on power-up by reading directly from ROM over I2C in master mode.
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CPS-10Q
CPS-10Q Datasheet
5 Applications
Central switch baseband system wireless processing
Baseband System (REC) -RapidIO Based
RF Card (RE)
RF
TDM
Receiver
sRIO
CPRI
80HFC1001
CPRI FIC
80HFC1000
CPRI FIC
sRIO
CPS- 10Q
CPS-10Q
CPS-6Q
DSP
RF Card (RE)
FPGA
DSP
DSP
80KSBR201
RF
TDM
Receiver
Serial Buffer
80HFC1001
CPRI FIC
Figure 1 Application Overview
Note: The CPS-10Q provides direct support for backplane connections using the serial RapidIO standard. The addition of an appropriate bridge (e.g.,
CPRI sRIO) allows for further backplane flexibility, accommodating designs based on a wide range of standards such as CPRI, OBSAI, GbE or
PCIe.
In a macro wireless station, a switch-based raw data combination and distribution architecture is widely adopted. Switch based architecture provides
high flexibility and high resource efficiency. The raw data from the Radio Unit is distributed to one or more processing cards by unicast or multicast.
Aggregating raw data from processing cards to a buffer-less chain can be done by a fast non-blocking switch.
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CPS-10Q
CPS-10Q Datasheet
Media Gateway and general processing
Figure 2 Application Overview
Note: The CPS-10Q provides direct support for backplane connections using the serial RapidIO standard.
A low jitter switch enables fully DSP processing power. Priority support, fast switching, and multicasting will differentiate class of traffic to provide QoS.
6 Functional Overview
The CPS-10Q is optimized for either board-level DSP/ASIC cluster applications or module-level distributed processing application. Up to 16 serial
RapidIO ports fully meet standard v1.3. The physical lanes may be configured to operate at 3.125Gbps, 2.5Gbps or 1.25Gbps. All lanes independently
work in short haul or long haul. The switch has a sustained 80Gbps bandwidth. It is non-blocking within a given sRIO priority.
The CPS-10Q can be programmed through a CPU or a DSP connected to one of the sRIO ports of the device or with a CPU connected to an I2C or
JTAG bus, it can also work along with a I2C configuration memory. This option allows the device work in “remote stand alone” mode.
Each sRIO port provides a packet trace capability. For any packet received by a port, a comparison between the first 160 bits and up to four configurable values can be performed. A match against any of these parameters will result in a copy of the packet and a route of the packet to a configurable
ouput port. This feature can be used as a tactical function to track user data or in a debug environment to test how specific packets are moving
through the platform.
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CPS-10Q
CPS-10Q Datasheet
7 Interfaces Overview
Rext
40
Differential
sRIO Lanes
1.25, 2.5, or
3.125 Gbps
IDT CPS-10Q
RST
REF_CLK
SPD[1:0]
I2C
Interface
400KHz
IRQ
Figure 3 Interface Diagram
sRIO Ports
The sRIO interfaces are the main communication ports on the switch. These ports are compliant with the serial RapidIO v. 1.3 specifications. Please
refer to the serial RapidIO specifications for full detail [2-10].
The CPS-10Q provides 40 differential dual simplex transceivers dedicated to sRIO I/O. In addition to standard quads that act as a single 1x or 4x port,
two enhanced quads can be independently configured to run in various configurations as 4 1x-ports or 1 4x-ports. The device supports a maximum of
16 1x-ports, or 10 4x-ports. Each port can be programmed to run independently at 1.25, 2.5, or 3.125Gbps. Each lane is able to handle long- or shorthaul serial transmission per RIO serial spec.
In the CPS-10Q there are 8 “Standard Quads” which follow the standard sRIO physical interface implementation. These ports either operate in 4xmode or as a single 1x-port. For example Lanes 0 - 3 are programmable into one 4x- or one 1x-port. Per sRIO standard, either the 1st or 3rd lanes in
a given 4x group may be used as a valid link for a 1x port. For example, either lane 0 or lane 2 may be connected in support of a 1x-port.
The CPS-10Q also has a proprietary implementation which we refer to as an “Enhanced Quad” for Quad4 and Quad9. An Enhanced Quad can be
operated in standard sRIO mode like the standard quads. Additionally the Enhanced Quad can be register-configured to run as 4 independent 1xports. In this manner, the user has the flexibility to use one, multiple, or two lanes in 1x-mode. For example, lanes 16 - 19 of the CPS-10Q are
programmable into one 4x- or four 1x-ports. This is unlike the standard sRIO port implementation that, when configured as a 1x-port, renders the
remaining possible connections unused.
I2C Bus
This interface may be used as an alternative to the standard sRIO or JTAG ports to program the switch and to check the status of registers - including
the error reporting registers. It is fully compliant with the I2C specification, it supports master mode and slave mode, also supports both Fast- and
Slow-mode buses [1]. Refer to the “I2C” section for full detail.
JTAG TAP Port
This TAP interface is IEEE1149.1 (JTAG) and 1149.6 (AC Extest) compliant [10, 11]. It may also be used as an alternative to the standard sRIO or I2C
ports to program the switch and to check the status of registers - including the error reporting registers. It has 5 pins. Refer to the JTAG chapter for full
detail.
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CPS-10Q
CPS-10Q Datasheet
Interrupt (IRQ)
An interrupt output is provided in support of Error Management functionality. This output may be used to flag a host processor in the event of error
conditions within the device. Refer to the Error Handling chapter for full detail.
Reset
A single Reset pin is used for full reset of the CPS-10Q, including setting all registers to power-up defaults. Refer to the Reset & Initialization chapter
for full detail.
Clock
The single system clock (REF_CLK+ / -) is a 156.25MHz differential clock.
Rext (Rextn & Rextp)
These pins are used to establish the drive bias on the SerDes output. An external bias resistor is required. The two pins must be connected to one
another with a 12k Ohm resistor. This provides CML driver stability across process and temperature.
SPD[1:0]
Speed Select Pins. These pins define the sRIO port speed at RESET for all ports. The RESET setting may be overridden by subsequent programming
of the QUAD_CTRL register. SPD[1:0] = {00 = 1.25G, 01 = 2.5G, 10 = 3.125G, 11 = RESERVED}. These pins must remain STATICALLY BIASED after
power-up.
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CPS-10Q
CPS-10Q Datasheet
8 Absolute Maximum Ratings(1)
Symbol
Rating
Commercial &
Unit
Industrial
VTERM (VDD3)
VDD3 Terminal Voltage with Respect to GND
-0.5 to 3.6
V
VTERM(2) (VDD3-supplied interfaces)
Input or I/O Terminal Voltage with Respect to GND
-0.3 to VDD3+0.3
V
VTERM (VDD)
VDD Terminal Voltage with Respect to GND
VTERM(2) (VDD-supplied interfaces)
-0.5 to 1.5
V
Input or I/O Terminal Voltage with Respect to GND
-0.3 to VDD+0.3
V
VTERM (VDDS)
VDDS Terminal Voltage with Respect to GND
VTERM(2) (VDDS-supplied interfaces)
-0.5 to 1.5
V
Input or I/O Terminal Voltage with Respect to GNDS
-0.3 to VDDS+0.3
V
VTERM (VDDA)
VDDA Terminal Voltage with Respect to GND
-0.5 to 1.5
V
VTERM(2) (VDDA-supplied interfaces)
Input or I/O Terminal Voltage with Respect to GNDS
-0.3 to VDDA+0.3
V
TBIAS(3)
Temperature Under Bias
-55 to +125
C
TSTG
Storage Temperature
-65 to +150
C
TJN
Junction Temperature
+125
C
IOUT (For VDD3 = 3.3V)
DC Output Current
30
mA
IOUT (For VDD3 = 2.5V)
DC Output Current
30
mA
Table 1 Absolute Maximum Ratings
Notes:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the
voltage on any Input or I/O pin cannot exceed its corresponding supply voltage during power supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions.
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CPS-10Q
CPS-10Q Datasheet
9 Recommended Temperature and Operating Voltage(1)
Grade
Ambient
Ground(2)
Supply Voltage(4)
Temperature
Commercial
0°C to 70°C
GND = 0V
GNDS = 0V
VDD = 1.2 +/- 5%
VDDS = 1.2 +/- 5%
VDD3(3) = 3.3 +/- 5%
or 2.5V +/- 100mV
VDDA = 1.2 +/- 5%
Industrial
-40°C to 85°C
GND = 0V
GNDS = 0V
VDD = 1.2 +/- 5%
VDDS = 1.2 +/- 5%
VDD3(3) = 3.3 +/- 5%
or 2.5V +/- 100mV
VDDA = 1.2 +/- 5%
Table 2 Recommended Temperature and Operating Voltage
Notes:
1. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed its corresponding supply voltage during power supply ramp up. The
device is not sensitive to supply rise and fall times, and thus these are not specified.
2. VDD3, VDDA, and VDDS share a common ground (GNDS). Core supply and ground are VDD and GND respectively.
3. VDD3 may be operated at either 3.3V or 2.5V simply by providing that supply voltage. For those interfaces operating on this supply, this datasheet provides input
and output specifications at each of these voltages.
4. VDDS & VDDA may be tied to a common power plane. VDD (core, digital supply) should have its own supply and plane. A ferrite bead may be used to supply VDDS/
VDDA from VDD. The bead should be chosen to provide a low DC resistance in order to maintain the rail voltage spec. To keep within the specified low VDDA /
VDDS limit, a 0.06 Ohm (DC) resistance is the max allowable. A bead with 10 Ohm impedance provides sufficient AC block while still meeting DC resistance
requirements.
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CPS-10Q
CPS-10Q Datasheet
10 AC Test Conditions
Input Pulse Levels
GND to 3.0V /
GND to 2.4V
Input Rise / Fall Times
2ns
Input Timing Reference Levels
1.5V / 1.25V
Output Reference Levels
1.5V / 1.25V
Output Load
Figures 4
Table 3 AC Test Conditions (VDD3=3.3V / 2.5V): JTAG, I2C, RST
50 Ohm
DATAout
50 Ohm
1.5V / 1.25V
10pF (TESTER)
Figure 4 AC Output Test Load (JTAG)
3.3V / 2.5V
2–10k Ohm
IRQ
400pF (max)
Figure 5 AC Output Test Load (IRQ)
Note: The IRQ pin is an open-drain driver. IDT recommends a weak
pull-up resistor (2-10k Ohm) be placed on this pin to VDD3.
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CPS-10Q
CPS-10Q Datasheet
3.3V / 2.5V
2k Ohm
SDA,
SCL
400pF (max)
Figure 6 AC Output Test Load (I2C)
Note: The SDA and SCL pins are open-drain drivers. Refer to the
Philips I2C specification [1] for appropriate selection of pull-up
resistors for each.
C1
TXP
Internal
To Device
Z0
RXP
R1
Tx
Rx
Vbias
TXN
R2
RXN
Z0
C2
Figure 7 sRIO Lanes Test Load
The characteristic impedance Z0 should be designed for 100 Ohms. An inline capacitor C1 and C2 at each input of the receiver provides AC-coupling
and a DC-block. The IDT recommended and test value is 100nF for each. Thus, any DC bias differential between the two devices on the link is
negated. The differential input resistance at the receiver is designed to be 100 Ohms (per sRIO specification). Thus, R1 and R2 are 50 Ohms each.
Note that VBIAS is the internal bias voltage of the device’s receiver.
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CPS-10Q
CPS-10Q Datasheet
11 Device Performance Figures
11.1 Performance Figures
The following table lists the CPS-10Q’s performance figures. Figures provided here are guaranteed by design and characterization, but are not
production tested.
Description
Min
Typ
Max
Units
Throughput (Peak)
__
__
Comments
100
Gbps
Throughput (Sustained)
__
80
__
Gbps
Value shown is for device configured for 10 4X ports, each running at 3.125Gbps, 276 byte packets at priority 0. Please contact
IDT technical support for figures related to a specific usage case
and traffic conditions.
Per Port throughput (Peak)
__
__
10
Gbps
Value shown is for device configured for each port with 4X
3.125G mode. The sustained throughput is shown in other table
below.
Switch Latency Jitter (70% switch load)(2)
__
60
__-
ns
Latency Jitter for the switch lock is the sum of the Physical layer
jitter plus one maintenance packet of contention delay for a
given output port. Worst case for the physical layer is the jitter
caused by the port sync process. This requires 6 32-bit control
symbols plus 2 cycle times the port rate. The figures shown here
are for priority 2 packets under 70% switch loading with an even
mix of packets of each priority. It assumes that no maintenance
packets contend on the output port.
Soft Reset to Receipt of Valid Packets
__
__
26
us
This includes reset time as well as link establishment.
Hard Reset to Receipt of Valid Packets
__
__
26
us
This includes reset time as well as link establishment.
25
__
2000
cycles(3)
Multicast Map Update Delay
Table 4 80KSW0005 Performance Figures
Notes:
1. Values are guaranteed by characterization, but are not production tested.
2. For those specifications associated with an sRIO transaction, it should be noted that the upper limit to a specification may be dictated by sRIO priority handling. For
example, a maintenance read packet having lower priority may be held off until higher priority packets in queue are serviced. The user should take into consideration
this additional priority-induced delay when examining these specifications. I2C and JTAG configuration register access transactions are always deterministic and
follow these specifications identically.
3. “Cycles” refer to internal core clock cycles which are two times the external reference clock (REF_CLK) frequency = 312.5 MHz.
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CPS-10Q
CPS-10Q Datasheet
11.2 Sustained Per-Port Throughput (Typical)
Pay Load Size
1.25GHz
2.5GHz
3.125GHz
1X
4X
1X
4X
1X
4X
16 Byte
0.70 G
2.33 G
1.38 G
4.42 G
1.93 G
4.67
32 Byte
0.79 G
2.4 G
1.57 G
5.48 G
2.1 G
5.89
64 Byte
0.86 G
2.92 G
1.73 G
6.32 G
2.24 G
7.02 G
128 Byte
0.94 G
3.38 G
1.87 G
6.76 G
2.28 G
8.19 G
256 Byte
0.97 G
3.66 G
1.93 G
7.30 G
2.39 G
8.93 G
Table 5 Sustained Per-Port Throughput (Typical)
Notes:
1. Values are guaranteed by characterization, but are not production tested.
2. Throughput values are for 8bit destination ID packet, Header + Pay Load + CRC. The (Header + CRC) size changes depending on payload size. For payloads less
then 80 Bytes, the (Header + CRC) is 12 bytes. For payloads bigger than 80 Bytes, the (Header + CRC) is 14 bytes.
3. As payload size increases, the physical layer control symbols (sRIO required overhead) become a smaller percentage of the overall per-port throughput figure. The
physical layer symbols include one SoP and one EoP for every packet. There is a status control symbol for every 1024 transmitted code-group as well as synchronization sequences required by sRIO. For two way traffic, packet acknowledgment control symbols will occur between the packets.
11.3 Data Packet Latency in “Store-and-Forward” Mode (Typical)
Pay Load Size
1.25GHz
2.5GHz
3.125GHz
1X
4X
1X
4X
1X
4X
8 Byte
454 ns
328 ns
271 ns
228 ns
240 ns
211 ns
16 Byte
518 ns
348 ns
304 ns
234 ns
266 ns
216 ns
32 Byte
646 ns
380 ns
367 ns
246 ns
316 ns
227 ns
64 Byte
905 ns
441 ns
493 ns
271 ns
419 ns
253 ns
128 Byte
1449 ns
580 ns
770 ns
336 ns
641 ns
307 ns
256 Byte
2473 ns
833 ns
1282 ns
457 ns
1049 ns
409 ns
Multicast Event
Control Symbol
126 ns
115 ns
66 ns
60 ns
55 ns
49 ns
Table 6 Switch Latency Table (Store-and-Forward Mode, Typical)
Notes:
1. Values are guaranteed by characterization, but are not production tested.
2. For those specifications associated with an sRIO transaction, it should be noted that the upper limit to a specification may be dictated by sRIO priority handling. For
example, a maintenance read packet having lower priority may be held off until higher priority packets in queue are serviced. The user should take into consideration this additional priority-induced delay when examining these specifications. I2C and JTAG transactions are always deterministic and follow these specifications
identically.
3. Switch latency is a statistical function, which typically increases with increased traffic loading on the switch. Values shown in Table 6 are typical for single input port
to single output port with matching input and output port rates in “Store-and-Forward” mode, no other switch loading. The switch latency in “Store-and-Forward”
packet forward methodology is also a strong function of port rate. For specific values under other specific application usage scenarios and traffic conditions, please
contact IDT technical support.
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CPS-10Q
CPS-10Q Datasheet
11.4 Data Packet Latency in “Cut-Through” Mode (Typical)
Pay Load Size
1.25GHz
2.5GHz
1X
4X
3.125GHz
1X
4X
1X
4X
8 Byte
369 ns
322 ns
233 ns
217 ns
205 ns
195 ns
16 Byte
366 ns
320 ns
225 ns
217 ns
204 ns
197 ns
32 Byte
354 ns
320 ns
224 ns
218 ns
204 ns
195 ns
64 Byte
351 ns
322 ns
223 ns
220 ns
203 ns
196 ns
128 Byte
351 ns
318 ns
224 ns
218 ns
203 ns
196 ns
256 Byte
351 ns
317 ns
222 ns
216 ns
205 ns
195 ns
Table 7 Switch Latency Table (Cut-Through Mode)
Note:
1. Values shown in Table 7 are typical for single input port to single output port with matching input and output port rates in “Cut-Through” mode, no other switch
loading. For specific values under other specific application usage scenarios and traffic conditions, please contact IDT technical support.
In “Store-and-Forward” mode and “Cut-Through” mode when trace and filter are enabled at the same time, only the latency for packets sending to the
trace port will increase by the time taken to send 20 bytes into the port (20bytes * 1/[port_speed * 0.8]) The latency for other traffic flow will be unaffected.
11.5 Maintenance Packet Latency (Typical)
1.25GHz
1.25GHz
2.5GHz
2.5GHz
3.125GHz
3.125GHz
Mode
1X
4X
1X
4X
1X
4X
Store-and-forward
571 ns
460 ns
395 ns
344 ns
352 ns
315 ns
Cut-Through
566 ns
449 ns
386 ns
334 ns
344 ns
315 ns
Table 8 Maintenance Packet (20 words) Latency
Note:
1. Values are guaranteed by characterization, but are not production tested.
11.6 Doorbell packet latency (Typical)
1.25GHz
1.25GHz
2.5GHz
2.5GHz
3.125GHz
3.125GHz
Mode
1X
4X
1X
4X
1X
4X
Store-and-forward
395 ns
323 ns
246 ns
225 ns
219 ns
208 ns
Cut-Through
378 ns
317 ns
230 ns
221 ns
209 ns
208 ns
Table 9 Doorbell Packet Latency
Note:
1. Values are guaranteed by characterization, but are not production tested.
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CPS-10Q
CPS-10Q Datasheet
12 Power Figures
Typical power draw for the 80KSW0005 is approximately 5.3W total for all ports enabled as 10 4x @ 3.125G under 50% switch load. The following
table provides power figures on a per-block basis. An estimate of the device power figure for a given application usage can be determined by using the
“CPS-10Q Power Calculator” modeling tool.
Description
Typical
Units
Supply
Comments
Serdes 1x @ 1.25G
66, 33
mW
VDDS, VDDA
Analog SerDes power consumption (VDDS and VDDA). This does not
include the sRIO quad power consumption.
SerDes 1x @ 2.5G
78, 36
mW
VDDS, VDDA
Analog SerDes power consumption (VDDS and VDDA). This does not
include the sRIO quad power consumption.
SerDes 1x @ 3.125G
82, 49
mW
VDDS, VDDA
Analog SerDes power consumption (VDDS and VDDA). This does not
include the sRIO quad power consumption.
Serdes 4x @ 1.25G
149, 226
mW
VDDS, VDDA
Analog SerDes power consumption (VDDS and VDDA). This does not
include the sRIO quad power consumption.
SerDes 4x @ 2.5G
178, 82
mW
VDDS, VDDA
Analog SerDes power consumption (VDDS and VDDA). This does not
include the sRIO quad power consumption.
SerDes 4x @ 3.125G
187, 110
mW
VDDS, VDDA
Analog SerDes power consumption (VDDS and VDDA). This does not
include the sRIO quad power consumption.
JTAG Block Enable
100
mW
VDD3
Configuration Register Access only. Max interface speed(10MHz).
I2C Block Enable
86
mW
VDD3
Configuration Register Access only. Max interface speed (400KHz).
Quiescent Power
1700
mW
VDD
Minimum possible operational power draw. All ports disable, I2C and
JTAG signals static.
Quiescent Power
86
mW
VDD3
Minimum possible operational power draw. All ports disable, I2C and
JTAG signals static.
Quiescent Power
75, 47
mW
VDDS, VDDA
Minimum possible operational power draw. All ports disable, I2C and
JTAG signals static.
Reset Power
15
mW
VDD
Peak power during RESET of the device.
Reset Power
32
mW
VDD3
Peak power during RESET of the device.
Reset Power
8, 39
mW
Standby Power @1.25G
2000
mW
VDD
Part powered up, reset, all links up (reset configuration), no traffic
Standby Power @1.25G
86
mW
VDD3
Part powered up, reset, all links up (reset configuration), no traffic
Standby Power @1.25G
1700, 1000
mW
Standby Power @2.5G
2200
mW
VDD
Part powered up, reset, all links up (reset configuration), no traffic
Standby Power @2.5G
86
mW
VDD3
Part powered up, reset, all links up (reset configuration), no traffic
Standby Power @2.5G
2000, 1000
mW
Standby Power @3.125G
2200
mW
VDD
Part powered up, reset, all links up (reset configuration), no traffic
Standby Power @3.125G
86
mW
VDD3
Part powered up, reset, all links up (reset configuration), no traffic
Standby Power @3.125G
2200, 1300
mW
Peak sustained Power
2500
mW
VDD
All sRIO ports enabled at maximum speed, maximum traffic to the switch.
Peak sustained Power
100
mW
VDD3
All sRIO ports enabled at maximum speed, maximum traffic to the switch.
Peak sustained Power
2300, 1500
mW
VDDS, VDDA Peak power during RESET of the device.
VDDS, VDDA Part powered up, reset, all links up (reset configuration), no traffic
VDDS, VDDA Part powered up, reset, all links up (reset configuration), no traffic
VDDS, VDDA Part powered up, reset, all links up (reset configuration), no traffic
VDDS, VDDA All sRIO ports enabled at maximum speed, maximum traffic to the switch
Table 10 Typical Power Figures
Condition: VDD = 1.2V, VDDS = 1.2V, VDDA = 1.2V, VDD3 = 3.3V @ Room temperature 25oC
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CPS-10Q
CPS-10Q Datasheet
Worst power draw for the 80KSW0005 is approximately 7W total. The condition is all ports @ 3.125G under 100% switch load at the max driving
strength and all trace function are enable.
13 I2C-Bus
The CPS-10Q is compliant with the I2C specification [1]. This specification provides all functional detail and electrical specifications associated with the
I2C bus. This includes signaling, addressing, arbitration, AC timing, DC specifications, and other details.
The device supports both master mode and slave mode, it’s selected by MM pin.
The I2C bus is comprised of Serial Data (SDA) and Serial Clock (SCL) pins. It can be used to attach a CPU or a configuration memory. The I2C interface supports Fast/Standard (F/S) mode (400/ 100 kHz).
I2C master mode and slave mode
The CPS-10Q devices support both master mode and slave mode. It’s selected by MM static configuration pin. Refer to the below for signaling and
operation.
I2C Device Address
The device address for the CPS-10Q is fully pin-defined by 10 external pins while in slave mode. This provides full flexibility in defining the slave
address to avoid conflicting with other I2C devices on a given bus. The device can be operated as either a 10-bit addressable device or a 7-bit
addressable device based on another external pin, address select (ADS). If the ADS pin is tied to VDD, then the CPS-10Q operates as a 10-bit
addressable device and the device address will be defined as ID[9:0]. If the ADS pin is tied to GND, then the device operates as a 7-bit addressable
device with the device address defined by ID[6:0]. The addressing mode must be established at power-up and remain static throughout operation.
Dynamic changes will result in undetermined behavior.
Pin
I2C Address Bit (pin_addr)
ID0
0
ID1
1
ID2
2
ID3
3
ID4
4
ID5
5
ID6
6
ID7
7 (don’t care in 7-bit mode)
ID8
8 (don’t care in 7-bit mode)
ID9
9 (don’t care in 7-bit mode)
Table 11 I2C Static Address Selection Pin Configuration
All of the CPS-10Q’s registers are addressable through I2C. These registers are accessed via 22-bit addresses and 32-bit word boundaries though
standard reads and writes. These registers may also be accessed through the sRIO and JTAG interfaces.
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CPS-10Q
CPS-10Q Datasheet
Signaling
Communication with the CPS-10Q on the I2C bus follows these three cases:
1) Suppose a master device wants to send information to the CPS-10Q:
– Master device addresses CPS-10Q (slave)
– Master device (master-transmitter), sends data to CPS-10Q (slave- receiver)
– Master device terminates the transfer
2) If a master device wants to receive information from the CPS-10Q:
– Master device addresses CPS-10Q (slave)
– Master device (master-receiver) receives data from CPS-10Q (slave- transmitter)
– Master device terminates the transfer.
3) If CPS-10Q polls configuration image from external memory
– CPS-10Q addresses the memory.
– Memory transmits the data.
– CPS-10Q gets the data.
All signaling is fully compliant with I2C. Full detail of signaling can be found in the Philips I2C specification [1]. Standard signaling and timing
waveforms are shown below.
Interfacing to Standard-, Fast-, and Hs-mode Devices
The CPS-10Q supports Fast / Standard (F/S) modes of operation. Per I2C specification, in mixed speed communication the CPS-10Q supports Hsand Fast-mode devices at 400 kbit/s, and Standard-mode devices at 100 kbit/s. Please refer to the I2C specification for detail on speed negotiation on
a mixed speed bus.
CPS-10Q-Specific Memory Access (Slave mode)
There is a CPS-10Q-specific I2C memory access implementation. This implementation is fully I2C compliant. It requires the memory address to be
explicitly specified during writes. This provides directed memory accesses through the I2C bus. Subsequent reads always begin at the address specified during the last write.
The write procedure requires the 3-Bytes (22-bits) of memory address to be provided following the device address. Thus, the following are required:
device address – one or two bytes depending on 10-bit / 7-bit addressing, memory address – 3 bytes yielding 22-bits of memory address, and a 32-bit
data payload – 4 byte words. To remain consistent with sRIO standard maintenance packet memory address convention, the I2C memory address
provided must be the 22MSBs. Since I2C writes to memory apply to double words (32-bits), the 2 LSBs are DON’T CARE as the LSBs correspond to
word and byte pointers.
The read procedure has the memory address section of the transfer removed. Thus, to perform a read, the proper access would be to perform a write
operation and issue a repeated start after the acknowledge bit following the third byte of memory address. Then, the master would issue a read
command selecting the CPS-10Q through the standard device address procedure with the R/W bit high. Note that in 10-bit device address mode
(ADS=1), only the two MSBs need be provided during this read. Data from the previously loaded address would immediately follow the device address
protocol. It is possible to issue a stop or repeated start anytime during the write data payload procedure, but must be before the final acknowledge (i.e.
canceling the write before the actual write operation is completed and performed). Also, the master would be allowed to access other devices attached
to the I2C bus before returning to select the CPS-10Q for the subsequent read operation from the loaded address.
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CPS-10Q
CPS-10Q Datasheet
Read/Write Figures
R=1 | W=0
0
27
18
9
36
45
A
DATA
A
DATA
A
DATA
START
Device
Address [7:0]
ACK
Memory
Address [23:18]
ACK
Memory
Address [17:10]
ACK
Memory
Address [9:2]
Device
Address [9:8]
DATA
A
DATA
A
DATA
A
DATA
82
_
AA
P
Input Data
[31:24]
ACK
Input Data
[23:16]
ACK
Input Data
[15:8]
ACK
Input Data
[7:0]
STOP
ACK
54
63
72
A
ACK
SLAVE ADDR
ACK
R/W
S 1 1 1 1 0 S A 0 A
Figure 8 Write protocol with 10-bit Slave Address (ADS =1).
I2C writes to memory align on 32-bit word boundaries, thus the 24 address MSBs must be provided while the 2 LSB’s associated with word and byte
pointers are DON’T CARE and are therefore not transmitted.
R=1 | W=0
0
18
9
27
36
45
SLAVE ADDR
A
DATA
A
DATA
A
DATA
A
START
Device
Address [7:0]
ACK
Memory
Address [23:18]
ACK
Memory
Address [17:10]
ACK
Memory
Address [9:2]
ACK
Device
Address [9:8]
ACK
R/W
S 1 1 1 1 0 S A 0 A
R=1 | W=0
A
DATA
A
DATA
A
DATA
Output Data
[31:24]
Output Data
[23:16]
Output Data
[15:8]
ACK
Output Data
[7:0]
STOP
NACK
ACK
R/W
START
repeated
Device
Address [9:8]
DATA
ACK
Sr 1 1 1 1 0 S A 1 A
92
_ _
P
A A
ACK
55
64
73
82
Figure 9 Read Protocol with 10-bit Slave Address (ADS=1)
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CPS-10Q
CPS-10Q Datasheet
R=1 | W=0
0
9
18
27
36
SLAVE ADDR
0 A
DATA
A
DATA
A
DATA
START
Device
Address [6:0]
ACK
R/W
Memory
Address [23:18]
ACK
Memory
Address [17:10]
ACK
Memory
Address [9:2]
DATA
A
DATA
A
DATA
A
DATA
73
_
A A
P
Input Data
[31:24]
ACK
Input Data
[23:16]
ACK
Input Data
[15:8]
ACK
Input Data
[7:0]
STOP
ACK
45
A
54
ACK
S
63
Figure 10 Write protocol with 7-bit Slave Address (ADS=0).
I2C writes to memory align on 32-bit word boundaries, thus the 24 address MSBs must be provided while the 2 LSB’s associated with word and byte
pointers are DON’T CARE and are therefore not transmitted.
R=1 | W=0
0
18
9
27
36
S
SLAVE ADDR
0 A
DATA
A
DATA
A
DATA
A
START
Device
Address [6:0]
ACK
R/W
Memory
Address [23:18]
ACK
Memory
Address [17:10]
ACK
Memory
Address [9:2]
ACK
R=1 | W=0
DATA
A
DATA
A
DATA
A
DATA
Output Data
[31:24]
Output Data
[23:16]
ACK
Output Data
[15:8]
ACK
Output Data
[7:0]
STOP
NACK
START
repeated
Device
Address [6:0]
1 A
ACK
Sr SLAVE ADDR
83
_ _
P
A A
ACK
R/W
46
55
64
73
Figure 11 Read protocol with 7-bit Slave Address (ADS=0)
CPS-10Q Configuration and Image (Master mode)
There is both a power up master and a command master mode. If powered up in master mode, the CPS-10Q polls configuration image from external
memory after the device reset sequence has completed. Once the device has completed its configuration sequence, it will revert to slave mode.
Through a config register write, the device can be commanded to enter master mode, which provides more configuration sequence flexibility. Refer to
“CPS-10Q User Manual” for details.
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CPS-10Q
CPS-10Q Datasheet
I2C DC Electrical Specifications
Note that the ADS and ID pins will all run off the core (1.2V) power supply, and these pins are required to be fixed during operation. Thus, these pins
must be statically tied to the 1.2V supply or GND.
Tables 12 through 14 below list the SDA and SCL electrical specifications for F/S-mode I2C devices.
At recommended operating conditions with VDD3 = 3.3V ± 5%
Parameter
Symbol
Minimum
Maximum
Unit
Input high voltage level
VIH
0.7 x VDD3
VDD3 (MAX)+ 0.5
V
Input low voltage level
VIL
-0.5
0.3 x VDD3
V
Hysteresis of Schmitt trigger inputs:
Vhys
0.05 x VDD3
-
Low level output voltage
VOL
0
0.4
V
Output fall time from VIH(MIN) to VIL(MAX) with a bus
capacitance from 10pF to 400pF
tOF
20 + 0.1 x Cb
250
ns
Pulse width of spikes which must be suppressed by
the input filter
tSP
0
50
ns
Input current each I/O pin (input voltage is between
0.1 x VDD3 and 0.9 x VDD3 (MAX) )
II
-10
10
uA
Capacitance for each I/O pin
CI
-
10
pF
Table 12
I2C SDA & SCL DC Electrical Specifications
At recommended operating conditions with VDD3 = 2.5V ± 100mV
Parameter
Symbol
Minimum
Maximum
Unit
Input high voltage level
VIH
0.7 x VDD3
VDD3 (MAX)+ 0.1
V
Input low voltage level
VIL
-0.5
0.3 x VDD3
V
Hysteresis of Schmitt trigger inputs:
Vhys
0.05 x VDD3
-
-
Low level output voltage
VOL
0
0.4
V
Output fall time from VIH(MIN) to VIL(MAX) with a bus
capacitance from 10pF to 400pF
tOF
20 + 0.1 x Cb
250
ns
Pulse width of spikes which must be suppressed by
the input filter
tSP
0
50
ns
Input current each I/O pin (input voltage is between
0.1 x VDD3 and 0.9 x VDD3 (MAX) )
II
-10
10
uA
Capacitance for each I/O pin
CI
-
10
pF
Table 13
I2
C SDA & SCL DC Electrical Specifications
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CPS-10Q
CPS-10Q Datasheet
I2C AC Electrical Specifications
Signal
Symbol
Reference
Edge
Standard
Mode
Fast
Mode
Unit
Min Max Min Max
I2C(1,4)
SCL
fSCL
none
100
0
400
kHz
tHD;STA
4.0
—
0.6
—
us
tR
—
1000
—
300
us
—
300
—
300
us
250
—
100
—
us
tF
SDA(2,3)
0
tSV;DAT
SCL rising
tHD;DAT
0
3.45
0
0.9
us
tR
—
1000
10
300
us
tF
Start or repeated start
condition
tSU;STA
tSU;STO
Stop condition
tSU;STO
—
300
10
300
us
SDA falling
4.7
—
0.6
—
us
4.0
—
0.6
—
us
SDA rising
4.0
—
0.6
—
us
Bus free time between a
stop and start condition
tBUF
4.7
—
1.3
—
us
Capacitive load for each
bus line
CB
—
400
—
400
pF
Table 14 Specifications of the SDA and SCL Bus Lines for F/S-mode I2C -bus Devices
Notes:
1. For more information, see the I 2C-Bus specification by Philips Semiconductor [1].
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling
edge of SCL.
3. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT > 250 ns must then be met. This will automatically be the
case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line tRMAX + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released.
I2C Timing Waveforms
tBUF
SDA
tLOW
tHD;STA
tHIGH
tHD;DAT
tSU;STA
tSU;DAT
tHD;STA
tSU;STO
SCL
Figure 12 I2C Timing Waveforms
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CPS-10Q
CPS-10Q Datasheet
14 Interrupt (IRQ) Electrical Specifications
At recommended operating conditions with VDD3 = 3.3V ± 5%
Symbol
Min
Max
Unit
Output low voltage (IOL = 4mA, VDD3 = Min.)
VOL
0
0.4
V
Output fall time from VIH(min) to VIL(max) with a bus
capacitance from 10pF to 400pF
tOF
-
25
ns
Input current each I/O pin (input voltage is between
0.1 x VDD3 and 0.9 x VDD3 (max))
II
-10
10
uA
Capacitance for IRQ_N
CI
-
10
pF
Parameter
Table 15 IRQ Electrical Specifications (VDD3 = 3.3V ± 5%)
At recommended operating conditions with VDD3 = 2.5V ± 100mV
Symbol
Min
Max
Unit
Output low voltage (IOL = 2mA, VDD3 = Min.)
VOL
0
0.4
V
Output fall time from VIH(min) to VIL(max) with a bus
capacitance from 10pF to 400pF
tOF
-
25
ns
Input current each I/O pin (input voltage is between
0.1 x VDD3 and 0.9 x VDD3 (max))
II
-10
10
uA
Capacitance for IRQ_N
CI
-
10
pF
Parameter
Table 16 IRQ Electrical Specifications (VDD3 = 2.5V ± 100mV)
Figure 13 IRQ Timing Diagram
The IRQ pin is an open-drain driver. IDT recommends a weak pull-up resistor (2-10k Ohm) be placed on this pin to VDD3. The IRQ pin goes active low
when any special error filter error flag is set, and is cleared when all error flags are reset. Please refer to the device user’s manual for full detail.
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CPS-10Q
CPS-10Q Datasheet
15 Serial RapidIO Ports
Overview
The CPS-10Q’s SERDES are in full compliance to the RapidIO AC specifications for the LP-Serial physical layer [5]. This section provides those specifications for reference. The electrical specifications cover both single and multiple-lane links. Two transmitters (short run and long run) and a single
receiver are specified for each of three baud rates, 1.25, 2.50, and 3.125 GBaud.
Two transmitter specifications allow for solutions ranging from simple chip-to-chip interconnect to driving two connectors across a backplane. A single
receiver specification is given that will accept signals from both the short run and long run transmitter specifications.
The short run transmitter setting should be used mainly for chip-to-chip connections on either the same printed circuit board or across a single
connector. This covers the case where connections are made to a mezzanine (daughter) card. The minimum swings of the short run specification
reduce the overall power used by the transceivers.
The long run transmitter specifications use larger voltage swings that are capable of driving signals across backplanes. This allows a user to drive
signals across two connectors and a backplane. The CPS-10Q can drive beyond the specification distance of at least 50 cm at all baud rates. Please
use IDT’s Simulation Kit IO models to determine reach and signal quality for a given PCB design.
Signal Definitions
LP-Serial links uses differential signaling. This section defines terms used in the description and specification of differential signals. Differential PeakPeak Voltage of Transmitter or Receiver shows how the signals are defined. The figure shows waveforms for either a transmitter output (TD and TD)
or a receiver input (RD and RD). Each signal swings between A Volts and B Volts where A > B. Using these waveforms, the definitions are as follows:
1. The transmitter output signals and the receiver input signals TD, TD, RD and RD each have a peak-to-peak swing of A - B Volts
2. The differential output signal of the transmitter, VOD, is defined as VTD-VTD.
3.
The differential input signal of the receiver, VID, is defined as VRD-VRD.
4.
5.
6.
The differential output signal of the transmitter and the differential input signal of the receiver each range from A - B to -(A - B) Volts.
The peak value of the differential transmitter output signal and the differential receiver input signal is A - B Volts
The peak-to-peak value of the differential transmitter output signal and the differential receiver input signal is 2 * (A - B) Volts
TD or RD
A Volts
TD or RD
B Volts
Differential Peak-Peak = 2 * (A – B)
Figure 14 Differential Peak-Peak Voltage of Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common mode voltage of 2.25
V and each of its outputs, TD and TD, has a swing that goes between 2.5V and 2.0V. Using these values, the peak-to-peak voltage swing of the
signals TD and TD is 500 mV p-p. The differential output signal ranges between 500 mV and -500 mV. The peak differential voltage is 500 mV. The
peak-to-peak differential voltage is 1000 mV p-p.
Equalization
With the use of high speed serial links, the interconnect media will cause degradation of the signal at the receiver. Effects such as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss can be large enough to degrade the eye opening at the receiver beyond what is allowed
in the specification. To negate a portion of these effects, equalization can be used. The equalization technique implemented in the CPS-10Q is Preemphasis on the transmitter (under register control).
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CPS-10Q
CPS-10Q Datasheet
Explanatory Note on Transmitter and Receiver Specifications
AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at three baud rates (a total of six cases) are
described.
The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified in Clause 47 of IEEE 802.3ae-2002.
XAUI has similar application goals to serial RapidIO. The goal of this standard is that electrical designs for serial RapidIO can reuse electrical designs
for XAUI, suitably modified for applications at the baud intervals and reaches described herein.
Transmitter Specifications
LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section.
The differential return loss, S11, of the transmitter in each case shall be better than
-10 dB for (Baud Frequency)/10 < Freq(f) < 625 MHz, and
-10 dB + 10log(f/625 MHz) dB for 625 MHz
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