Jitter Attenuator & FemtoClock NG Multiplier
®
ICS810N252I-02
DATA SHEET
General Description
Features
The ICS810N252I-02 device uses IDT's fourth generation
FemtoClock® NG technology for optimal high clock frequency and
low phase noise performance, combined with a low power
consumption and high power supply noise rejection. The
ICS810N252I-02 is a PLL based synchronous multiplier that is
optimized for PDH or SONET to Ethernet clock jitter attenuation and
frequency translation.
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•
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Fourth generation FemtoClock® NG technology
•
Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, HCSL
•
Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
•
•
Crystal interface designed for a 27MHz crystal
•
Customized settings for jitter attenuation and reference tracking
using an external loop filter connection
•
FemtoClock NG frequency multiplier provides low jitter, high
frequency output
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•
•
•
Absolute pull range: ±50ppm
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•
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3.3V supply voltage
The ICS810N252I-02 contains two internal frequency multiplication
stages that are cascaded in series. The first stage is a jitter
attenuator, capable of jitter attenuation down to 10Hz using the
external loop filter. The second stage is a FemtoClock NG®
frequency multiplier that provides the low jitter, high frequency
Ethernet output clock that easily meets Gigabit and 10 Gigabit
Ethernet jitter requirements. Pre-divider and output divider
multiplication ratios are selected using device selection control pins.
The multiplication ratios are optimized to support most common
clock rates used in PDH, SONET and Ethernet applications. The
device requires the use of an external, inexpensive fundamental
mode 27MHz crystal. The device is packaged in a space-saving
32-VFQFN package and supports industrial temperature range.
CLK1
nCLK1
VDD
nCLK0
CLK0
XTAL_IN
XTAL_OUT
VDDX
Pin Assignment
Two single-ended LVCMOS/LVTTL outputs
Each output supports independent frequency selection at 25MHz,
125MHz, 156.25MHz and 312.5MHz
Attenuates the phase jitter of the input clock by using a low-cost
fundamental mode crystal
Power supply noise ratio (PSNR): -85dB
FemtoClock NG VCO frequency: 625MHz
RMS phase jitter @ 125MHz, using a 27MHz crystal
(12kHz – 20MHz): 0.67ps (typical)
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
32 31 30 29 28 27 26 25
LF1
1
24
LF0
2
23 nc
GND
ISET 3
22
QB
GND 4
21
VDDO
CLK_SEL
5
20 nc
VDD
6
19 QA
RESERVED 7
18
GND
17
ODASEL_0
ODASEL_1
ODBSEL_0
ODBSEL_1
VDD
PDSEL_1
VDDA
10 11 12 13 14 15 16
PDSEL_0
9
PDSEL_2
GND 8
ICS810N252I-02
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm ePad size
K Package
Top View
ICS810N252CKI-02 REVISION A MAY 31, 2013
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©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Block Diagram
27MHz
Pulldown
DIGITAL
VCXO
Xtal
Osc.
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
PD
+
LF
Pulldown
0
Pullup/
Pulldown
÷P
Pulldown
1
Pullup/
Pulldown
Phase
Detector
+
Charge
Pump
ODASEL_[1:0]
÷NA
QA
÷NB
QB
FemtoClockÒ NG
VCO
Fractional
Feedback
Divider
Pulldown
2
2
Pulldown
ODBSEL_[1:0]
A/D Control
Block
÷M
LF1
3
LF0
Pullup
ISET
PDSEL_[2:0]
CP
RSET
RS
CS
ICS810N252CKI-02 REVISION A MAY 31, 2013
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©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
LF1, LF0
Analog
Input/Output
Loop filter connection node pins. LF0 is the output. LF1 is the input.
3
ISET
Analog
Input/Output
Charge pump current setting pin.
4, 8, 18, 24
GND
Power
5
CLK_SEL
Input
6, 12, 27
VDD
Power
7
RESERVED
Reserve
9,
10,
11
PDSEL_2,
PDSEL_1,
PDSEL_0
Input
13
VDDA
Power
14,
15
ODBSEL_1,
ODBSEL_0
Input
Pulldown
Frequency select pins for Bank B output. See Table 3B.
LVCMOS/LVTTL interface levels.
16,
17
ODASEL_1,
ODASEL_0
Input
Pulldown
Frequency select pins for Bank A output. See Table 3B.
LVCMOS/LVTTL interface levels.
19
QA
Output
Single-ended Bank A clock output. LVCMOS/LVTTL interface levels.
20, 23
nc
Unused
No connect.
21
VDDO
Power
Output supply pin.
22
QB
Output
Single-ended Bank B clock output. LVCMOS/LVTTL interface levels.
25
nCLK1
Input
Pullup/
Pulldown
Inverting differential clock input. VDD/2 bias voltage when left floating.
26
CLK1
Input
Pulldown
Non-inverting differential clock input.
28
nCLK0
Input
Pullup/
Pulldown
Inverting differential clock input. VDD/2 bias voltage when left floating.
29
CLK0
Input
Pulldown
Non-inverting differential clock input.
30,
31
XTAL_OUT,
XTAL_IN
Input
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
32
VDDX
Power
Power supply pin for crystal oscillator.
Power supply ground.
Pulldown
Input clock select. When HIGH selects CLK1, nCLK1. When LOW, selects
CLK0, nCLK0. LVCMOS / LVTTL interface levels.
Core supply pins.
Reserved pin.
Pullup
Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A.
Analog supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
ICS810N252CKI-02 REVISION A MAY 31, 2013
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©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
CIN
Input Capacitance
CPD
Power Dissipation
Capacitance (per output)
RPULLUP
Minimum
Typical
Maximum
Units
3.5
pF
8
pF
Input Pullup Resistor
51
k:
RPULLDOWN
Input Pulldown Resistor
51
k:
ROUT
Output Impedance
14
:
VDDO = 3.465V
VDDO = 3.3V
Function Tables
Table 3A. Pre-Divider Selection Function Table
Inputs
PDSEL_2
PDSEL_1
PDSEL_0
Pre-Divider Value
0
0
0
1
0
0
1
193
0
1
0
256
0
1
1
1944
1
0
0
2500
1
0
1
7776
1
1
0
12500
1
1
1
15552 (default)
Table 3B. Output Divider Function Table
Inputs
ODxSEL_1
ODxSEL_0
Output Divider Value
0
0
25 (default)
0
1
5
1
0
4
1
1
2
ICS810N252CKI-02 REVISION A MAY 31, 2013
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©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Table 3C. Frequency Function Table
Input
Frequency
(MHz)
Pre-Divider
Value
VCXO Frequency
(MHz)
FemtoClock
Feedback
Divider Value
FemtoClock VCO
Frequency (MHz)
Output Divider
Value
Output Frequency
(MHz)
0.008
1
27
25
625
25
25
0.008
1
27
25
625
5
125
0.008
1
27
25
625
4
156.25
0.008
1
27
25
625
2
312.5
1.544
193
27
25
625
25
25
1.544
193
27
25
625
5
125
1.544
193
27
25
625
4
156.25
1.544
193
27
25
625
2
312.5
2.048
256
27
25
625
25
25
2.048
256
27
25
625
5
125
2.048
256
27
25
625
4
156.25
2.048
256
27
25
625
2
312.5
19.44
1944
27
25
625
25
25
19.44
1944
27
25
625
5
125
19.44
1944
27
25
625
4
156.25
19.44
1944
27
25
625
2
312.5
25
2500
27
25
625
25
25
25
2500
27
25
625
5
125
25
2500
27
25
625
4
156.25
25
2500
27
25
625
2
312.5
77.76
7776
27
25
625
25
25
77.76
7776
27
25
625
5
125
77.76
7776
27
25
625
4
156.25
77.76
7776
27
25
625
2
312.5
125
12500
27
25
625
25
25
125
12500
27
25
625
5
125
125
12500
27
25
625
4
156.25
125
12500
27
25
625
2
312.5
155.52
15552
27
25
625
25
25
155.52
15552
27
25
625
5
125
155.52
15552
27
25
625
4
156.25
155.52
15552
27
25
625
2
312.5
ICS810N252CKI-02 REVISION A MAY 31, 2013
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©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
3.63V
Inputs, VI
-0.5V to VDD+ 0.5V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, TJA
33.1qC/W (0 mps)
Storage Temperature, TSTG
-65qC to 150qC
DC Electrical Characteristics
Table 4A. LVPECL Power Supply DC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
VDD – 0.30
3.3
VDD
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
VDDX
Crystal Oscillator Supply
Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
230
mA
IDDA
Analog Supply Current
VDDA = HIGH
30
mA
IDDO
Output Supply Current
VDDA = LOW, PDSEL[2:0] = 000,
ODxSEL[1:0] = 11
15
mA
Maximum
Units
PLL Mode
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
2
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input
High Current
IIL
Input
Low Current
Test Conditions
Minimum
Typical
CLK_SEL,
ODASEL_[1:0],
ODBSEL_[1:0]
VDD = VIN = 3.465V
150
μA
PDSEL_[2:0]
VDD = VIN = 3.465V
5
μA
CLK_SEL,
ODASEL_[1:0],
ODBSEL_[1:0]
VDD = 3.465V, VIN = 0V
-5
μA
PDSEL_[2:0]
VDD = 3.465, VIN = 0V
-150
μA
2.6
V
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
0.5
V
NOTE 1: Outputs terminated with 50: to VDDO/2. See Parameter Measurement Information section, Output Load Test Circuit diagram.
ICS810N252CKI-02 REVISION A MAY 31, 2013
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©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Table 4C. Differential DC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
V
VCMR
Common Mode Input Voltage; NOTE 1
0.5
VDD – 0.85
V
Maximum
Units
0.008
155.52
MHz
25
312.5
MHz
CLK0, nCLK0,
CLK1, nCLK1
Minimum
Typical
VDD = VIN = 3.465V
Maximum
Units
150
μA
CLK0, CLK1
VDD = 3.465V, VIN = 0V
-5
μA
nCLK0, nCLK1
VDD = 3.465V, VIN = 0V
-150
μA
NOTE 1. Common mode voltage is defined at the crosspoint.
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
fIN
Input Frequency
fOUT
Output Frequency
tjit(Ø)
RMS Phase Jitter, (Random),
NOTE 1
PSNR
Power Supply Rejection Ratio
tsk(o)
Output Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
tLOCK
VCXO & FemtoClock PLL Lock
Time; NOTE 4
Test Conditions
Minimum
Typical
125MHz fOUT, 27MHz crystal,
Integration Range: 12kHz – 20MHz
0.668
0.762
ps
156.25MHz fOUT, 27MHz crystal,
Integration Range: 12kHz – 20MHz
0.684
0.797
ps
312.5MHz fOUT, 27MHz crystal,
Integration Range: 12kHz – 20MHz
0.643
0.730
ps
VPP = 50mV Sine Wave, Integration
Range: 10kHz – 10MHz
-85
dB
70
ps
20% to 80%
200
550
ps
fOUT < 156.25MHz
48
52
%
fOUT = 312.5MHz
45
55
%
Reference Clock Input is ±50ppm from
Nominal Frequency, Bandwidth Low
9
s
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Characterized with outputs at the same frequency using the loop filter components for the 44Hz loop bandwidth.
Refer to Jitter Attenuator Loop Bandwidth Selection Table.
NOTE 1: Outputs switching to same frequency. Refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: Lock Time measured from power-up to stable output frequency, LOW bandwidth setting.
ICS810N252CKI-02 REVISION A MAY 31, 2013
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©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Noise Power
dBc
Hz
Typical Phase Noise at 125MHz
Offset Frequency (Hz)
ICS810N252CKI-02 REVISION A MAY 31, 2013
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©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Parameter Measurement Information
1.65V±5%
1.65V±5%
VDD,
VDDX,
VDDO
VDD
SCOPE
nCLK[0:1]
VDDA
V
Qx
Cross Points
PP
CLK[0:1]
V
CMR
GND
GND
-1.65V±5%
3.3V LVCMOS Output Load Test Circuit
Differential Input Level
Noise Power
Phase Noise Plot
Offset Frequency
f1
f2
RMS Phase Jitter =
1
* Area Under Curve Defined by the Offset Frequency Markers
2* *ƒ
RMS Phase Jitter
VCXO & FemtoClock PLL Lock Time
V
DDO
Qx
2
80%
tR
tF
20%
20%
V
QA, QB
DDO
Qy
80%
2
tsk(o)
LVCMOS Output Rise/Fall Time
Output Skew
V
DDO
2
QA, QB
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
ICS810N252CKI-02 REVISION A MAY 31, 2013
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©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VDD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1in the center of the input voltage swing. For
example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2
value should be adjusted to set V1 at 1.25V. The values below are for
when both the single ended swing and VDD are at the same voltage.
This configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
impedance. For most 50: applications, R3 and R4 can be 100:. The
values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS810N252CKI-02 REVISION A MAY 31, 2013
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©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Differential Clock Input Interface
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 2A, the input termination
applies for IDT open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both differential signals must meet the VPP and
VCMR input requirements. Figures 2A to 2E show interface examples
for the input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
Zo = 50Ω
nCLK
nCLK
Differential
Input
LVHSTL
IDT
LVHSTL Driver
R1
50Ω
R2
50Ω
Differential
Input
LVPECL
R1
50Ω
R2
50Ω
R2
50Ω
Figure 2A. CLK/nCLK Input Driven by an IDT Open
Emitter LVHSTL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
3.3V
3.3V
3.3V
3.3V
Zo = 50Ω
CLK
CLK
R1
100Ω
nCLK
Zo = 50Ω
Differential
Input
LVPECL
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
nCLK
Receiver
LVDS
Figure 2D. CLK/nCLK Input Driven by a
3.3V LVDS Driver
3.3V
3.3V
*R3
CLK
nCLK
HCSL
*R4
Differential
Input
Figure 2E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
ICS810N252CKI-02 REVISION A MAY 31, 2013
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©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVCMOS Outputs
For applications not requiring the use of both differential inputs, it is
recommended that the CLK1 and nCLK1 inputs be used for optimal
performance. CLK0 and nCLK0 can be left floating. Though not
required, but for additional protection, a 1k: resistor can be tied from
CLK0 to ground.
All unused LVCMOS outputs can be left floating. There should be no
trace attached.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k: resistor can be used.
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 3. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
ICS810N252CKI-02 REVISION A MAY 31, 2013
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©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Jitter Attenuator EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality operation of
the Jitter Attenuator. In choosing a crystal, special precaution must
be taken with load capacitance (CL), frequency accuracy and
temperature range.
tuning curve. In addition, the frequency accuracy specification in the
crystal characteristics table are used to calculate the APR (Absolute
Pull Range). It is recommended that the crystal CL is not to exceed
the value stated in the Crystal Parameter Table because it can lead
to a reduced APR.
LF0
LF1
ISET
The crystal’s CL characteristic determines its resonating frequency
and is closely related to the center tuning of the crystal. The total
external capacitance (CEXTERNAL) seen by the crystal when installed
on a PCB is the sum of the stray board capacitance, IC package lead
capacitance, internal device capacitance and any installed tuning
capacitors (CTUNE). The recommended CLin the Crystal Parameter
Table balances the tuning range by centering the tuning curve for a
typical PCB. If the crystal CL is greater than the total external
capacitance (CL > CEXTERNAL), the crystal will oscillate at a higher
frequency than the specification. If the crystal CL is lower than the
total external capacitance (CL < CEXTERNAL), the crystal will oscillate
at a lower frequency than the specification. Mismatches between CL
and CEXTERNAL require adjustments in CTUNE in order to center the
RS
CP
RSET
CS
XTAL_IN
CTUNE
27MHz
XTAL_OUT
CTUNE
Crystal Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Mode of Oscillation
fN
Frequency
fT
Frequency Tolerance
fS
Frequency Stability
Maximum
Units
Fundamental
27
Operating Temperature Range
MHz
-40
±20
ppm
±20
ppm
+85
0C
CL
Load Capacitance
10
pF
CO
Shunt Capacitance
4
pF
ESR
Equivalent Series Resistance
:
40
Drive Level
Aging @ 25 0C
First Year
1
mW
±3
ppm
Jitter Attenuator Characteristics Table
The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS,CP
and RSET values for recommended high, mid and low loop bandwidth
configurations. The device has been characterized using these
parameters. In addition, the digital VCXO gain (KVCXO) has been
provided for additional loop filter requirements.
Symbol
Parameter
Typical
Units
kVCXO
VCXO Gain
2.78
kHz/V
Jitter Attenuator Loop Bandwidth Selection Table (2nd Order Loop Filter)
Bandwidth
Crystal Frequency
RS (k:)
CS (μF)
CP (μF)
R3 (k:)
C3 (μF)
RSET (k:)
15Hz (Low)
27MHz
215
10
0.022
0
DEPOP
2.74
30Hz (Mid)
27MHz
432
2.2
0.0047
0
DEPOP
2.74
60Hz (High)
27MHz
470
1
0.0022
0
DEPOP
1.5
NOTE: See Application Schematic to identify loop filter components RS, CS, CP, R3, C3 and RSET.
ICS810N252CKI-02 REVISION A MAY 31, 2013
13
©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
For applications in which there is substantial low frequency jitter in
the input reference and the phase detector frequency of 8kHz or
10kHz lies in or near a jitter mask, a three pole filter is recommended.
Suggested part values are in the table below. Note that the option of
a three pole filter can be left open by laying out the three pole filter
but setting R3 to 0: and not populating C3. Refer to the application
schematic for a specific example.
Jitter Attenuator Loop Bandwidth Selection Table (3rd Order Loop Filter)
Bandwidth
Crystal Frequency
RS (k:)
CS (μF)
CP (μF)
R3 (k:)
C3 (μF)
RSET (k:)
15Hz (Low)
27MHz
196
10
0.022
82.5
0.010
2.74
30Hz (Mid)
27MHz
392
2.2
0.0047
165
0.0022
2.74
60Hz (High)
27MHz
432
1
0.0022
182
0.001
1.5
NOTE: See Application Schematic to identify loop filter components RS, CS, CP, R3, C3 and RSET.
The crystal and external loop filter components should be kept as
close as possible to the device. Loop filter and crystal traces should
be kept short and separated from each other. Other signal traces
ICS810N252CKI-02 REVISION A MAY 31, 2013
should be kept separate and not run underneath the device, loop filter
or crystal components.
14
©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Schematic Example
Figure 4 shows an example of the ICS810N252I-02 application
schematic. In this example, the device is operated at VDD= VDDA =
VDDX = VDDO = 3.3V. The inputs are driven by a 3.3V LVPECL driver
and an LVDS driver.
In order to achieve the best possible filtering, it is highly
recommended that the 0.1uF capacitors on the device side of the
ferrite beads be placed on the device side of the PCB as close to the
power pins as possible. This is represented by the placement of
these capacitors in the schematic. If space is limited, the ferrite
beads, 10uF and 0.1uF capacitor connected to 3.3V can be placed
on the opposite side of the PCB. If space permits, place all filter
components on the device side of the board.
A three pole loop filter is used for the greater reduction of 8kHz or
10kHz phase detector spurs relative to that afforded by a two pole
loop filter. It is recommended that the loop filter components be laid
out for the 3-pole option, which will also allow a 2-pole filter to be used
The loop filter components are to be laid out on the ICS810N252I-02
side of the PCB directly adjacent to the LF0 and LF1 pins.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS810N252I-02 provides
separate VDD, VDDA, VDDX and VDDO power supplies for each jitter
attenuator to isolate any high switching noise from coupling into the
internal PLLs.
ICS810N252CKI-02 REVISION A MAY 31, 2013
15
©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Logic Control Input Examples
Set Logic
Input to '1'
VD D
VD D
Set Logic
Input to '0'
VD D
3. 3V
R 25 10
RU1
1K
RU2
N ot Ins t al l
F B1
2
VD D A
C 45
10uF
C8
1
BLM18B B221S N 1
C7
0. 1uF
10u F
To Logic
Input
pins
R 26 10
To Logic
Input
pins
RD1
N ot Ins t al l
VD D X
C 47
10uF
RD2
1K
3. 3V
F B2
VD D O
2
C 10
1
BLM18B B221S N 1
C9
0. 1uF
10u F
U1
C1 a nd C2 Va lues s et b y cen te r
freq uen cy tune p roce dur e
PD SE L_2
PD SE L_1
PD SE L_0
9
10
11
ODA SEL_1
ODA SEL_0
16
17
ODB SEL_1
ODB SEL_0
14
15
X1
C1
TU N E
27MH z ( 10pf )
C2
TU N E
C LK _S EL
5
31
30
Zo = 50 O hm
PD SE L_ 2
PD SE L_ 1
PD SE L_ 0
ODA SEL_1
ODA SEL_0
ODB SEL_1
ODB SEL_0
VD D
VD D
VD D
VD D A
V DD X
VD D O
R 33
29
28
100
VD D
V DD
VD D
13
32
21
VD D A
V DD X
VD D O
C 12
0. 1 uF
C 17
0.1uF
C LK _S EL
XTA L_I N
XTA L_OU T
R1
QA
Zo = 50 O hm
6
12
27
19
C 15
0.1uF
C 46
0. 1uF
C 30
0. 1uF
C 14
0. 1uF
Place each 0.1uF bypass
cap directly adjacent
to it's corresponding
VDD, VDDA, VDDX or VDDO
pin.
36
C LK 0
nC LK0
R2
LV D S Dr iv er
QB
22
Z o = 50
36
Zo = 50 O hm
R 8 50
C LK 1
nC LK1
nc
nc
nc
R 4 50
R5
50
2
3
LV C MOS R ec eiv er
7
23
20
Z o = 50
LF 0
IS ET
4
8
18
24
LF 1
LF 1
GN D
GN D
GN D
GN D
1
PEC L D riv er
ePAD
Zo = 50 O hm
LV C MOS R ec eiv er
33
26
25
LF 0
R 3 165k
C3
2. 2nF
Cp
4. 7nF
Rs
392k
R set
2.74K
Cs
2. 2uF
Loop filt er and Rset - Mid LBW Set ting
Figure 4. ICS810N252I-02 Application Schematic.
ICS810N252CKI-02 REVISION A MAY 31, 2013
16
©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS810N252I-02.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS810N252I-02 is the sum of the core power plus the power dissipation due to the load. The following is
the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
Core Output Power Dissipation
•
Power (core)MAX = VDD_MAX * (IDD + IDDA) = 3.465V *(230mA + 30mA) = 900.9mW
•
Power (output)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 15mA = 51.98mW
LVCMOS Output Power Dissipation
•
Output Impedance ROUT Power Dissipation due to Loading 50: to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50: + ROUT)] = 3.465V / [2 * (50: + 14:)] = 27.07mA
•
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 14: * (27.07mA)2 = 10.26mW per output
Total Power (ROUT) = 10.26mW * 2 = 20.52mW
•
Dynamic Power Dissipation at 312.5MHz
Power (312.5MHz) = CPD * Frequency * (VDDO)2 = 8pF * 312.5MHz * (3.465V)2 = 30.02mW per output
Total Power (312.5MHz) = 30.02mW * 2 = 60.04mW
Total Power
= Power (core)MAX + Power (output)MAX + Power (ROUT) + Total Power (312.5MHz)
= 900.0mW + 51.98mW + 20.52mW + 60.04mW
= 1033.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = TJA * Pd_total + TA
Tj = Junction Temperature
TJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance TJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 33.1°C/W per Table 76 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.033W * 33.1°C/W = 119.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance TJA for 32 Lead VFQFN, Forced Convection
TJA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
ICS810N252CKI-02 REVISION A MAY 31, 2013
0
1
3
33.1°C/W
28.1°C/W
25.4°C/W
17
©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Reliability Information
Table 7. TJA vs. Air Flow Table for a 32 Lead VFQFN
TJA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
3
33.1°C/W
28.1°C/W
25.4°C/W
Transistor Count
The transistor count for ICS810N252I-02 is: 44,740
ICS810N252CKI-02 REVISION A MAY 31, 2013
18
©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
A3
N
L
N
Anvil
Anvil
Singulation
Singula tion
e (Ty p.)
2 If N & N
1
are Even
2
OR
E2
(N -1)x e
(Re f.)
E2
2
To p View
b
A
(Ref.)
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
e
N &N
Odd
0. 08
C
Bottom View w/Type A ID
D2
C
Bottom View w/Type C ID
2
1
2
1
CHAMFER
4
Th er mal
Ba se
D2
2
N N-1
RADIUS
4
N N-1
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
Table 8. Package Dimensions
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pin out are shown on the front page. The
package dimensions are in Table 8.
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.25
0.30
8
ND & NE
D&E
5.00 Basic
D2 & E2
3.0
3.3
e
0.50 Basic
L
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
ICS810N252CKI-02 REVISION A MAY 31, 2013
19
©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Ordering Information
Table 9. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
810N252CKI-02LF
ICS252CI02L
“Lead-Free” 32 Lead VFQFN
Tray
-40°C to 85°C
810N252CKI-02LFT
ICS252CI02L
“Lead-Free” 32 Lead VFQFN
Tape & Reel
-40°C to 85°C
ICS810N252CKI-02 REVISION A MAY 31, 2013
20
©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
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IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
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