Jitter Attenuator & FemtoClock®
Multiplier
ICS813252I-02
OBSOLETE
DATA SHEET
GENERAL DESCRIPTION
FEATURES
The ICS813252I-02 is a PLL based synchronous multiplier that is
optimized for PDH or SONET to Ethernet clock jitter attenuation
and frequency translation. The device contains two internal
frequency multiplication stages that are cascaded in series. The first
stage is a VCXO PLL that is optimized to provide reference clock
jitter attenuation. The second stage is a FemtoClock® frequency
multiplier that provides the low jitter, high frequency Ethernet
output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter
requirements. Pre-divider and output divider multiplication ratios
are selected using device selection control pins. The multiplication
ratios are optimized to support most common clock rates used in
PDH, SONET and Ethernet applications. The VCXO requires the
use of an external, inexpensive pullable crystal. The VCXO uses
external passive loop filter components which allows configuration
of the PLL loop bandwidth and damping characteristics. The
device is packaged in a space-saving 32-VFQFN package and
supports industrial temperature range.
• Two LVPECL outputs
Each output supports independent frequency selection at
25MHz, 125MHz, 156.25MHz and 312.5MHz
• Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
• Attenuates the phase jitter of the input clock by using a lowcost pullable fundamental mode VCXO crystal
• VCXO PLL bandwidth can be optimized for jitter attenuation
and reference tracking using external loop filter connection
• FemtoClock frequency multiplier provides low jitter, high frequency output
• Absolute pull range: 50ppm
• FemtoClock VCO frequency: 625MHz
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(10kHz – 20MHz): 1.3ps (maximum)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
PIN ASSIGNMENT
• Available in lead-free (RoHS 6) package
nCLK1
VCC
CLK1
CLK0
nCLK0
VCCX
XTAL_IN
XTAL_OUT
• For functional replacement device use 813N252CKI-02LF
32 31 30 29 28 27 26 25
LF1
1
24
VEE
LF0
2
23
nQB
ISET
3
22
QB
VEE
4
21
VCCO
CLK_SEL
5
20
nQA
VCC
6
19
QA
RESERVED
7
18
VEE
VEE
8
17
ODASEL_0
ICS813252I-02
ODASEL_1
ODBSEL_0
ODBSEL_1
VCC
VCCA
PDSEL_0
PDSEL_1
PDSEL_2
9 10 11 12 13 14 15 16
32-Lead VFQFN
5mm x 5mm x 0.925 package body
K Package
Top View
ICS813252CKI-02 REVISION A AUGUST 4, 2016
1
©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
XTAL_IN
LF1
LF0
ISET
Loop
Filter
XTAL_OUT
BLOCK DIAGRAM
25MHz
Output Divider
PDSEL_[2:0]
Pullup
CLK0
0
nCLK0
CLK1
1
nCLK1
CLK_SEL
Pulldown
VCXO Input
Pre-Divider
000 = 1
001 = 193
010 = 256
011 = 2430
100 = 3125
101 = 9720
110 = 15625
111 = 19440
00 = 25 (default)
01 = 5
10 = 4
11 = 2
Phase
Detector
(default)
2
VCXO
Charge
Pump
VCXO Feedback Divider
÷3125
VCXO Jitter Attenuation PLL
FemtoClock PLL
625MHz
Output Divider
00 = 25 (default)
01 = 5
10 = 4
11 = 2
2
ICS813252CKI-02 REVISION A AUGUST 4, 2016
2
QA
nQA
ODASEL_[1:0]
QB
nQB
ODBSEL_[1:0]
©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2
LF1, LF0
Analog Input/
Output
Loop filter connection node pins.
LF0 is the output. LF1 is the input.
3
ISET
Analog Input/
Output
Charge pump current setting pin.
4, 8, 18, 24
VEE
Power
5
CLK_SEL
Input
6, 12, 27
VCC
Power
7
RESERVED
Reserved
9,
10,
11
PDSEL_2,
PDSEL_1,
PDSEL_0
Input
13
VCCA
Power
14,
15
ODBSEL_1,
ODBSEL_0
Input
Pulldown
Frequency select pins for Bank B output. See Table 3B. LVCMOS/LVTTL interface levels.
16,
17
ODASEL_1,
ODASEL_0
Input
Pulldown
Frequency select pins for Bank A output. See Table 3B. LVCMOS/LVTTL interface levels.
19, 20
QA, nQA
Output
Differential Bank A clock outputs. LVPECL interface levels.
21
VCCO
Power
Output power supply pin.
22, 23
QB, nQB
Output
Differential Bank B clock outputs. LVPECL interface levels.
25
nCLK1
Input
Pullup/
Inverting differential clock input. VCC/2 bias voltage when left floating.
Pulldown
26
CLK1
Input
Pulldown Non-inverting differential clock input.
28
nCLK0
Input
Pullup/
Inverting differential clock input. VCC/2 bias voltage when left floating.
Pulldown
29
CLK0
Input
Pulldown Non-inverting differential clock input.
30,
31
XTAL_OUT,
XTAL_IN
Input
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
32
VCCX
Power
Power supply pin for VCXO charge pump.
Negative supply pins.
Pulldown
Input clock select. When HIGH selects CLK1/nCLK1.
When LOW, selects CLK0/nCLK0. LVCMOS/LVTTL interface levels.
Core power supply pins.
Reserved pin. Do not connect.
Pullup
Pre-divider select pins. LVCMOS/LVTTL interface levels.
See Table 3A.
Analog supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
C
Input Capacitance
4
pF
R
Input Pullup Resistor
51
kΩ
R
Input Pulldown Resistor
51
kΩ
IN
PULLUP
PULLDOWN
ICS813252CKI-02 REVISION A AUGUST 4, 2016
Test Conditions
3
Minimum
Typical
Maximum
Units
©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
TABLE 3A. PRE-DIVIDER FUNCTION TABLE
Inputs
TABLE 3B. OUTPUT DIVIDER FUNCTION TABLE
Inputs
Pre-Divider Value
Output Divider Value
ODxSEL_1
ODxSEL_0
1
0
0
25 (default)
1
193
0
1
5
1
0
256
1
0
4
0
1
1
2430
1
1
2
1
0
0
3125
1
0
1
9720
1
1
0
15625
1
1
1
19440 (default)
PDSEL_2
PDSEL_1
PDSEL_0
0
0
0
0
0
0
ICS813252CKI-02 REVISION A AUGUST 4, 2016
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©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
TABLE 3C. FREQUENCY FUNCTION TABLE
Input
Frequency
(MHz)
Pre-Divider
Value
VCXO
Frequency
(MHz)
FemtoClock Feedback Divider
Value
Femtoclock
VCO Frequency
(MHz)
Output Divider
Value
Output Frequency
(MHz)
0.008
1
25
25
625
25
25
0.008
1
25
25
625
5
125
0.008
1
25
25
625
4
156.25
0.008
1
25
25
625
2
312.5
1.544
193
25
25
625
25
25
1.544
193
25
25
625
5
125
1.544
193
25
25
625
4
156.25
1.544
193
25
25
625
2
312.5
2.048
256
25
25
625
25
25
2.048
256
25
25
625
5
125
2.048
256
25
25
625
4
156.25
2.048
256
25
25
625
2
312.5
19.44
2430
25
25
625
25
25
19.44
2430
25
25
625
5
125
19.44
2430
25
25
625
4
156.25
19.44
2430
25
25
625
2
312.5
25
3125
25
25
625
25
25
25
3125
25
25
625
5
125
25
3125
25
25
625
4
156.25
25
3125
25
25
625
2
312.5
77.76
9720
25
25
625
25
25
77.76
9720
25
25
625
5
125
77.76
9720
25
25
625
4
156.25
77.76
9720
25
25
625
2
312.5
125
15625
25
25
625
25
25
125
15625
25
25
625
5
125
125
15625
25
25
625
4
156.25
125
15625
25
25
625
2
312.5
155.52
19440
25
25
625
25
25
155.52
19440
25
25
625
5
125
155.52
19440
25
25
625
4
156.25
155.52
19440
25
25
625
2
312.5
ICS813252CKI-02 REVISION A AUGUST 4, 2016
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©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
XTAL_IN
Other Inputs
0V to VCC
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
37°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
VCC
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
VCC – 0.15
3.3
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
VCCX
Charge Pump Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
235
mA
ICCA
Analog Supply Current
15
mA
VCC
V
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
VIH
Input High Voltage
2
VCC + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input
High Current
CLK_SEL,
ODASEL_[0:1],
ODBSEL_[0:1]
VCC = VIN = 3.465V
150
µA
PDSEL[0:2]
VCC = VIN = 3.465V
5
µA
Input
Low Current
CLK_SEL,
ODASEL_[0:1],
ODBSEL_[0:1]
VCC = 3.465V, VIN = 0V
-5
µA
PDSEL[0:2]
VCC = 3.465V, VIN = 0V
-150
µA
IIL
Test Conditions
ICS813252CKI-02 REVISION A AUGUST 4, 2016
Minimum
6
Typical
Maximum Units
©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum
Typical
Maximum
Units
150
µA
CLK0/nCLK0,
CLK1/nCLK1
V = V = 3.465V
CLK0, CLK1
V = 0V, V = 3.465V
-5
µA
nCLK0, nCLK1
V = 0V, V = 3.465V
-150
µA
IN
IN
IN
VPP
Peak-to-Peak Input Voltage; NOTE 1
VCMR
Common Mode Input Voltage; NOTE 1, 2
CC
CC
CC
0.15
1.3
V + 0.5
V - 0.85
EE
V
V
CC
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
Maximum
Units
0.008
155.52
MHz
25
312.5
MHz
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
fIN
Input Frequency
fOUT
Output Frequency
jit(Ø)
RMS Phase Jitter (Random);
NOTE 1
125MHz fOUT, 25MHz crystal Integration Range:
10kHz – 20MHz
1.3
ps
jit(acc)
Accumulated Jitter, RMS;
NOTE 2
125MHz fOUT, 25MHz crystal, 20K
Cycles
10
ps
jit(pk-pk)
Peak-to-Peak Jitter
100K Random Cycles
35
ps
sk(o)
Output Skew; NOTE 2, 3
75
ps
odc
Output Duty Cycle
45
55
%
tR / tF
Output Rise/Fall Time
200
700
ps
tLOCK
PLL Lock Time
175
ms
t
t
t
t
Test Conditions
20% to 80%
Minimum
Typical
NOTE: Characterized with outputs at the same frequency using the loop filter components for the mid loop bandwidth.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
Refer to VCXO-PLL Loop Bandwidth Selection Table.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load condtions.
Measured at the output differential cross points.
ICS813252CKI-02 REVISION A AUGUST 4, 2016
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©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
TYPICAL PHASE NOISE @ 125MHZ
125MHz
Z
H )
(dBc
PHASE NOISE
RMS Phase Jitter (Random)
10kHz to 20MHz = 0.98ps (typical)
OFFSET FREQUENCY (HZ)
ICS813252CKI-02 REVISION A AUGUST 4, 2016
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©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
PARAMETER MEASUREMENT INFORMATION
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PHASE JITTER
OUTPUT SKEW
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
ICS813252CKI-02 REVISION A AUGUST 4, 2016
9
©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS813252I-02
provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCX, VCCA,
and VCCO should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be
used for each pin. Figure 1 illustrates this for a generic VCC pin
and also shows that VCCA requires that an additional 10Ω resistor
along with a 10µF bypass capacitor be connected to the VCCA pin.
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
can be 100Ω. The values of the resistors can be increased to reduce
the loading for slower and weaker LVCMOS driver. When using
single ended signaling, the noise rejection benefits of differential
signaling are reduced. Even though the differential input can handle
full rail LVCMOS signaling, it is recommended that the amplitude
be reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less than
-0.3V and VIH cannot be more than VCC + 0.3V. Though some of the
recommended components might not be used, the pads should be
placed in the layout. They can be utilized for debugging purposes.
The datasheet specifications are characterized and guaranteed by
using a differential signal.
Figure 2 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VCC/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located
as close to the input pin as possible. The ratio of R1 and R2 might
need to be adjusted to position the VREF in the center of the input
voltage swing. For example, if the input clock swing is 2.5V and VCC
= 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V.
The values below are for when both the single-ended swing and VDD
are at the same voltage. This configuration requires that the sum of
the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the input will attenuate the signal in half. This can be
done in one of two ways. First, R3 and R4 in parallel should equal the
transmission line impedance. For most 50 applications, R3 and R4
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
ICS813252CKI-02 REVISION A AUGUST 4, 2016
10
©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 3A to 3F show interface examples
for the CLK/nCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. Please
consult with the vendor of the driver component to confirm the
driver termination requirements. For example in Figure 3A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 3A. CLK/nCLK INPUT DRIVEN BY AN
IDT OPEN EMITTER LVHSTL DRIVER
FIGURE 3B. CLK/nCLK INPUT DRIVEN BY A
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
Zo = 50 Ohm
Zo = 50 Ohm
LVDS_Driv er
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
nCLK
Receiv er
Zo = 50 Ohm
R2
84
FIGURE 3C. CLK/nCLK INPUT DRIVEN BY A
3.3V LVPECL DRIVER
FIGURE 3D. CLK/nCLK INPUT DRIVEN BY A
3.3V LVDS DRIVER
FIGURE 3E. CLK/nCLK INPUT DRIVEN BY A
3.3V HCSL DRIVER
FIGURE 3F. CLK/nCLK INPUT DRIVEN BY A
2.5V SSTL DRIVER
ICS813252CKI-02 REVISION A AUGUST 4, 2016
11
©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on
the package, as shown in Figure 4. The solderable area on the PCB,
as defined by the solder mask, should be at least the same size/
shape as the exposed pad/slug area on the package to maximize
the thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern.
It is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This
is desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used as a
guideline only. For further information, refer to the Application Note
on the Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadfame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern
must be connected to ground through these vias. The vias act as
“heat pipes”. The number of vias (i.e. “heat pipes”) are application
specific and dependent upon the package power dissipation as well
as electrical conductivity requirements. Thus, thermal and electrical
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CLK/nCLK INPUTS
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
OUTPUTS:
LVPECL OUTPUTS
ICS813252CKI-02 REVISION A AUGUST 4, 2016
12
©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
FIGURE 5A. LVPECL OUTPUT TERMINATION
ICS813252CKI-02 REVISION A AUGUST 4, 2016
R2
84
FIGURE 5B. LVPECL OUTPUT TERMINATION
13
©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
SCHEMATIC EXAMPLE
Figure 6 shows an example of the ICS813252I-02 application
the loop filter components be laid out for the 3-pole option.
schematic. In this example, the device is operated at VCC = VCCX
This will also allow the 2-pole filter to be used.
= VCCO = 3.3V. The decoupling capacitors should be located
as close as possible to the power pin. The input is driven by
a 3.3V LVPECL driver. An optional 3-pole filter can also be
used for additional spur reduction. It is recommended thatVCC
R1
125
R2
125
Zo = 50
CLK1
nCLK1
Zo = 50
R3
84
LVPECL Driv er
VCC = VCCX = VCCO= 3.3V
R4
84
VCC
R5
125
R6
125
Zo = 50
CLK0
nCLK0
Zo = 50
R8
85
R7
84
LVPECL Driv er
3.3V
R10
133
R11
133
Zo = 50 Ohm
QB
+
3-pole loop filter example - (optional)
R9
LF
LF
Rs
200k
Zo = 50 Ohm
-
820k
Cp
0.01uF
Cs
1.0uF
C3
220pF
R13
82.5
XTAL_OUT
R14
82.5
C1
SP
X1
XTAL_IN
VCC
VCC
C2
SP
CLK0
nCLK0
nQB
10
VCCX
C5
0.01u
0.1u
32
31
30
29
28
27
26
25
C6
10u
U1
VCCX
XTAL_IN
XTAL_OUT
CLK0
nCLK0
VCC
CLK1
nCLK1
2-pole loop filter for Mid Bandwidth setting
LF
Cp
0.001uF
Cs
0.1uF
VCC
CLK_SEL
C8
0.1u
1
2
3
4
5
6
7
8
LF1
LF0
ISET
VEE
CLK_SEL
VCC
RESERVED
VEE
VEE
nQB
QB
VCCO
nQA
QA
VEE
ODASEL_0
R15
2.21K
ICS813252I-02
Set Logic
Input to
'1'
RU1
1K
PDSEL_2
PDSEL_1
PDSEL_0
Logic Control Input Examples
VCC
Set Logic
Input to
'0'
VCC
0.1u
C7
ODASEL_0
QA
VCC
VCCA
RD1
Not Install
VCCO
nQA
VCC
RU2
Not Install
To Logic
Input
pins
24
23
22
21
20
19
18
17
PDSEL_2
PDSEL_1
PDSEL_0
VCC
VCCA
ODBSEL_1
ODBSEL_0
ODASEL_1
Rs
221k
9
10
11
12
13
14
15
16
LF
C4
ODBSEL_1
ODBSEL_0
ODASEL_1
R12
To Logic
Input
pins
R19
10
C9
0.1u
C10
0.01u
C11
10u
RD2
1K
Zo = 50 Ohm
+
Zo = 50 Ohm
R16
50
Optional
Y-Termination
R17
50
R18
50
FIGURE 6. ICS813252I-02 SCHEMATIC EXAMPLE
ICS813252CKI-02 REVISION A AUGUST 4, 2016
14
©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality operation
of the VCXO-PLL. In choosing a crystal, special precaution
must be taken with the package and load capacitance (CL). In
addition, frequency, accuracy and temperature range must also be
considered. Since the pulling range of a crystal also varies with the
package, it is recommended that a metal-canned package like HC49
be used. Generally, a metal-canned package has a larger pulling
range than a surface mounted device (SMD). For crystal selection
information, refer to the VCXO Crystal Selection Application Note.
crystal specification. In either case, the absolute tuning range is
reduced. The correct value of CL is dependent on the characteristics
of the VCXO. The recommended CL in the Crystal Parameter Table
balances the tuning range by centering the tuning curve.
The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS
and CP values for recommended high, mid and low loop bandwidth
configurations. The device has been characterized using these
parameters. For other configurations, refer to the Loop Filter
Component Selection for VCXO Based PLLs Application Note.
The crystal and external loop filter components should be kept as
close as possible to the device. Loop filter and crystal traces should
be kept short and separated from
each other. Other signal traces
should be kept separate and not
run underneath the device, loop
filter or crystal components.
The crystal’s load capacitance CL characteristic determines its
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance, IC
package lead capacitance, internal varactor capacitance and any
installed tuning capacitors (CTUNE).
If the crystal’s CL is greater than the total external capacitance,
the VCXO will oscillate at a higher frequency than the crystal
specification. If the crystal’s CL is lower than the total external
capacitance, the VCXO will oscillate at a lower frequency than the
VCXO CHARACTERISTICS TABLE
Symbol
Parameter
Typical
Unit
kVCXO
VCXO Gain
15,700
Hz/V
CV_LOW
Low Varactor Capacitance
9.9
pF
CV_HIGH
High Varactor Capacitance
22.2
pF
VCXO-PLL APPROXIMATE LOOP BANDWIDTH SELECTION TABLE
Bandwidth
Crystal Frequency (MHz)
RS (kΩ)
CS (µF)
CP (µF)
RSET (kΩ)
10Hz (Low)
25MHz
121
1.0
0.01
9.09
90Hz (Mid)
25MHz
221
0.1
0.001
2.21
300Hz (High)
25MHz
680
0.1
0.0001
2.21
CRYSTAL CHARACTERISTICS
Symbol
Parameter
Minimum
Mode of Operation
Fundamental
Typical
Maximum
fN
Frequency
fT
Frequency Tolerance
±20
ppm
fS
Frequency Stability
±20
ppm
85
°C
Operating Temperature Range
25
Units
-40
MHz
CL
Load Capacitance
10
pF
CO
Shunt Capacitance
4
pF
CO/C1
Pullability Ratio
220
ESR
Equivalent Series Resistance
20
Drive Level
1
mW
Aging @ 25°C
±3 per year
ppm
ICS813252CKI-02 REVISION A AUGUST 4, 2016
240
15
©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS813252I-02.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS813252I-02 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 235mA = 814.275mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 814.275mW + 60mW = 874.275mW
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum
recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 37°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.874W * 37°C/W = 117.3°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 32 LEAD VFQFN, FORCED CONVECTION
θJA vs. 0 Air Flow (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
ICS813252CKI-02 REVISION A AUGUST 4, 2016
16
0
1
2.5
37.0°C/W
32.4°C/W
29.0°C/W
©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 7.
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of VCCO– 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
ICS813252CKI-02 REVISION A AUGUST 4, 2016
17
©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN
θJA vs. 0 Air Flow (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
37.0°C/W
32.4°C/W
29.0°C/W
TRANSISTOR COUNT
The transistor count for ICS813252I-02 is: 6579
ICS813252CKI-02 REVISION A AUGUST 4, 2016
18
©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
PACKAGE OUTLINE AND DIMENSIONS - K SUFFIX FOR 32 LEAD VFQFN
S eating Plan e
(R ef.)
A1
Ind ex Area
(Ref.)
N &N
Even
(N -1)x e
A3
N
L
N
Anvil
Anvil
Singulation
Singula tion
e (Ty p.)
2 If N & N
are Even
1
2
OR
E2
(N -1)x e
(Re f.)
E2
2
To p View
b
A
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
0. 08
(Ref.)
e
N &N
Odd
C
Th er mal
Ba se
D2
2
D2
C
Bottom View w/Type A ID
Bottom View w/Type B ID
Bottom View w/Type C ID
BB
4
2
1
N N-1
There are 3 methods of indicating pin 1 corner
at the back of the VFQFN package are:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type B: Dummy pad between pin 1 and N.
3. Type C: Mouse bite on the paddle (near pin 1)
CC
CHAMFER
4
2
1
2
1
4
DD
4
RADIUS
N N-1
N N-1
4
AA
4
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS (VHHD -2/ -4)
SYMBOL
NOTE: The above mechanical package drawing is a generic drawing
that applies to any pin count VFQFN package. This drawing is not
intended to convey the actual pin count or pin layout of this device.
The pin count and pinout are shown on the front page. The package
dimensions are in Table 8.
Minimum
N
Maximum
32
A
0.80
1.0
A1
0
0.05
A3
b
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
8
NE
8
D, E
5.0 BASIC
D2, E2
3.0
3.3
L
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
ICS813252CKI-02 REVISION A AUGUST 4, 2016
19
©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
813252CKI-02LF
ICS352CI02L
32 Lead “Lead-Free” VFQFN
tray
-40°C to 85°C
813252CKI-02LFT
ICS352CI02L
32 Lead “Lead-Free” VFQFN
2500 tape & reel
-40°C to 85°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications.
Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change
any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
ICS813252CKI-02 REVISION A AUGUST 4, 2016
20
©2016 Integrated Device Technology, Inc.
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
ICS813252I-02 Data Sheet
REVISION HISTORY SHEET
Rev
Table
Page
A
T9
20
Ordering Information Table - added ICS prefix in the Part/Order Number.
5/6/08
T5
T9
7
10
AC Characteristics Table - added Thermal Note.
Updated “Wiring the Differential Input to Accept Single-ended Levels” application
note.
Updated Figure 5A & 5B, LVPECL Termination Output drawings.
Updated Package Outline drawing.
Deleted “ICS” prefix from Part/Order Number.
4/13/10
19
Added method package drawing.
Corrected typo in inside page header. from ICS1325I-02 to ICS81325I-02.
8/25/10
1
8/22/14
20
Product Discontinuation Notice - PDN CQ-14-05
Features - removed reference to leaded parts
Ordering Information - removed leaded devices
1
Product Discontinuation Notice to Obsolete.
8/4/16
13
19
20
A
A
T9
A
Description of Change
ICS813252CKI-02 REVISION A AUGUST 4, 2016
21
Date
©2016 Integrated Device Technology, Inc.
ICS813252I-02 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
www.IDT.com
6024 Silver Creek Valley Road Sales
San Jose, CA 95138
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
www.IDT.com/go/contactIDT
Techical Support
clocks@idt.com
+480-763-2056
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performace, is subject to change without notice. Performance specifications and the operating parameters of the described products
are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or
warranty of any kind, whether express or implied, including, but not limited to, the suitablity of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the
intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of
users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Techology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of
IDT or their respective third party owners.
Copyright 2016. All rights reserved.
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