813321AG-04LFT

813321-04 VCXO W/3.3V, 2.5V LVPECL FemtoClock™ PLL PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 GENERAL DESCRIPTION FEATURES The 813321-04 is a two stage device – a VCXO followed by a FemtoClock™ PLL. The FemtoClock PLL can multiply the crystal frequency of the VCXO up to a range of 122MHz to 160MHz, with a random rms phase jitter of less than 1ps (1.875MHz – 20MHz). This phase jitter performance meets the requirements of 1Gb/10Gb Ethernet, 1Gb, 2Gb, 4Gb and 10Gb Fibre Channel, and SONET up to OC48. • One 3.3V or 2.5V LVPECL output pair DATASHEET • Crystal operating frequency range: 14MHz - 20MHz • VCO range: 490MHz - 640MHz • Output frequency range: 122MHz - 160MHz • VCXO pull range: ±50ppm (typical APR) @ 3.3V • Supports the following applications (among others): SONET, Ethernet, Fibre Channel • RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz): 0.53ps (typical) @ 3.3V • Supply voltage modes: VCC/VCCO 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V • 0°C to 70°C ambient operating temperature • Available in both lead-free (RoHS 6) package • For functional replacement part use 8N3QV01EG-0016CDI PIN ASSIGNMENT BLOCK DIAGRAM VCO_SEL Pullup XTAL_IN 0 19.44MHz XTAL_OUT VCXO Phase Detector VCO N = ÷4 490MHz - 640MHz Q nQ 1 VC M = ÷25 (default), ÷32 Pullup 813321-04 OE Pullup 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View SEL 813321-04 REVISION A 3/18/15 1 ©2015 Integrated Device Technology, Inc. 813321-04 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name 1, 6, 11, 15 nc Type Unused Description No connect. 2 VCCO Power Output supply pin. 3, 4 Q, nQ Output Differential clock outputs. LVPECL interface levels. 5 VEE Power Negative supply pin. 7 VCCA Power Analog supply pin. 8 VCC Power Core supply pin. 9, 10 XTAL_OUT, XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 12 VC Input 13 SEL Input 14 OE Input Pullup Output enable pin. When HIGH, the output is active. When LOW, the output is in a high impedance state. LVCMOS/ LVTTL interface. 16 VCO_SEL Input Pullup VCO select pin. LVCMOS/LVTTL interface levels. VCXO control voltage input. Pulldown Select pin. LVCMOS/LVTTL interface levels. See Table 3. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics Table, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ TABLE 3. SEL FUNCTION TABLE Control Input SEL M 0 ÷25 (defalut) 1 ÷32 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL 2 REVISION A 3/18/15 813321-04 DATA SHEET ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 92.4°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum VCC Core Supply Voltage VCCA Analog Supply Voltage VCCO Output Supply Voltage 3.135 ICCA IEE Units 3.135 3.3 3.465 V VCC – 0.10 3.3 VCC V 3.3 3.465 V Analog Supply Current 10 mA Power Supply Current 130 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = 0°C TO 70°C Symbol Parameter VCC Core Supply Voltage VCCA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VCC – 0.10 3.3 VCC V VCCO Output Supply Voltage 2.375 2.5 2.625 V ICCA Analog Supply Current 10 mA IEE Power Supply Current 130 mA TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 2.5V±5%, VEE = 0V, TA = 0°C TO 70°C Symbol Parameter VCC Core Supply Voltage VCCA Minimum Typical Maximum Units 2.375 2.5 2.625 V Analog Supply Voltage VCC – 0.10 2.5 VCC V VCCO Output Supply Voltage 2.375 2.5 2.625 V ICCA Analog Supply Current 10 mA IEE Power Supply Current 125 mA REVISION A 3/18/15 Test Conditions 3 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL 813321-04 DATA SHEET TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, TA = 0°C TO 70°C Symbol Parameter Test Conditions VCC = 3.3V VIH Input High Voltage VCC = 2.5V VCC = 3.3V VIL IIH Input Low Voltage VCC = 2.5V Input High Current OE, VCO_SEL SEL IIL Input Low Current OE, VCO_SEL SEL Minimum Typical 2 VCC + 0.3 V VCC + 0.3 V -0.3 0.8 V -0.3 0.7 V 5 µA 150 µA VCC = VIN = 3.465V or 2.625V VCC = 3.465V or 2.625V, VIN = 0V Units 1.7 VCC = VIN = 3.465V or 2.625V VCC = 3.465V or 2.625V, VIN = 0V Maximum -150 µA -5 µA TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 Typical VCCO - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50 to VCCO - 2V. Ω TABLE 4F. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5% OR 2.5V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCCO - 1.4 VCCO - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.5 V VSWING Peak-to-Peak Output Voltage Swing 0.4 1.0 V NOTE 1: Outputs terminated with 50 to VCCO - 2V. Ω VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL 4 REVISION A 3/18/15 813321-04 DATA SHEET TABLE 5A. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter, (Random); NOTE 1, 2 fVCO PLL VCO Lock Range tR / tF Output Rise/Fall Time Test Conditions Minimum VCO_SEL = 1 122 155.52MHz (1.875MHz - 20MHz) Typical Maximum Units 160 MHz 0.53 20% to 80% odc Output Duty Cycle NOTE 1: Phase jitter using a crystal interface. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. ps 490 640 MHz 250 600 ps 48 52 % Maximum Units 160 MHz TABLE 5B. AC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = 0°C TO 70°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter, (Random); NOTE 1, 2 fVCO PLL VCO Lock Range tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum VCO_SEL = 1 122 155.52MHz (1.875MHz - 20MHz) Typical 0.64 20% to 80% ps 490 640 MHz 250 600 ps 48 52 % Maximum Units 160 MHz NOTE 1: Phase jitter using a crystal interface. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. TABLE 5C. AC CHARACTERISTICS, VCC = VCCO = 2.5V±5%, VEE = 0V, TA = 0°C TO 70°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter, (Random); NOTE 1, 2 fVCO PLL VCO Lock Range tR / tF Output Rise/Fall Time Test Conditions Minimum VCO_SEL = 1 122 155.52MHz (1.875MHz - 20MHz) 20% to 80% odc Output Duty Cycle NOTE 1: Phase jitter using a crystal interface. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. REVISION A 3/18/15 5 Typical 0.53 ps 490 640 MHz 250 600 ps 48 52 % VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL 813321-04 DATA SHEET TYPICAL PHASE NOISE AT 155.52MHZ 0 -10 -20 155.52MHz -40 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.53ps (typical) ➤ -30 -60 OC-12 Filter -70 -80 Raw Phase Noise Data -90 -100 ➤ NOISE POWER dBc Hz -50 -110 -120 -130 -140 ➤ -150 -160 -170 Phase Noise Result by adding Sonet OC-12 Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) REVISION A 3/18/15 6 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL 813321-04 DATA SHEET PARAMETER MEASUREMENT INFORMATION 3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL 7 REVISION A 3/18/15 813321-04 DATA SHEET APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 813321-04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and V CCO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional10Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. 3.3V or 2.5V VCC .01µF 10Ω .01µF 10µF VCCA FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. REVISION A 3/18/15 8 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL 813321-04 DATA SHEET TERMINATION FOR 3.3V LVPECL OUTPUT lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission FIGURE 2A. LVPECL OUTPUT TERMINATION VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL FIGURE 2B. LVPECL OUTPUT TERMINATION 9 REVISION A 3/18/15 813321-04 DATA SHEET TERMINATION FOR 2.5V LVPECL OUTPUT Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCCO = 2.5V, the VCCO - 2V is very close to ground 2.5V VCCO=2.5V Zo = 50 Ohm R1 250 level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C. 2.5V 2.5V VCCO=2.5V R3 250 Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - 2,5V LVPECL Driv er R2 62.5 2,5V LVPECL Driv er R4 62.5 R1 50 R2 50 R3 18 FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE REVISION A 3/18/15 10 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL 813321-04 DATA SHEET VCXO CRYSTAL SELECTION Choosing a crystal with the correct characteristics is one of the most critical steps in using a Voltage Controlled Crystal Oscillator (VCXO). The crystal parameters affect the tuning range and accuracy of a VC ➤ VCXO. Below are the key variables and an example of using the crystal parameters to calculate the tuning range of the VCXO. Oscillator VC - Control voltage used to tune frequency CV - Varactor capacitance, varies due to the change in control voltage CL1, CL2 - Load tuning capacitance used for fine tuning or centering nominal frequency Control Voltage CV C ➤ ➤ V VCXO (Internal) CS1, CS2 - Stray Capacitance caused by pads, vias, and other board parasitics XTAL CS1 CL2 ➤ CL1 CS2 Optional ➤ FIGURE 4. VCXO OSCILLATOR CIRCUIT TABLE 6. EXAMPLE CRYSTAL PARAMETERS Symbol Parameter fN Nominal Frequency fT fS Test Conditions Minimum Typical Maximum Units 20 MHz Frequency Tolerance ±20 ppm Frequency Stability ±20 ppm 70 °C 14 Operating Temperature Range 0 CL Load Capacitance 12 pF CO Shunt Capacitance 4 pF C1, C2 Pullability Ratio ESR 220 240 Equivalent Series Resistance 20 Drive Level 1 Aging @ 25°C ±3 per year Mode of Operation VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL mW ppm Fundamental 11 REVISION A 3/18/15 813321-04 DATA SHEET TABLE 7. VARACTOR PARAMETERS Symbol Parameter CV_LOW Low Varactor Capacitance Test Conditions VC = 0V Minimum Typical 6 Maximum Units pF CV_HIGH High Varactor Capacitance VC = 3.3V 11 pF FORMULAS C Low = (C (C L1 L1 + C S 1 + CV _ Low ) ⋅ (C L 2 + C S 2 + CV _ Low ) C High = + C S 1 + CV _ Low ) + (C L 2 + C S 2 + CV _ Low ) (C (C L1 + C S 1 + CV _ High ) ⋅ (C L 2 + C S 2 + CV _ High ) L1 + C S 1 + CV _ High ) + (C L 2 + C S 2 + CV _ High ) • CLow is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance. CLow determines the high frequency component on the TPR. • CHigh is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance. CHigh determines the low frequency component on the TPR. ⎛ ⎞ ⎜ ⎟ 1 1 ⎟ ⋅ 10 Total Pull Range (TPR ) = ⎜ − ⎜ ⎟ C Low ⎞ C ⎛ ⎛ ⎞ C 0 High ⎟ 2 ⋅ C 0 C 1 ⋅ ⎜1 + ⎜ 2 ⋅ C 1 ⋅ ⎜1 + ⎟⎟ C 0 C 0 ⎝ ⎠ ⎝ ⎠⎠ ⎝ 6 Absolute Pull Range (APR) = Total Pull Range – (Frequency Tolerance + Frequency Stability + Aging) EXAMPLE CALCULATIONS is ±15ppm. Third, though many boards will not require load tuning capacitors (CL1, CL2), it is recommended for long-term consistent performance of the system that two tuning capacitor pads be placed into every design. Typical values for the load tuning capacitors will range from 0 to 4pF. Using the tables and figures above, we can now calculate the TPR and APR of the VCXO using the example crystal parameters. For the numerical example below there were some assumptions made. First, the stray capacitance (CS1, CS2), which is all the excess capacitance due to board parasitic, is 4pF. Second, the expected lifetime of the project is 5 years; hence the inaccuracy due to aging (0 + 4pƒ + 15pƒ ) · (0 + 4pƒ + 15pƒ ) CLow = (0 + 4pƒ + 27.4pƒ ) · (0 + 4pƒ + 27.4pƒ ) = 9.5pƒ CHigh = (0 + 4pƒ + 15pƒ ) · (0 + 4pƒ + 15pƒ ) ⎛ 1 ⎜ TPR == ⎜ ⎜⎜ 2 ⎝ 2· 220 · 1 + 9.5pƒ 4pƒ ( 1 – ) ( 2· 220 · 1 +15.7pƒ 4pƒ ) = 15.7pƒ (0 + 4pƒ + 27.4pƒ ) · (0 + 4pƒ + 27.4pƒ ) ⎞ ⎟ 6 ⎟ ⋅· 10 = 212ppm ⎞⎟ ⎟ ⎟ ⎠⎠ TPR = ±106ppm APR = 106ppm – (20ppm + 20ppm + 15ppm) = ±51ppm (C0/C1 ratio) can be used. Also, with the equations above, one can vary the frequency tolerance, temperature stability, and aging or shunt capacitance to achieve the required pullability. The example above will ensure a total pull range of ±106 ppm with an APR of ±51ppm. Many times, board designers may select their own crystal based on their application. If the application requires a tighter APR, a crystal with better pullability REVISION A 3/18/15 12 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL 813321-04 DATA SHEET POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 813321-04. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 813321-04 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 130mA = 450mW Total Power_MAX (3.465V, with output switching) = 450mW + 30mW = 480mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 92.4°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.480W * 92.4°C/W = 114.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 8. THERMAL RESISTANCE θJA FOR 16-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL 0 1 2.5 92.4°C/W 88.0°C/W 75.91°C/W 13 REVISION A 3/18/15 813321-04 DATA SHEET 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. VCCO Q1 VOUT RL 50Ω VCCO - 2V FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO– 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) = [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW REVISION A 3/18/15 14 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL 813321-04 DATA SHEET RELIABILITY INFORMATION TABLE 9. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 92.4°C/W 88.0°C/W 75.91°C/W TRANSISTOR COUNT The transistor count for 813321-04 is: 3948 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL 15 REVISION A 3/18/15 813321-04 DATA SHEET PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP TABLE 10. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N Maximum 16 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 REVISION A 3/18/15 16 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL 813321-04 DATA SHEET TABLE 11. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS813321AG-04LF 3321A04L 16 lead “Lead-Free” TSSOP tube 0°C to 70°C ICS813321AG-04LFT 3321A04L 16 lead “Lead-Free” TSSOP tape & reel 0°C to 70°C NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL 17 REVISION A 3/18/15 813321-04 DATA SHEET REVISION HISTORY SHEET Rev Table Page A T11 17 A REVISION A 3/18/15 Description of Change Date Removed leaded devices and updated data sheet format 3/19/15 Product Discontinuation Notice - Last time buy expires May 6, 2017 PDN CQ-16-01 5/5/16 18 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL Corporate Headquarters 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. 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