813N2532CKILFT

Jitter Attenuator & FemtoClock® NG Multiplier 813N2532 Datasheet General Description Features The 813N2532 device uses IDT's fourth generation FemtoClock® NG technology for optimal high clock frequency and low phase noise performance, combined with a low power consumption and high power supply noise rejection. The 813N2532 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. • • • Fourth generation FemtoClock® NG technology • Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, HCSL The 813N2532 is a fully integrated Phase Locked loop utilizing a FemtoClock NG Digital VCXO that provides the low jitter, high frequency SONET/PDH output clock that easily meets OC-48 jitter requirements. This VCXO technology simplifies PLL design by replacing the pullable crystal requirement of analog VCXOs with a fixed 27MHz generator crystal. Jitter attenuation down to 10Hz is provided by an external loop filter. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET and Ethernet applications. The device requires the use of an external, inexpensive fundamental mode 27MHz crystal. The device is packaged in a space-saving 32-VFQFN package and supports commercial temperature range. • Accepts input frequencies from 8kHz to 38.88MHz including 8kHz, 19.44MHz, 25MHz and 38.88MHz • Crystal interface optimized for a 27MHz, 10pF parallel resonant crystal • Attenuates the phase jitter of the input clock by using a low-cost fundamental mode crystal • Customized settings for jitter attenuation and reference tracking using external loop filter connection • FemtoClock NG frequency multiplier provides low jitter, high frequency output • • • Absolute pull range: ±100ppm • RMS phase jitter @ 155.52MHz, using a 27MHz crystal (12kHz – 20MHz): 0.64ps (typical) • RMS phase jitter @ 125MHz, using a 27MHz crystal (12kHz – 20MHz): 0.66ps (typical) • • • 3.3V supply voltage nCLK1 CLK1 VCC nCLK0 CLK0 XTAL_OUT VCCX XTAL_IN Pin Assignment Two LVPECL output pairs Output frequencies: 19.44MHz, 25MHz, 125MHz, 155.52MHz and 156.25MHz Power supply noise rejection (PSNR): -95dB (typical) RMS phase jitter @ 156.25MHz, using a 27MHz crystal (12kHz – 20MHz): 0.64ps (typical) 0°C to 70°C ambient operating temperature Lead-free (RoHS 6) packaging 32 31 30 29 28 27 26 25 LF1 1 24 LF0 2 23 nQB VEE ISET 3 22 QB VEE 4 21 VCCO CLK_SEL 5 20 nQA VCC 6 19 QA VEE 17 ODASEL_0 ODASEL_1 ODBSEL_0 ODBSEL_1 VCCA VCC 10 11 12 13 14 15 16 PDSEL_0 9 FB_SEL 18 VEE 8 PDSEL_1 LOR 7 813N2532 32 Lead VFQFN 5mm x 5mm x 0.925mm package body 3.15mm x 3.15mm ePad size K Package Top View ©2016 Integrated Device Technology, Inc. 1 Revision D, April 8, 2016 813N2532 Datasheet Block Diagram LOR 27MHz Pulldown FB_ SEL Pullup PDSEL _ [1:0] Pullup DIGITAL VCXO Xtal Osc. 2 ODASEL_ [1:0 ] QA ÷NA nQA 2 CLK _SEL Pulldown CLK0 Pulldown PD + LF FemtoClock NG VCO QB ÷NB nCLK0 Pullup /Pulldown Fractional Feedback Divider 0 ÷P CLK1 nCLK1 Pulldown 1 Pullup / Pulldown LOR Pulldown Phase Detector + Charge Pump nQB 2 ODBSEL _[1:0] A/ D Control Block ©2016 Integrated Device Technology, Inc. LF0 LF1 ISET ÷M 2 *** Dashed lines indicates external components Revision D, April 8, 2016 813N2532 Datasheet Pin Description and Pin Characteristics Tables Table 1. Pin Descriptions Number Name Type Description 1, 2 LF1, LF0 Analog Input/Output Loop filter connection node pins. LF0 is the output. LF1 is the input. 3 ISET Analog Input/Output Charge pump current setting pin. 4, 8, 18, 24 VEE Power 5 CLK_SEL Input 6, 12, 27 VCC Power Core supply pins. 7 LOR Output Loss of reference indicator. LVCMOS/LVTTL interface levels. 9 FB_SEL Input Pullup Feedback divider select pin. LVCMOS/LVTTL interface levels. See Table 3B. 10, 11 PDSEL_1, PDSEL_0 Input Pullup Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A. 13 VCCA Power 14, 15 ODBSEL_1, ODBSEL_0 Input Pulldown Frequency select pins for Bank B output. See Table 3C. LVCMOS/LVTTL interface levels. 16, 17 ODASEL_1, ODASEL_0 Input Pulldown Frequency select pins for Bank A output. See Table 3C. LVCMOS/LVTTL interface levels. 19, 20 QA, nQA Output Differential Bank A clock outputs. LVPECL interface levels. 21 VCCO Power Output supply pin. 22, 23 QB, nQB Output Differential Bank B clock outputs. LVPECL interface levels. 25 nCLK1 Input Pullup/ Pulldown Inverting differential clock input. VCC/2 bias voltage when left floating. 26 CLK1 Input Pulldown Non-inverting differential clock input. 28 nCLK0 Input Pullup/ Pulldown Inverting differential clock input. VCC/2 bias voltage when left floating. 29 CLK0 Input Pulldown Non-inverting differential clock input. 30, 31 XTAL_OUT, XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. 32 VCCX Power Power supply pin for the crystal oscillator. Negative supply pins. Pulldown Input clock select. When HIGH selects CLK1, nCLK1. When LOW, selects CLK0, nCLK0. LVCMOS / LVTTL interface levels. Analog supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 2 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k ©2016 Integrated Device Technology, Inc. Test Conditions 3 Minimum Typical Maximum Units Revision D, April 8, 2016 813N2532 Datasheet Function Tables Table 3A. Pre-Divider Selection Function Table Table 3C. Output Divider Function Table Inputs Inputs PDSEL_1 PDSEL_0 ÷P Value ODxSEL_1 ODxSEL_0 ÷Nx Value 0 0 1 0 0 128 (default) 0 1 1944 0 1 100 1 0 2500 1 0 20 1 1 3888 (default) 1 1 16 NOTE: x denotes A or B. Table 3B. Feedback Divider Selection Function Table Input FB_SEL VCO Frequency (MHz) 0 2500 1 2488.32 (default) Table 3D. Frequency Function Table Input Frequency (MHz) ÷P Value FemtoClock NG VCXO Center Frequency (MHz) ÷Nx Value Output Frequency (MHz) 0.008 1 2488.32 128 19.44 0.008 1 2500 100 25 0.008 1 2500 20 125 0.008 1 2488.32 16 155.52 0.008 1 2500 16 156.25 19.44 1944 2488.32 128 19.44 19.44 1944 2500 100 25 19.44 1944 2500 20 125 19.44 1944 2488.32 16 155.52 19.44 1944 2500 16 156.25 25 2500 2488.32 128 19.44 25 2500 2500 100 25 25 2500 2500 20 125 25 2500 2488.32 16 155.52 25 2500 2500 16 156.25 38.88 3888 2488.32 128 19.44 38.88 3888 2500 100 25 38.88 3888 2500 20 125 38.88 3888 2488.32 16 155.52 38.88 3888 2500 16 156.25 NOTE: x denotes A or B. ©2016 Integrated Device Technology, Inc. 4 Revision D, April 8, 2016 813N2532 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 3.63V Inputs, VI XTAL_IN Other Inputs 0V to 2V -0.5V to VCC+ 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 33.1C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. LVPECL Power Supply DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage VCC – 0.29 3.3 VCC V VCCO Output Supply Voltage 3.135 3.3 3.465 V VCCX Crystal Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 312 mA ICCA Analog Supply Current 29 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VIH Input High Voltage 2 VCC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH IIL Input High Current Input Low Current Test Conditions Minimum Typical CLK_SEL, CLK0, ODASEL_[1:0], ODBSEL_[1:0] VCC = VIN = 3.465V 150 µA FB_SEL, PDSEL_[1:0] VCC = VIN = 3.465V 10 µA CLK_SEL, CLK0, ODASEL_[1:0], ODBSEL_[1:0] FB_SEL, PDSEL_[1:0] ©2016 Integrated Device Technology, Inc. VCC = 3.465V, VIN = 0V -10 µA VCC = 3.465, VIN = 0V -150 µA 5 Revision D, April 8, 2016 813N2532 Datasheet Table 4C. Differential DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTES 1, 2 VEE VCC – 0.85 V Maximum Units CLK0, nCLK0, CLK1, nCLK1 Minimum Typical VCC = VIN = 3.465V Maximum Units 150 µA CLK0, CLK1 VCC = 3.465V, VIN = 0V -10 µA nCLK0, nCLK1 VCC = 3.465V, VIN = 0V -150 µA NOTE 1: VIL should not be less than -0.3V. NOTE 2. Common mode voltage is defined at the crosspoint. Table 4D. LVPECL DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical VOH Output High Voltage; NOTE 1 VCCO – 1.10 VCCO – 0.75 V VOL Output Low Voltage; NOTE 1 VCCO – 2.0 VCCO – 1.6 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50 to VCCO – 2V. See Parameter Measurement Information section, 3.3V Output Load Test Circuit. ©2016 Integrated Device Technology, Inc. 6 Revision D, April 8, 2016 813N2532 Datasheet AC Electrical Characteristics Table 5. AC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter fIN Input Frequency fOUT Output Frequency tjit(Ø) RMS Phase Jitter, (Random), NOTE 1 tsk(o) Output Skew; NOTE 2, 3 PSNR Power Supply Noise Rejection; NOTE 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle tLOCK Output-to-Input Phase Lock Time; NOTE 5 Test Conditions Minimum Typical Maximum Units 0.008 38.88 MHz 19.44 156.25 MHz 156.25MHz fOUT, 27MHz crystal, Integration Range: 12kHz – 20MHz 0.64 ps 155.52MHz fOUT, 27MHz crystal, Integration Range: 12kHz – 20MHz 0.64 ps 125MHz fOUT, 27MHz crystal, Integration Range: 12kHz – 20MHz 0.66 ps 80 VPP = 50mV Sine Wave, Range: 10kHz – 10MHz 20% to 80% Reference Clock Input is ±100ppm from Nominal Frequency -95 ps dB 200 500 ps 48 52 % 3 s NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized with outputs at the same frequency using the loop filter components for the 44Hz loop bandwidth. Refer to Jitter Attenuator Loop Bandwidth Selection Table. NOTE 1: Refer to the Phase Noise Plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross point. NOTE 4: PSNR results achieved by injecting noise on VCCA supply pin with no external filter network. NOTE 5: Lock Time measured from power-up to stable output frequency. ©2016 Integrated Device Technology, Inc. 7 Revision D, April 8, 2016 813N2532 Datasheet Noise Power dBc Hz Typical Phase Noise at 125MHz Offset Frequency (Hz) ©2016 Integrated Device Technology, Inc. 8 Revision D, April 8, 2016 813N2532 Datasheet Parameter Measurement Information 2V 2V VCC VCC, VCCO, VCCX nCLK[0:1] VCCA V PP Cross Points CLK[0:1] V CMR VEE -1.3V ± 0.165V 3.3V LVPECL Output Load AC Test Circuit Differential Input Level VCC Supply Voltage 60% of VCC VEE Output-to-Inp Phase Lock Output Output-to-Input Phase Lock Time RMS Phase Jitter nQx nQA, nQB Qx nQy QA, QB Qy Output Skew LVPECL Output Rise/Fall Time nQA, nQB QA, QB Output Duty Cycle/Pulse Width/Period ©2016 Integrated Device Technology, Inc. 9 Revision D, April 8, 2016 813N2532 Datasheet Applications Information Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage V1= VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. The values below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. VCC VCC VCC VCC R3 100 Ro RS R1 1K Zo = 50 Ohm + Driver V1 R4 Ro + Rs = Zo Receiv er - 100 C1 0.1uF R2 1K Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ©2016 Integrated Device Technology, Inc. 10 Revision D, April 8, 2016 813N2532 Datasheet Differential Clock Input Interface with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult 3.3V 1.8V Zo = 50Ω CLK Zo = 50Ω nCLK Differential Input LVHSTL IDT LVHSTL Driver R1 50Ω R2 50Ω Figure 2A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver Figure 2B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2D. CLK/nCLK Input Driven by a 3.3V LVDS Driver 3.3V 3.3V *R3 CLK nCLK HCSL *R4 Differential Input Figure 2E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ©2016 Integrated Device Technology, Inc. 11 Revision D, April 8, 2016 813N2532 Datasheet Recommendations for Unused Input and Output Pins Inputs: Outputs: CLK/nCLK Inputs LVPECL Outputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Control Pins All control pins have internal pullup or pulldown resistors; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 3.3V R3 125Ω 3.3V Zo = 50Ω 3.3V R4 125Ω 3.3V 3.3V + Zo = 50Ω + _ LVPECL Input Zo = 50Ω _ R1 50Ω R2 50Ω LVPECL R1 84Ω VCC - 2V RTT = 1 * Zo ((VOH + VOL) / (VCC – 2)) – 2 R2 84Ω RTT Figure 3A. 3.3V LVPECL Output Termination ©2016 Integrated Device Technology, Inc. Input Zo = 50Ω Figure 3B. 3.3V LVPECL Output Termination 12 Revision D, April 8, 2016 813N2532 Datasheet Jitter Attenuator EXTERNAL COMPONENTS Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the Jitter Attenuator. In choosing a crystal, special precaution must be taken with load capacitance (CL), frequency accuracy and temperature range. In addition, the frequency accuracy specification in the crystal characteristics table are used to calculate the APR (Absolute Pull Range) . LF0 LF1 ISET The crystal’s CL characteristic determines its resonating frequency and is closely related to the center tuning of the crystal. The total external capacitance seen by the crystal when installed on a PCB is the sum of the stray board capacitance, IC package lead capacitance, internal device capacitance and any installed tuning capacitors (CTUNE). The recommended CLin the Crystal Parameter Table balances the tuning range by centering the tuning curve for a typical PCB. If the crystal CL is greater than the total external capacitance, the crystal will oscillate at a higher frequency than the specification. If the crystal CL is lower than the total external capacitance, the crystal will oscillate at a lower frequency than the specification. Tuning adjustments might be required depending on the PCB parasitics or if using a crystal with a higher CL specification. RS CP RSET CS XTAL_IN CTUNE 3.3pF 27MHz XTAL_OUT CTUNE 3.3pF Crystal Characteristics Symbol Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental fN Frequency fT Frequency Tolerance ±20 ppm fS Frequency Stability ±20 ppm +70 0C 27 Operating Temperature Range 0 MHz CL Load Capacitance 10 pF CO Shunt Capacitance 4 pF ESR Equivalent Series Resistance 40  Drive Level 1 mW ±3 ppm Aging @ 25 0C ©2016 Integrated Device Technology, Inc. First Year 13 Revision D, April 8, 2016 813N2532 Datasheet Jitter Attenuator Characteristics Table The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS, CP and RSET values for recommended high, mid and low loop bandwidth configurations. The device has been characterized using these parameters. In addition, the digital VCXO gain (KVCXO) has been provided for additional loop filter requirements. Symbol Parameter Typical Units kVCXO VCXO Gain 2.78 kHz/V Jitter Attenuator Loop Bandwidth Selection Table (2ND Order Loop Filter) Bandwidth Crystal Frequency RS (k) CS (µF) CP (µF) R3 (k) C3 (µF) RSET (k) 15Hz (Low) 27MHz 215 10 0.022 0 DEPOP 2.74 30Hz (Mid) 27MHz 365 2.2 0.0047 0 DEPOP 2.74 60Hz (High) 27MHz 470 1 0.0022 0 DEPOP 1.5 NOTE: See Application schematic to identify loop filter components RS, CS, CP, R3, C3 and RSET. For applications in which there is substantial low frequency jitter in the input reference and the phase detector frequency of 8kHz or 10kHz lies in or near a jitter mask, a three pole filter is recommended. Suggested part values are in the table below. Note that the option of a three pole filter can be left open by laying out the three pole filter but setting R3 to 0 and not populating C3. Refer to the application schematic for a specific example. Jitter Attenuator Loop Bandwidth Selection Table (3RD Order Loop Filter) Bandwidth Crystal Frequency RS (k) CS (µF) CP (µF) R3 (k) C3 (µF) RSET (k) 15Hz (Low) 27MHz 196 10 0.022 82.5 0.010 2.74 30Hz (Mid) 27MHz 392 2.2 0.0047 165 0.0022 2.74 60Hz (High) 27MHz 432 1 0.0022 182 0.001 1.5 NOTE: See Application schematic to identify loop filter components RS, CS, CP, R3, C3 and RSET. The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces ©2016 Integrated Device Technology, Inc. should be kept separate and not run underneath the device, loop filter or crystal components. 14 Revision D, April 8, 2016 813N2532 Datasheet VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER PIN LAND PATTERN (GROUND PAD) PIN PAD Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ©2016 Integrated Device Technology, Inc. 15 Revision D, April 8, 2016 813N2532 Datasheet Schematic Example Figure 5 shows an example of the 813N2532 application schematic. In this example, the device is operated at VCC = VCCA = VCCX = VCCO = 3.3V. The inputs are driven by a 3.3V LVPECL driver and an LVDS driver. Two examples of LVPECL output terminations are shown in this schematic. VCC, VCCA, VCCX and VCCO power supplies for each jitter attenuator to isolate any high switching noise from coupling into the internal PLLs. In order to achieve the best possible filtering, it is highly recommended that the 0.1uF capacitors on the device side of the ferrite beads be placed on the device side of the PCB as close to the power pins as possible. This is represented by the placement of these capacitors in the schematic. If space is limited, the ferrite beads, 10µF and 0.1µF capacitor connected to 3.3V can be placed on the opposite side of the PCB. If space permits, place all filter components on the device side of the board. Selection of either the two pole or three pole filter is based on the application. A three pole loop filter is used for the greater reduction of 8kHz or 10kHz phase detector spurs relative to that afforded by a two pole loop filter. These spurs are generated when the input reference contains low frequency jitter in the pass band of the closed loop response. So for example if the 813N2532 is placed downstream from an IDT WAN PLL, then this jitter will not be present, allowing a two pole filter to be used. If however the 813N2532 is used to directly jitter attenuate a line recovered clock, then a three pole filter must be used. It is recommended that the loop filter components be laid out for the 3-pole option. With a three pole layout, the two pole filter option is preserved by depopulating C3 and setting R3 = 0. The loop filter components should be laid out on the 813N2532 side of the PCB directly adjacent to the LF0 and LF1 pins. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 813N2532 provides separate ©2016 Integrated Device Technology, Inc. 16 Revision D, April 8, 2016 813N2532 Datasheet   VCC 3.3V Logic Control Input Examples R 1 10 2 VCCA Set Logic Input to '1' VCC Set Logic Input to '0' VCC C 45 10uF F B1 C8 1 BLM18BB221SN1 C7 0.1uF 10uF R 2 10 RU1 1K R U2 N ot Install To Logic Input pins VCCX C 47 10uF To Logic Input pins RD1 Not I nst all 3.3V F B2 VCCO 2 R D2 1K C 10 1 BLM18BB221SN1 C9 0.1uF 10uF Place each 0.1uF bypass cap directly adjacent to its corresponding VCC, VCCA, VVCCX or VCCO pin. C1 and C2 V alues set by center frequency tune procedure X1 FB_SEL PD SEL_1 PD SEL_0 27MH z (10pf ) OD ASEL_1 OD ASEL_0 C1 TUN E OD BSEL_1 OD BSEL_0 C2 TU NE CLK_SEL Zo = 50 O hm R7 Zo = 50 O hm U1 9 10 F B_SEL 11 PDSEL_1 PDSEL_0 16 17 OD ASEL_1 OD ASEL_0 14 15 OD BSEL_1 OD BSEL_0 5 CLK_SEL 31 30 XTAL_IN XTAL_OU T 29 28 100 VCC VCC VCC VCC 6 12 27 C30 0. 1uF C 15 0. 1uF VCC A VCCX VC CO 13 32 21 C46 0.1uF VC CA VCC X VCC O C14 0. 1uF C12 0. 1uF C 17 0. 1uF CLK0 nCLK0 LOR 7 LO R +3.3V LVD S D river R10 133 R11 133 Zo = 50 O hm R6 50 26 25 Zo = 50 O hm CLK1 nCLK1 QA nQ A 19 20 Z o = 50 Ohm QA nQ A + Z o = 50 Ohm R4 50 PEC L Driver - R5 50 1 (VCC-2.0V) LVPECL Thevinin Termination LF 1 R13 82.5 2 LF 0 3 R14 82.5 ISET Z o = 50 Ohm LF 1 QB nQ B LF0 Z o = 50 Ohm - Cs 2. 2uF 33 ePAD Cp 4.7nF + QB nQ B Rset 2.74K 4 8 18 24 C3 2.2nF Rs 392k VEE VEE VEE VEE R 3 165k 22 23 LVPECL Optional Y-Termination R16 50 R17 50 R18 50 Loop filter and Rset - Mid LBW Setting Figure 5. 813N2532 Schematic Example ©2016 Integrated Device Technology, Inc. 17 Revision D, April 8, 2016 813N2532 Datasheet Power Considerations This section provides information on power dissipation and junction temperature for the 813N2532. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 813N2532 is the sum of the core power plus the power dissipated due to loading. The following is the power dissipation for VCCO = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading. • Power (core)MAX = VCCO_MAX * IEE_MAX = 3.465V * 312mA = 1081.1mW • Power (outputs)MAX = 31.55mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 31.55mW = 63.1mW Total Power_MAX (3.465V, with all outputs switching) = 1081.1mW + 63.1mW = 1144.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 33.1°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 1.1442W * 33.1°C/W = 107.9°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ©2016 Integrated Device Technology, Inc. 0 1 3 33.1°C/W 28.1°C/W 25.4°C/W 18 Revision D, April 8, 2016 813N2532 Datasheet 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50Ω VCCO - 2V Figure 6. LVPECL Driver Circuit and Termination To calculate power dissipation per output pair due to loading, use the following equations which assume a 50 load, and a termination voltage of VCCO – 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.75V (VCC_MAX – VOH_MAX) = 0.75V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.6V (VCC_MAX – VOL_MAX) = 1.6V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V– (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) = [(2V– 0.75V)/50] * 0.75V = 18.75mW Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – 1.6V)/50] * 1.6V = 12.80mW Total Power Dissipation per output pair = Pd_H + Pd_L = 31.55mW ©2016 Integrated Device Technology, Inc. 19 Revision D, April 8, 2016 813N2532 Datasheet Reliability Information Table 7. JA vs. Air Flow Table for a 32 Lead VFQFN JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 3 33.1°C/W 28.1°C/W 25.4°C/W Transistor Count The transistor count for 813N2532 is: 44,795 ©2016 Integrated Device Technology, Inc. 20 Revision D, April 8, 2016 813N2532 Datasheet Package Outline and Package Dimensions Package Outline - K Suffix for 32 Lead VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area A3 N L N Anvil Anvil Singulation Singula tion e (Ty p.) 2 If N & N 1 are Even 2 OR E2 (N -1)x e (Re f.) E2 2 To p View b A (Ref.) D e D2 2 N &N Odd Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C D2 C Bottom View w/Type A ID Bottom View w/Type C ID 2 1 2 1 CHAMFER 4 Th er mal Ba se RADIUS N N-1 4 N N-1 There are 2 methods of indicating pin 1 corner at the back of the VFQFN package: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) Table 8. Package Dimensions Symbol N A A1 A3 b ND & NE D&E D2 & E2 e L JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Minimum Nominal 32 0.80 0 0.25 Ref. 0.18 0.25 NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pin-out are shown on the front page. The package dimensions are in Table 8. Maximum 1.00 0.05 0.30 8 5.00 Basic 3.0 0.30 3.3 0.50 Basic 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 ©2016 Integrated Device Technology, Inc. 21 Revision D, April 8, 2016 813N2532 Datasheet Ordering Information Table 9. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 813N2532CKLF ICS3N2532CL “Lead-Free” 32 Lead VFQFN Tray 0°C to 70°C 813N2532CKLFT ICS3N2532CL “Lead-Free” 32 Lead VFQFN Tape & Reel 0°C to 70°C ©2016 Integrated Device Technology, Inc. 22 Revision D, April 8, 2016 813N2532 Datasheet Revision History Sheet Rev Table B B Page Supply Voltage, VCC. Rating changed from 4.5V min. to 3.63V per Errata NEN-11-03. Correct typo in block diagram from /2 to /3 for PDSEL[2:0]. 6/01/11 1 2 Features Section, deleted SSTL for the Two differential inputs bullet. Corrected block diagram from /3 back to /2 on the PDSEL[1:0]. Removed the connection between the FB_SEL line and the PDSEL[1:0] line. Clock Input Interface Section, deleted all references to SSTL 6/03/11 Features: Updated RMS Phase Jitter data to reflect RMS Phase Jitter data in Table 5 Analog Supply Voltage. Changed from VCC-0.31V to VCC-0.29V, Power Supply Current changed from 300mA to 312mA, Analog Supply Current changed from 31mA to 29mA. RMS Phase Jitter, 156.25MHz changed 0.6ps to 0.64ps, RMS Phase Jitter, 155.52MHz changed 0.622ps to 0.644ps, RMS Phase Jitter, 125MHz changed 0.6ps to 0.66ps. Jitter Attenuator Char Table: changed kVCXO - 2.79 kHz/V Typical to 2.02 Typical kHz/V Power Considerations: changed IEE_MAX = 300mA to 312mA; 1039.55mW to 1081.1mW; Total Power_MAX CHANGED 1039.55mW to 1081.1mW, 1102.65mW 1144.2mW. Tj changed 1.103W and 106.5C to 1.1442W and 107.9C. Changed text: “To calculate worst case power dissipation into the load” to “To calculate power dissipation per output pair due to loading”. Changed transistor count from 44,832 to 44,795. Changed part order number and marking from Rev A to Rev C. Deleted count for Tape and Reel. Deleted Lead-Free note. 8/3/12 Updated Wiring the Differential Input to Accept Single-Ended Levels text and schematic. Jitter Attenuator Characteristics Table: kVCXO 2.78kHz/V. Added Jitter Attenuator Loop Bandwidth Selection Tables: 2nd and 3rd Order Loop Filter. Replaced text and schematic. 9/21/12 Applications Information - deleted Power Supply Filtering Techniques application note. It is included in the schematic example on page 17. Jitter Attenuator Loop Bandwidth Selection Table (3RD Order Loop Filter): corrected C3 (k) heading to C3(µF). 10/2/13 Deleted “ICS” prefix from part number through out the datasheet. Updated datasheet header/footer. 4/8/16 T4A 1 5 T5 7 13 16 17 18 19 C 10 14 17, 18 C D Date 5 2 11 C Description of Change 10 14 ©2016 Integrated Device Technology, Inc. 23 Revision D, April 8, 2016 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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