Jitter Attenuator & FemtoClock NG® Multiplier
813N322I-02
Datasheet
General Description
Features
The 813N322I-02 device uses IDT's fourth generation FemtoClock®
NG technology for optimal high clock frequency and low phase noise
performance, combined with a low power consumption and high
power supply noise rejection. The 813N322I-02 is a PLL based
synchronous multiplier that is optimized for Ethernet to SONET/PDH
clock jitter attenuation and frequency translation.
•
•
•
Fourth Generation FemtoClock® NG technology
•
Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, HCSL
The 813N322I-02 is a fully integrated Phase Locked loop utilizing a
FemtoClock NG Digital VCXO that provides the low jitter, high
frequency SONET/PDH output clock that easily meets OC-48 jitter
requirements. This VCXO technology simplifies PLL design by
replacing the pullable crystal requirement of analog VCXOs with a
fixed 27MHz generator crystal. Jitter attenuation down to 10Hz is
provided by an external loop filter. Pre-divider and output divider
multiplication ratios are selected using device selection control pins.
The multiplication ratios are optimized to support most common
clock rates used in PDH, SONET and Ethernet applications. The
device requires the use of an external, inexpensive fundamental
mode 27MHz crystal. The device is packaged in a space-saving
32-VFQFN package and supports industrial temperature range.
•
Accepts input frequencies from 8kHz to 156.25MHz including
8kHz,19.44MHz, 25MHz, 62.5MHz, 77.76MHz, 125MHz,
155.52MHz and 156.25MHz
•
Crystal interface designed for a 27MHz, 10pF parallel resonant
crystal
•
Attenuates the phase jitter of the input clock by using a low-cost
fundamental mode crystal
•
Customized settings for jitter attenuation and reference tracking
using an external loop filter connection
•
FemtoClock NG frequency multiplier provides low jitter, high
frequency output
•
•
•
•
Absolute pull range: ±50ppm
•
•
•
3.3V supply voltage
Each output supports independent frequency selection at
19.44MHz, 77.76MHz, 155.52MHz and 622.08MHz
Power supply noise rejection (PSNR): -95dB (typical)
FemtoClock NG VCXO frequency: 2488.32MHz
RMS phase jitter @ 155.52MHz, using a 27MHz crystal
(12kHz – 20MHz): 0.674ps (typical)
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
nCLK1
CLK1
VCC
nCLK0
CLK0
XTAL_IN
XTAL_OUT
VCCX
Pin Assignment
Two LVPECL output pairs
32 31 30 29 28 27 26 25
LF1
1
24
LF0
2
23 nQB
VEE
ISET 3
22
QB
VEE 4
21
VCCO
CLK_SEL
5
20 nQA
VCC
6
19 QA
VEE
17
ODASEL_0
ODASEL_1
ODBSEL_0
ODBSEL_1
VCC
VCCA
10 11 12 13 14 15 16
PDSEL_0
9
PDSEL_1
18
VEE 8
PDSEL_2
RESERVED 7
813N322I-02
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
©2016 Integrated Device Technology, Inc.
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Revision C, February 26, 2016
813N322I-02 Datasheet
Block Diagram
27 M Hz
P u lld o w n
D IG IT A L
VCXO
X ta l
O sc
C L K_S E L
PD
+
LF
P u lld o w n
2
O D A S E L_[1:0]
QA
÷N A
nQA
F e m to C lo ck ® N G
VCO
QB
÷NB
C L K0
n C L K0
C L K1
n C L K1
F ra ctio n a l
F e e d b a ck
D ivid e r
P u lld o w n
0
P u llu p /
P u lld o w n
÷P
P u lld o w n
1
P u llu p /
P u lld o w n
P h a se
D e te cto r
+
C h a rg e
Pum p
nQ B
2
P u lld o w n
O D B S E L_ [1:0]
A /D C o n tro l
B lo ck
÷M
LF1
2
ISET
P u llu p
LF0
P D S E L_[2 :0]
NOTE: Refer to the Application Information section
for three pole filter options.
CP
RSET
RS
CS
©2016 Integrated Device Technology, Inc.
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813N322I-02 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
LF1, LF0
Analog
Input/Output
Loop filter connection node pins. LF0 is the output. LF1 is the input.
3
ISET
Analog
Input/Output
Charge pump current setting pin.
4, 8, 18, 24
VEE
Power
5
CLK_SEL
Input
6, 12, 27
VCC
Power
7
RESERVED
Reserve
9,
10,
11
PDSEL_2,
PDSEL_1,
PDSEL_0
Input
13
VCCA
Power
14,
15
ODBSEL_1,
ODBSEL_0
Input
Pulldown
Frequency select pins for Bank B output. See Table 3B.
LVCMOS/LVTTL interface levels.
16,
17
ODASEL_1,
ODASEL_0
Input
Pulldown
Frequency select pins for Bank A output. See Table 3B.
LVCMOS/LVTTL interface levels.
19, 20
QA, nQA
Output
Differential Bank A clock outputs. LVPECL interface levels.
21
VCCO
Power
Output supply pin.
22, 23
QB, nQB
Output
Differential Bank B clock outputs. LVPECL interface levels.
25
nCLK1
Input
Pullup/
Pulldown
Inverting differential clock input. VCC/2 bias voltage when left floating.
26
CLK1
Input
Pulldown
Non-inverting differential clock input.
28
nCLK0
Input
Pullup/
Pulldown
Inverting differential clock input. VCC/2 bias voltage when left floating.
29
CLK0
Input
Pulldown
Non-inverting differential clock input.
30,
31
XTAL_OUT,
XTAL_IN
Input
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
32
VCCX
Power
Power supply pin for the crystal oscillator
Negative supply pins.
Pulldown
Input clock select. When HIGH selects CLK1, nCLK1. When LOW, selects
CLK0, nCLK0. LVCMOS / LVTTL interface levels.
Core supply pins.
Reserve pin.
Pullup
Pre-divider select pins. LVCMOS/LVTTL interface levels.
See Table 3A.
Analog supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
3.5
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
©2016 Integrated Device Technology, Inc.
Test Conditions
3
Minimum
Typical
Maximum
Units
Revision C, February 26, 2016
813N322I-02 Datasheet
Function Tables
Table 3A. Pre-Divider Selection Function Table
Inputs
PDSEL_2
PDSEL_1
PDSEL_0
÷P Value
0
0
0
1
0
0
1
1944
0
1
0
2500
0
1
1
6250
1
0
0
7776
1
0
1
12500
1
1
0
15552
1
1
1
15625 (default)
Table 3B. Output Divider Function Table
Inputs
ODxSEL_1
ODxSEL_0
÷Nx Value
0
0
128 (default)
0
1
32
1
0
16
1
1
4
NOTE: x denotes A or B.
©2016 Integrated Device Technology, Inc.
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813N322I-02 Datasheet
Table 3C. Example Configurations for Selected Output and Input Frequencies
User Configuration and Frequencies
Input
Frequency
(MHz)
Output
Frequency
(MHz)
PDSEL_
[2:0]
ODxSEL_
[1:0]
19.44
PreDivider
P
Feedback
Divider
M
Fractional
Feedback
Divider
FemtoClock
NG
FemtoClock NG
VCXO Center
Frequency
(MHz)
00
77.76
0.008
Internal Divider Values and Frequencies
128
01
000
Output
Divider
Nx
32
1
128
2430
2488.32
155.52
10
16
622.08
11
4
19.44
00
128
77.76
19.44
01
001
32
1944
128
1944
2488.32
155.52
10
16
622.08
11
4
19.44
00
128
77.76
25
01
010
32
2500
128
1944
2488.32
155.52
10
16
622.08
11
4
19.44
00
128
77.76
62.5
01
011
32
6250
128
1944
2488.32
155.52
10
16
622.08
11
4
19.44
00
128
77.76
77.76
01
100
32
7776
128
1944
2488.32
155.52
10
16
622.08
11
4
19.44
00
128
77.76
125
01
101
32
12500
128
1944
2488.32
155.52
10
16
622.08
11
4
19.44
00
128
77.76
155.52
01
110
32
15552
128
1944
2488.32
155.52
10
16
622.08
11
4
19.44
00
128
77.76
156.25
01
111
32
15625
128
1944
2488.32
155.52
10
16
622.08
11
4
NOTE: ODxSEL denotes ODASEL or ODBSEL.
©2016 Integrated Device Technology, Inc.
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813N322I-02 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
3.63V
Inputs, VI
XTAL_IN
Other Inputs
0V to 2V
-0.5V to VCC+ 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, JA
33.1C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. LVPECL Power Supply DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
VCC – 0.30
3.3
VCC
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
VCCX
Charge Pump Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
274
mA
ICCA
Analog Supply Current
30
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
Input
High Current
Input
Low Current
Test Conditions
Minimum
Typical
Maximum
Units
2
VCC + 0.3
V
-0.3
0.8
V
CLK_SEL,
ODASEL_[1:0],
ODBSEL_[1:0]
VCC = VIN = 3.465V
150
µA
PDSEL_[2:0]
VCC = VIN = 3.465V
10
µA
CLK_SEL,
ODASEL_[1:0],
ODBSEL_[1:0]
PDSEL_[2:0]
©2016 Integrated Device Technology, Inc.
VCC = 3.465V, VIN = 0V
-10
µA
VCC = 3.465, VIN = 0V
-150
µA
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813N322I-02 Datasheet
Table 4C. Differential DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
V
VCMR
Common Mode Input Voltage; NOTE 1
VEE
VCC – 0.85
V
Maximum
Units
CLK0, nCLK0,
CLK1, nCLK1
Minimum
Typical
VCC = VIN = 3.465V
Maximum
Units
150
µA
CLK0, CLK1
VCC = 3.465V, VIN = 0V
-10
µA
nCLK0, nCLK1
VCC = 3.465V, VIN = 0V
-150
µA
NOTE 1. Common mode voltage is defined at the cross point.
Table 4D. LVPECL DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VOH
Output High Voltage; NOTE 1
VCCO – 1.10
VCCO – 0.75
V
VOL
Output Low Voltage; NOTE 1
VCCO – 2.0
VCCO – 1.6
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
NOTE 1: Outputs terminated with 50 to VCCO – 2V. See Parameter Measurement Information section, 3.3V Output Load Test Circuit.
©2016 Integrated Device Technology, Inc.
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813N322I-02 Datasheet
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
fIN
Input Frequency
fOUT
Output Frequency
tjit(Ø)
RMS Phase Jitter, (Random),
NOTE 1
tsk(o)
Output Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
PSNR
Power Supply Noise
Rejection; NOTE 4
tLOCK
Output-to-Input Phase
Lock Time; NOTE 5
Test Conditions
Minimum
Typical
Maximum
Units
0.008
156.25
MHz
19.44
622.08
MHz
77.76MHz fOUT, 27MHz crystal,
Integration Range: 12kHz – 20MHz
0.823
0.951
ps
155.52MHz fOUT, 27MHz crystal,
Integration Range: 12kHz – 20MHz
0.674
0.788
ps
622.08MHz fOUT, 27MHz crystal,
Integration Range: 12kHz – 20MHz
0.616
0.736
ps
50
ps
100
450
ps
48
52
%
20% to 80%
VPP = 50mV Sine Wave,
Integration Range: 10kHz - 10MHz
-95
dB
Reference Clock Input is ±50ppm from
Nominal Frequency
3
s
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Characterized with outputs at the same frequency using the loop filter components for the 44Hz loop bandwidth.
Refer to Jitter Attenuator Loop Bandwidth Selection Table.
NOTE 1: Refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: PSNR results achieved by injecting noise on VCCA supply pin with no external filter network.
NOTE 5: Lock Time measured from power-up to stable output frequency.
©2016 Integrated Device Technology, Inc.
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Revision C, February 26, 2016
813N322I-02 Datasheet
Noise Power dBc
Hz
Typical Phase Noise at 155.52MHz
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc.
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813N322I-02 Datasheet
Parameter Measurement Information
2V
2V
VCC
VCC,
VCCO,
VCCX
nCLK[0:1]
VCCA
V
PP
Cross Points
CLK[0:1]
V
CMR
VEE
-1.3V ± 0.165V
3.3V LVPECL Output Load AC Test Circuit
Differential Input Level
VDD
Supply Voltage
VDD min
GND
Output-to-Input
Phase Lock
Output
Lock Time
Not to Scale
Output-to-Input Phase Lock Time
RMS Phase Jitter
nQx
nQA, nQB
Qx
nQy
QA, QB
Qy
Output Skew
LVPECL Output Rise/Fall Time
nQA, nQB
QA, QB
Output Duty Cycle/Pulse Width/Period
©2016 Integrated Device Technology, Inc.
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813N322I-02 Datasheet
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VCC/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1in the center of the input voltage swing. For
example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2
value should be adjusted to set V1 at 1.25V. The values below are for
when both the single ended swing and VCC are at the same voltage.
This configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
impedance. For most 50 applications, R3 and R4 can be 100. The
values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
VCC
VCC
VCC
VCC
R3
100
Ro
RS
R1
1K
Zo = 50 Ohm
+
Driver
V1
R4
Ro + Rs = Zo
Receiv er
-
100
C1
0.1uF
R2
1K
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
©2016 Integrated Device Technology, Inc.
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813N322I-02 Datasheet
Differential Clock Input Interface
with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 3A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 2A to 2E show interface examples
for the CLK/nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
Differential
Input
LVHSTL
IDT
LVHSTL Driver
R1
50Ω
R2
50Ω
Figure 2A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
3.3V
3.3V
*R3
CLK
nCLK
HCSL
*R4
Differential
Input
Figure 2E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
©2016 Integrated Device Technology, Inc.
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813N322I-02 Datasheet
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVPECL Outputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
3.3V
R3
125Ω
3.3V
Zo = 50Ω
3.3V
R4
125Ω
3.3V
3.3V
+
Zo = 50Ω
+
_
LVPECL
Input
Zo = 50Ω
_
R1
50Ω
R2
50Ω
LVPECL
R1
84Ω
VCC - 2V
1
RTT =
* Zo
((VOH + VOL) / (VCC – 2)) – 2
R2
84Ω
RTT
Figure 3A. 3.3V LVPECL Output Termination
©2016 Integrated Device Technology, Inc.
Input
Zo = 50Ω
Figure 3B. 3.3V LVPECL Output Termination
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813N322I-02 Datasheet
Schematic Layout
Figure 4 (next page) shows an example of 813N322I-02 application
schematic. In this example, the device is operated at VCC = VCCA =
VCCX = VCCO = 3.3V. The inputs are driven by a 3.3V LVPECL driver
and an LVDS driver. Two examples of LVPECL output terminations
are shown in this schematic.
In order to achieve the best possible filtering, it is highly
recommended that the 0.1µF capacitors on the device side of the
ferrite beads be placed on the device side of the PCB as close to the
power pins as possible. This is represented by the placement of
these capacitors in the schematic. If space is limited, the ferrite
beads, 10µF and 0.1µF capacitor connected to 3.3V can be placed
on the opposite side of the PCB. If space permits, place all filter
components on the device side of the board.
A three pole loop filter is used for the greater reduction of 8kHz or
10kHz phase detector spurs relative to that afforded by a two pole
loop filter. It is recommended that the loop filter components be laid
out on the 813N322I-02 side of the PCB directly adjacent to the LF0
and LF1 pins.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 813N322I-02 provides
separate VCC, VCCA, VCCX and VCCO power supplies for each jitter
attenuator to isolate any high switching noise from coupling into the
internal PLLs.
©2016 Integrated Device Technology, Inc.
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Revision C, February 26, 2016
813N322I-02 Datasheet
Zo = 50 Ohm
CLK1
Log ic Control Input Ex ampl es
Zo = 50 Ohm
nCLK1
Set Logi c
Inp ut to '1 '
VC C
R1
50
3.3V LVPECL Driver
Set Lo gic
In put to '0'
VCC
R2
50
RU1
1K
R9
50
RU 2
Not Inst all
To Logic
Input
pins
To Logic
Input
pins
RD1
Not I nstall
RD 2
1K
Zo = 50 Ohm
CLK0
R33
Zo = 50 Ohm
100
nC LK0
VCC = VCCA = VCCX = VCCO
= 3.3V
LVDS Dr iv er
XTAL_OU T
C1
TUNE
X1
27MHz ( 10pf )
P lace eac h 0. 1uF bypas s ca p
d irec tly adja cent to i t's
c orre spon ding VCC , VCC A, V CCX or
V CCO pin.
XTAL_IN
C2
TU NE
Loop fil ter for
Mid Ba ndwidth settin g
R10
133
VCC
VCC X
C4
0.1uF
R 3 220k
3. 3V
R11
133
Z o = 50 Ohm
+
C16
0.1uF
33
Cs
1uF
LF1
LF0
C LK_SEL
VCC
ePAD
LF1
LF0
ISET
VEE
CLK_SEL
VC C
RESERVED
VEE
Z o = 50 Ohm
Rset
2.21K
-
R13
82.5
VEE
nQB
QB
VCCO
nQA
QA
VEE
ODASEL_0
24
23
22
21
20
19
18
17
R14
82.5
nQB
QB
Optional Fo ur
Re sistor
Thevini n
Termin ation
nQA
QA
ODASEL_0
Zo = 50 Ohm
+
Zo = 50 Ohm
9
10
11
12
13
ODBSEL_1 14
ODBSEL_0 15
OD ASEL_1 16
C8
0.1uF
1
2
3
4
5
6
7
8
0.1uF
C7
32
31
30
29
28
27
26
25
U1
VCCX
XT AL_IN
XTAL_OU T
CLK0
nCLK0
VCC
CLK1
nCLK1
C3
1nF
PDSEL_2
PDSEL_1
PDSEL_0
VCC
VCCA
ODBSEL_1
ODBSEL_0
ODASEL_1
Rs
470k
Cp
2.2nF
VCCO
PD SEL_2
PDSEL_1
PD SEL_0
R16
50
R17
50
For AC termination options c onsult
the IDT Applications Note
"Termination - LVPECL"
R18
50
VCC
R 19 10
VCCA
C9
0.1uF
C10
0.1uF
VCC
3. 3V
VCC
C 11
10uF
2
F B1
1
BLM18BB221SN1
C 13
C 12
0.1uF
10uF
R 12
10
VC CX
3. 3V
VCCO
C6
10uF
C 15
10uF
2
F B2
1
BLM18BB221SN1
C 14
0.1uF
Figure 4. 813N322I-02 Application Schematic
©2016 Integrated Device Technology, Inc.
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Revision C, February 26, 2016
813N322I-02 Datasheet
Jitter Attenuator External Components
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality operation of
the Jitter Attenuator. In choosing a crystal, special precaution must
be taken with load capacitance (CL), frequency accuracy and
temperature range.
the PCB parasitics or if using a crystal with a higher CL specification.
In addition, the frequency accuracy specification in the crystal
characteristics table are used to calculate the APR (Absolute Pull
Range).
LF0
LF1
ISET
The crystal’s CL characteristic determines its resonating frequency
and is closely related to the center tuning of the crystal. The total
external capacitance seen by the crystal when installed on a PCB is
the sum of the stray board capacitance, IC package lead
capacitance, internal device capacitance and any installed tuning
capacitors (CTUNE). The recommended CLin the Crystal Parameter
Table balances the tuning range by centering the tuning curve for a
typical PCB. If the crystal CL is greater than the total external
capacitance, the crystal will oscillate at a higher frequency than the
specification. If the crystal CL is lower than the total external
capacitance, the crystal will oscillate at a lower frequency than the
specification. Tuning adjustments might be required depending on
RS
CP
RSET
CS
XTAL_IN
CTUNE
3.3pF
27MHz
XTAL_OUT
CTUNE
3.3pF
Crystal Characteristics
Symbol
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
fN
Frequency
fT
Frequency Tolerance
27
±20
ppm
fS
Frequency Stability
±20
ppm
+85
0C
Operating Temperature Range
MHz
-40
CL
Load Capacitance
10
pF
CO
Shunt Capacitance
4
pF
ESR
Equivalent Series Resistance
Aging @ 25
0C
First Year
The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS,CP
and RSET values for recommended high, mid and low loop bandwidth
configurations. The device has been characterized using these
parameters. In addition, the digital VCXO gain (KVCXO) has been
provided for additional loop filter requirements.
40
±3
ppm
Jitter Attenuator Characteristics Table
Symbol
Parameter
Typical
Units
kVCXO
VCXO Gain
2.018
kHz/V
Jitter Attenuator Loop Bandwidth Selection Table (2ND Order Loop Filter)
Bandwidth
Crystal Frequency
RS (k)
CS (µF)
CP (µF)
R3 (k)
C3 (k)
RSET (k)
9Hz (Low)
27MHz
140
10
0.01
0
Do not Populate
2.21
44Hz (Mid)
27MHz
487
1
0.0022
0
Do not Populate
1.87
56Hz (High)
27MHz
487
1
0.0022
0
Do not Populate
1.5
NOTE: See Application schematic to identify loop filter components RS, CS, CP, R3, C3 and RSET.
©2016 Integrated Device Technology, Inc.
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Revision C, February 26, 2016
813N322I-02 Datasheet
For applications in which there is substantial low frequency jitter in
the input reference and the phase detector frequency of 8kHz or
10kHz lies in or near a jitter mask, a three pole filter is recommended.
Suggested part values are in the table below. Note that the option of
a three pole filter can be left open by laying out the three pole filter
but setting R3 to 0 ohms and not populating C3. Refer to the
application schematic for a specific example.
Jitter Attenuator Loop Bandwidth Selection Table (3RD Order Loop Filter)
Bandwidth
Crystal Frequency
RS (k)
CS (µF)
CP (µF)
R3 (k)
C3 (k)
RSET (k)
14Hz (Low)
27MHz
300
1
0.01
220
0.001
3.0
29Hz (Mid)
27MHz
470
1
0.0022
220
0.001
2.21
52Hz (High)
27MHz
520
1
0.0022
220
0.001
1.5
NOTE: See Application schematic to identify loop filter components RS, CS, CP, R3, C3 and RSET.
The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept
short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal
components.
©2016 Integrated Device Technology, Inc.
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Revision C, February 26, 2016
813N322I-02 Datasheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 5. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
PIN
LAND PATTERN
(GROUND PAD)
PIN PAD
Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
©2016 Integrated Device Technology, Inc.
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Revision C, February 26, 2016
813N322I-02 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 813N322I-02.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 813N322I-02 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCCO = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCCO_MAX * IEE_MAX = 3.465V * 274mA = 949.41mW
•
Power (outputs)MAX = 31.55mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 31.55mW = 63.1mW
Total Power_MAX (3.3V, with all outputs switching) = 949.41mW + 63.1mW = 1012.51mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 33.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.013W * 33.1°C/W = 118.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
©2016 Integrated Device Technology, Inc.
0
1
2.5
33.1°C/W
28.1°C/W
25.4°C/W
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Revision C, February 26, 2016
813N322I-02 Datasheet
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCCO – 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.75V
(VCC_MAX – VOH_MAX) = 0.75V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.6V
(VCC_MAX – VOL_MAX) = 1.6V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V– (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V– 0.75V)/50] * 0.75V = 18.75mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.6V)/50] * 1.6V = 12.80mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 31.55mW
©2016 Integrated Device Technology, Inc.
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Revision C, February 26, 2016
813N322I-02 Datasheet
Reliability Information
Table 7. JA vs. Air Flow Table for a 32 Lead VFQFN
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
33.1°C/W
28.1°C/W
25.4°C/W
Transistor Count
The transistor count for 813N322I-02 is: 44,795
©2016 Integrated Device Technology, Inc.
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Revision C, February 26, 2016
813N322I-02 Datasheet
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
L
A3
N
N
Anvil
Anvil
Singulation
Singula tion
e (Ty p.)
2 If N & N
1
are Even
2
OR
E2
(N -1)x e
(Re f.)
E2
2
To p View
b
A
(Ref.)
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
e
N &N
Odd
0. 08
Bottom View w/Type A ID
C
4
Th er mal
Ba se
D2
C
Bottom View w/Type C ID
2
1
2
1
CHAMFER
D2
2
N N-1
RADIUS
4
N N-1
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pin out are shown on the front page. The
package dimensions are in Table 8.
Table 8. Package Dimensions
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.25
0.30
8
ND & NE
D&E
5.00 Basic
D2 & E2
3.0
3.3
e
0.50 Basic
L
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
©2016 Integrated Device Technology, Inc.
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Revision C, February 26, 2016
813N322I-02 Datasheet
Ordering Information
Table 9. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
813N322CKI-02LF
ICS322CI02L
“Lead-Free” 32 Lead VFQFN
Tray
-40°C to 85°C
813N322CKI-02LFT
ICS322CI02L
“Lead-Free” 32 Lead VFQFN
Tape & Reel
-40°C to 85°C
©2016 Integrated Device Technology, Inc.
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Revision C, February 26, 2016
813N322I-02 Datasheet
Revision History Sheet
Rev
B
B
C
Table
Page
Description of Change
4A
5
6
8
10
23
VCCA Min: changed VCC-0.27 to VCC-0.30; ICCA Max: changed 27mA to 30mA.
tR/tF: changed 140ps to 100ps.
Corrected Differential Input Level diagram.
Deleted Tape and Reel quantity.
Per PCN No. N1205-01
8/11/12
1
15
Removed PCN nomenclature.
New Schematic.
8/22/12
Deleted “ICS” prefix from part number.
Updated datasheet header/footer.
2/26/16
©2016 Integrated Device Technology, Inc.
Date
24
Revision C, February 26, 2016
Corporate Headquarters
Sales
Tech Support
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
email: clocks@idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as
those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected
names, logos and designs, are the property of IDT or their respective third party owners.
Copyright ©2016 Integrated Device Technology, Inc. All rights reserved.
