82P33731ABAG

Synchronous Equipment Timing Source for 10G/40G/100G Synchronous Ethernet HIGHLIGHTS • • • • • • • • Synchronous Equipment Timing Source (SETS) for Synchronous Ethernet (SyncE) per ITU-T G.8264 DPLL1 generates ITU-T G.8262 compliant SyncE clocks, Telcordia GR-1244-CORE/GR-253-CORE, and ITU-T G.813 compliant SONET/ SDH clocks DPLL2 performs rate conversions for synchronization interfaces or for other general purpose timing applications APLL3 is Voltage Controlled Crystal Oscillator (VCXO) based and generates clocks with jitter 25Hz) frequency translator that can be used, for example, to convert a recovered line clock to a 1.544 MHz or 2.048 MHz synchronization interface clock. For SETS applications per ITU-T G.8264, DPLL1 is configured as an EEC/SEC to output clocks for the T0 reference point and DPLL2 is used to output clocks for the T4 reference point. Clocks generated by DPLL1 can be passed through APLL1 or APLL2 which are LC based jitter attenuating Analog PLLs (APLLs). The output clocks generated by APLL1 and APLL2 are suitable for serial GbE and lower rate interfaces. Clocks generated by DPLL1 can be passed through APLL3 which is a voltage controlled crystal oscillator (VCXO) based jitter attenuating APLL. APLL3 can be provisioned with one or two selectable crystal resonators to support up to two base frequencies. The output clocks generated by APLL3 are suitable for multi-lane 100GBASE-R, 40GBASE-R and lower rate interfaces. The device provides an AMI output for a CC signal bearing 64 kHz, 8 kHz and 0.4 kHz synchronization information. The CC output can be connected to either DPLL1 or DPLL3. All 82P33731 control and status registers are accessed through an I2C slave microprocessor interface. For configuring the DPLLs, APLL1 and APLL2, the I2C master interface can automatically load a configuration from an external EEPROM after reset. APLL3 must be configured via the I2C slave interface. ©2017 Integrated Device Technology, Inc. 2 August 28, 2017 82P33731 Datasheet FUNCTIONAL BLOCK DIAGRAM System Clock LOS0 / XO_FREQ0 LOS1 / XO_FREQ1 LOS2 / XO_FREQ2 SYS PLL LOS3 APLL1 IN1(CC) IN2(CC) Composite Clocks OutDiv OUT1 OutDiv OUT2 OutDiv OUT3p/n OutDiv OUT4p/n OutDiv OUT5p/n OutDiv OUT6p/n IN3(P/N) IN4(P/N) IN5(P/N) IN6(P/N) IN7(P/N) IN8(P/N) IN9 IN10 Reference monitors APLL2 DPLL1 (T0) Reference selection Frac-N input dividers IN11 DPLL2 (T4) IN12 OutDiv OUT7 Composite Clock OUT8 OutDiv OUT9 OutDiv OUT10 OutDiv OUT11p/n OutDiv OUT12p/n IN13 IN14 APLL3 (VCXO) ex_sync module I2C Master I2C Slave Control and Status Registers FRSYNC_8K_1PPS MFRSYNC_2K_1PPS JTAG Crystal Figure 1. Functional Block Diagram ©2017 Integrated Device Technology, Inc. 3 August 28, 2017 82P33731 Datasheet CONTENTS HIGHLIGHTS ........................................................................................................................................................................... 1 FEATURES .............................................................................................................................................................................. 1 APPLICATIONS ....................................................................................................................................................................... 1 DESCRIPTION......................................................................................................................................................................... 2 FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................... 3 CONTENTS.............................................................................................................................................................................. 3 1 PIN ASSIGNMENT ............................................................................................................................................................. 5 2 PIN DESCRIPTION ............................................................................................................................................................ 6 2.1 2.2 2.3 RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS ............................................................................................................. 9 2.1.1 Inputs ................................................................................................................................................................................................. 9 2.1.2 Outputs ............................................................................................................................................................................................... 9 RESET OPERATION ..................................................................................................................................................................................... 10 MS/SL PIN USAGE ........................................................................................................................................................................................ 10 3 FUNCTIONAL DESCRIPTION .......................................................................................................................................... 11 3.1 3.2 SYNCHRONOUS ETHERNET (SYNCE), SONET, AND SDH SYSTEM ARCHITECTURES ...................................................................... 11 HARDWARE FUNCTIONAL DESCRIPTION ................................................................................................................................................ 13 3.2.1 System clock .................................................................................................................................................................................... 13 3.2.2 Modes of operation .......................................................................................................................................................................... 13 3.2.2.1 DPLL1 Operating Mode ................................................................................................................................................... 13 3.2.2.1.1 Free-Run Mode ............................................................................................................................................. 15 3.2.2.1.2 Pre-Locked Mode .......................................................................................................................................... 15 3.2.2.1.3 Locked Mode ................................................................................................................................................. 15 3.2.2.1.4 Pre-Locked2 Mode ........................................................................................................................................ 17 3.2.2.1.5 Lost-Phase Mode .......................................................................................................................................... 17 3.2.2.1.6 DCO Control Modes ...................................................................................................................................... 17 3.2.2.1.7 Holdover Mode .............................................................................................................................................. 18 3.2.2.1.8 Hitless Reference Switching .......................................................................................................................... 18 3.2.2.1.9 Phase Slope Limit .......................................................................................................................................... 19 3.2.2.1.10 Frequency Offset Limit .................................................................................................................................. 19 3.2.2.2 DPLL2 Operating Mode ................................................................................................................................................... 19 3.2.2.2.1 Free-Run Mode ............................................................................................................................................. 19 3.2.2.2.2 Locked Mode ................................................................................................................................................. 19 3.2.2.2.3 Holdover Mode .............................................................................................................................................. 19 3.2.2.2.4 Frequency Offset Limit .................................................................................................................................. 20 3.2.3 Input Clocks and frame sync ............................................................................................................................................................ 20 3.2.3.1 Input Clock Pre-divider ..................................................................................................................................................... 20 3.2.3.2 Input Clock Quality Monitoring ......................................................................................................................................... 22 3.2.3.2.1 Loss of Signal (LOS) Monitoring .................................................................................................................... 22 3.2.3.2.2 Activity Monitoring ......................................................................................................................................... 22 3.2.3.2.3 Frequency Monitoring .................................................................................................................................... 23 3.2.3.3 Input Clock Selection ........................................................................................................................................................ 24 3.2.3.3.1 Forced Selection ............................................................................................................................................ 24 3.2.3.3.2 Automatic Selection ....................................................................................................................................... 24 3.2.3.3.2.1Input Clock Validation ................................................................................................................... 24 3.2.3.3.2.2Revertive and Non-Revertive Switching ....................................................................................... 25 3.2.3.3.3 Selected / Qualified Input Clocks Indication .................................................................................................. 25 3.2.3.3.4 Input Clock Loss of Signal ............................................................................................................................. 25 3.2.4 DPLL Locking Process ..................................................................................................................................................................... 25 3.2.4.1 Fast Loss .......................................................................................................................................................................... 25 3.2.4.2 Fine Phase Loss ............................................................................................................................................................... 25 ©2017 Integrated Device Technology, Inc. 3 August 28, 2017 82P33731 Datasheet 3.2.5 3.2.6 3.2.7 3.2.8 3.2.4.3 Hard Limit Exceeding ....................................................................................................................................................... 3.2.4.4 Locking Status .................................................................................................................................................................. 3.2.4.5 Phase Lock Alarm ............................................................................................................................................................ APLL1 and APLL2 ............................................................................................................................................................................ APLL3 .............................................................................................................................................................................................. 3.2.6.1 External Crystals .............................................................................................................................................................. Output Clocks & Frame Sync Signals .............................................................................................................................................. 3.2.7.1 Output Clocks ................................................................................................................................................................... 3.2.7.2 Frame Sync Signals ......................................................................................................................................................... Input and output Phase control ........................................................................................................................................................ 3.2.8.1 DPLL1 and DPL2 Phase offset control ............................................................................................................................. 3.2.8.2 Input Phase control .......................................................................................................................................................... 3.2.8.3 Output Phase control ........................................................................................................................................................ 25 25 26 26 27 27 28 28 29 31 31 31 31 4 POWER SUPPLY FILTERING TECHNIQUES ................................................................................................................. 32 5 MICROPROCESSOR INTERFACE .................................................................................................................................. 34 5.1 5.2 I2C SLAVE MODE ......................................................................................................................................................................................... 34 5.1.1 I2C Device Address ......................................................................................................................................................................... 34 5.1.2 I2C Bus Timing ................................................................................................................................................................................. 34 5.1.3 Supported Transactions ................................................................................................................................................................... 36 I2C MASTER MODE ...................................................................................................................................................................................... 36 5.2.1 I2C Boot-up Initialization Mode ........................................................................................................................................................ 37 5.2.2 EEPROM memory map notes .......................................................................................................................................................... 37 6 JTAG ................................................................................................................................................................................. 38 7 THERMAL MANAGEMENT .............................................................................................................................................. 39 7.1 7.2 JUNCTION TEMPERATURE ......................................................................................................................................................................... 39 THERMAL RELEASE PATH .......................................................................................................................................................................... 39 8.1 8.2 8.3 ABSOLUTE MAXIMUM RATING ................................................................................................................................................................... 40 RECOMMENDED OPERATION CONDITIONS ............................................................................................................................................ 40 I/O SPECIFICATIONS ................................................................................................................................................................................... 41 8.3.1 AMI Input / Output Port .................................................................................................................................................................... 41 8.3.1.1 Structure ........................................................................................................................................................................... 41 8.3.1.2 I/O Level ........................................................................................................................................................................... 41 8.3.1.3 Over-Voltage Protection ................................................................................................................................................... 42 8.3.2 CMOS Input / Output Port ................................................................................................................................................................ 42 8.3.3 LVPECL / LVDS Input / Output Port ................................................................................................................................................. 43 8.3.3.1 PECL Input Port ............................................................................................................................................................... 43 8.3.3.2 LVPECL Output Port .................................................................................................................................................... 44 8.3.3.2.1 LVPECL Termination for 3.3 V ...................................................................................................................... 44 8.3.3.2.2 LVPECL Termination for 2.5 V ...................................................................................................................... 45 8.3.4 LVDS Input / Output Port ................................................................................................................................................................. 46 8.3.4.1 LVDS Input Port ............................................................................................................................................................... 46 8.3.4.2 LVDS Output Port ............................................................................................................................................................. 47 8.3.5 Output Clock Duty Cycle .................................................................................................................................................................. 48 8.3.6 Wiring the Differential Input for Single-Ended Levels ....................................................................................................................... 49 JITTER PERFORMANCE ........................................................................................................................................................................... 50 INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................... 61 OUTPUT / OUTPUT CLOCK TIMING ........................................................................................................................................................... 61 8 ELECTRICAL SPECIFICATIONS ..................................................................................................................................... 40 8.4 8.5 8.6 PACKAGE OUTLINE DRAWINGS – PAGE 1........................................................................................................................ PACKAGE OUTLINE DRAWINGS – PAGE 2........................................................................................................................ ORDERING INFORMATION.................................................................................................................................................. REVISION HISTORY ............................................................................................................................................................. ©2017 Integrated Device Technology, Inc. 4 62 63 64 64 August 28, 2017 82P33731 Datasheet 1 PIN ASSIGNMENT 1 2 3 4 5 6 7 8 9 10 11 12 A OUT5_POS OUT5_NEG OUT6_POS OUT6_NEG VDDAO OUT12_POS VDDAO  OUT11_POS CAP2 XTAL2_IN SONET/SDH/LO S3 XTAL1_IN B VSSAO VDDAO VDDAO VSSAO VSSAO OUT12_NEG VSSAO OUT11_NEG VSSA XTAL2_OUT MPU_MODE1/I XTAL1_OUT 2CM_SCL B C VDDA VSSA VSS OUT7 I2C_SDA VDDA VDDA IC CAP1 IC MPU_MODE0/I MFRSYNC_2 2CM_SDA K_1PPS C D VSSA VDDA VSSCOM VSSD VDDD VSSA VSSA CAP3 I2C_AD2 I2C_SCL OUT10 OUT9 D E OSCI VSSA IC VDDDO I2C_AD1 VDDD0 VSSDO VSSA DPLL2_LOCK IN14 IN13 FRSYNC_8K_ 1PPS E F TMS VDDA VSSA VSSDO VSS VSSD VDDD VSSA VDDA IN12 IN8_NEG IN8_POS F G TCK VDDA IC VSS VSS VSS IC VSS IC IN11 IN7_NEG IN7_POS G H XO_FREQ0/ LOS0 VDDA VSSA VSS VSS VSS VSS VSS DPLL1_LOCK IN10 VSSD VDDD_1_8 H J XO_FREQ1/ LOS1 XO_FREQ2/ LOS2 VSS VSS VSS VSS VSS VSS INT_REQ IN9 IN6_NEG IN6_POS J K VDDA VDDA TRSTB VSSAO OUT2 RSTB VSSDO MS_SL IN2 IN1 IN5_NEG IN5_POS K L VSSA VSSA TDI VDDAO TDO IC VDDDO OUT1 VSSD VDDD_1_8 IN4_NEG IN4_POS L M OUT4_POS OUT4_NEG VSSAO VDDAO OUT3_POS OUT3_NEG VSSDO VDDDO OUT8_POS OUT8_NEG IN3_NEG IN3_POS M 1 2 3 4 5 6 7 8 9 10 11 12 A Figure 1. Pin Assignment (Top View) ©2017 Integrated Device Technology, Inc. 5 August 28, 2017 82P33731 Datasheet 2 PIN DESCRIPTION Table 1: Pin Description Pin No. Name I/O Type Description Global Control Signal E1 K8 OSCI MS/SL I I pull-up CMOS OSCI: Crystal Oscillator System Clock A clock provided by a crystal oscillator is input on this pin. It is the system clock for the device. The oscillator frequency is selected via pins XO_FREQ0 ~ XO_FREQ2 CMOS MS/SL: Master / Slave Selection This pin, together with the MS_SL_CTRL bit, controls whether the device is configured as the Master or as the Slave. The signal level on this pin is reflected by the MASTER_SLAVE bit. MS_SL = 0: Slave MS_SL = 1: Master (default with internal pull-up) A11 SONET/SDH/ LOS3 I pull-down CMOS SONET/SDH: SONET / SDH Frequency Selection During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H): High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET); Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH). After reset, this pin takes on the operation of LOS3 LOS3- This pin is used to disqualify input clocks. See input clocks section for more details. K6 RSTB I pull-up CMOS RSTB: Reset Refer to section 2.2 reset operation for detail. H1 J1 J2 XO_FREQ0/ LOS0 XO_FREQ1/ LOS1 XO_FREQ2/ LOS2 K10 IN1 K9 IN2 M12 M11 IN3_POS IN3_NEG L12 L11 IN4_POS IN4_NEG K12 K11 IN5_POS IN5_NEG J12 J11 IN6_POS IN6_NEG G12 G11 IN7_POS IN7_NEG XO_FREQ0 ~ XO_FREQ2: These pins set the oscillator frequency. XO_FREQ[2:0] Oscillator Frequency (MHz) 000 10.000 001 12.800 010 13.000 I 011 19.440 pull-down CMOS 100 20.000 101 24.576 110 25.000 111 30.720 LOS0 ~ LOS2 - These pins are used to disqualify input clocks. See input clocks section for more details. After reset, this pin takes on the operation of LOS0-LOS2 Input Clock and Frame Synchronization Input Signal IN1: Input Clock 1 A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin. I AMI AMI input has internal 1k ohm to 1.5V termination. IN2: Input Clock 2 A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin. I AMI AMI input has internal 1k ohm to 1.5V termination. IN3_POS / IN3_NEG: Positive / Negative Input Clock 3 I PECL/LVDS A reference clock is input on this pin.This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. IN4_POS / IN4_NEG: Positive / Negative Input Clock 4 I PECL/LVDS A reference clock is input on this pin.This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. IN5_POS / IN5_NEG: Positive / Negative Input Clock 5 I PECL/LVDS A reference clock is input on this pin.This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. IN6_POS / IN6_NEG: Positive / Negative Input Clock 6 I PECL/LVDS A reference clock is input on this pin.This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. IN7_POS / IN7_NEG: Positive / Negative Input Clock 7 I PECL/LVDS A reference clock is input on this pin.This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. ©2017 Integrated Device Technology, Inc. 6 August 28, 2017 82P33731 Datasheet Table 1: Pin Description (Continued) Pin No. Name F12 F11 IN8_POS IN8_NEG J10 IN9 H10 IN10 G10 IN11 F10 IN12 E11 IN13 E10 IN14 I/O Type Description IN8_POS / IN8_NEG: Positive / Negative Input Clock 8 I PECL/LVDS A reference clock is input on this pin.This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. IN9: Input Clock 9 I CMOS A reference clock is input on this pin.This pin can also be used as a sync input, and in this pull-down case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. IN10: Input Clock 10 I CMOS A reference clock is input on this pin.This pin can also be used as a sync input, and in this pull-down case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. IN11: Input Clock 11 I CMOS A reference clock is input on this pin.This pin can also be used as a sync input, and in this pull-down case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. IN12: Input Clock 12 I CMOS A reference clock is input on this pin.This pin can also be used as a sync input, and in this pull-down case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. IN13: Input Clock 13 I CMOS A reference clock is input on this pin.This pin can also be used as a sync input, and in this pull-down case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. IN14: Input Clock 14 I CMOS A reference clock is input on this pin.This pin can also be used as a sync input, and in this pull-down case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. Output Frame Synchronization Signal E12 C12 FRSYNC _8K_1PPS MFRSYNC _2K_1PPS O CMOS FRSYNC_8K_1PPS: 8 kHz Frame Sync Output An 8 kHz signal or a 1PPS sync signal is output on this pin. O CMOS MFRSYNC_2K_1PPS: 2 kHz Multiframe Sync Output A 2 kHz signal or a 1PPS sync signal is output on this pin. Output Clock L8 K5 M5 M6 M1 M2 A1 A2 A3 A4 C4 OUT1 OUT2 OUT3_POS OUT3_NEG OUT4_POS OUT4_NEG OUT5_POS OUT5_NEG OUT6_POS OUT6_NEG OUT7 M9 M10 OUT8_POS OUT8_NEG D12 D11 A8 B8 A6 B6 OUT9 OUT10 OUT11_POS OUT11_NEG OUT12_POS OUT12_NEG C9, A9, D8 CAP1, CAP2, CAP3 ©2017 Integrated Device Technology, Inc. OUT1 ~ OUT2: Output Clock 1 ~ 2 O CMOS O PECL/LVDS OUT3_POS / OUT3_NEG: Positive / Negative Output Clock 3 This output is set to LVDS by default. O PECL/LVDS OUT4_POS / OUT4_NEG: Positive / Negative Output Clock 4 This output is set to LVDS by default. O PECL/LVDS OUT5_POS / OUT5_NEG: Positive / Negative Output Clock 5 This output is set to LVDS by default. O PECL/LVDS OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6 This output is set to LVDS by default. O CMOS O AMI O O CMOS CMOS O PECL/LVDS O PECL/LVDS OUT7: Output Clock 7 OUT8_POS / OUT8_NEG: Positive / Negative Output Composite Clock A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is differentially output on this pair of pins. OUT9: Output Clock 9 OUT10: Output Clock 10 OUT11_POS / OUT11_NEG: Positive / Negative Output Clock 11 OUT12_POS / OUT12_NEG: Positive / Negative Output Clock 12 Miscellaneous CAP1, CAP2 and CAP3: Analog Power Filter Capacitor connection 1 to 3. These capacitors are be part of the power filtering. 7 August 28, 2017 82P33731 Datasheet Table 1: Pin Description (Continued) Pin No. Name I/O Type A12 XTAL1_IN I Analog B12 XTAL1_OUT O Analog A10 XTAL2_IN I Analog B10 XTAL2_OUT O Analog Description Crystal oscillator 1 input. Determines first of two frequency families (Sonet/SDH, Ethernet or Ethernet*66/64) available for APLL3. Connect to ground if XTAL1 is not used. Crystal oscillator 1 output. Leave open if XTAL1 is not used. Crystal oscillator 2 input. Determines first of two frequency families (chosen from Sonet/SDH, Ethernet or Ethernet*66/ 64) available for APLL3. Connect to ground if XTAL2 is not used Crystal oscillator 2 output. Leave open if XTAL2 is not used. Lock Signal E9 DPLL2_LOCK O CMOS H9 DPLL1_LOCK O CMOS INT_REQ O Tri-state DPLL2_LOCK This pin goes high when DPLL2 is locked DPLL1_LOCK This pin goes high when DPLL1 is locked Microprocessor Interface J9 B11 MPU_MODE1/ I2CM_SCL I/O pull-up C11 MPU_MODE0/ I2CM_SDA D9 I2C_AD2 E5 I2C_AD1 D10 I2C_SCL I C5 I2C_SDA I/O I pull-down I pull-down CMOS INT_REQ: Interrupt Request This pin is used as an interrupt request. MPU_MODE[1:0]: Microprocessor Interface Mode Selection During reset, these pins determine the default value of the MPU_SEL_CNFG[1:0] bits as follows: 00: I2C mode 01 ~ 10: Reserved CMOS/ Open Drain 11: I2C master (EEPROM) mode I2CM_SCL: Serial Clock Line In I2C master mode, the serial clock is output on this pin. I2CM_SDA: Serial Data Input for I2C Master Mode In I2C master mode, this pin is used as the for the serial data. I2C_AD2: Device Address Bit 2 CMOS I2C_AD[2:1] pins are the address bus of the microprocessor interface. I2C_AD1: Device Address Bit 1 CMOS I2C_AD[2:1] pins are the address bus of the microprocessor interface. I2C_SCL: Serial Clock Line CMOS The serial clock is input on this pin. I2C_SDA: Serial Data Input/Output Open Drain This pin is used as the input/output for the serial data. JTAG (per IEEE 1149.1) F1 TMS I pull-up CMOS K3 TRSTB I pull-up CMOS G1 TCK I pull-down CMOS L3 TDI I pull-up CMOS ©2017 Integrated Device Technology, Inc. TMS: JTAG Test Mode Select The signal on this pin controls the JTAG test performance and is sampled on the rising edge of TCK. TRSTB: JTAG Test Reset (Active Low) A low signal on this pin resets the JTAG test port. This pin should be connected to ground when JTAG is not used. TCK: JTAG Test Clock The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge of TCK and TDO is updated on the falling edge of TCK. If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely retain their state. TDI: JTAG Test Data Input The test data are input on this pin. They are clocked into the device on the rising edge of TCK. 8 August 28, 2017 82P33731 Datasheet Table 1: Pin Description (Continued) Pin No. Name L5 TDO I/O O tri-state Type Description CMOS TDO: JTAG Test Data Output The test data are output on this pin. They are clocked out of the device on the falling edge of TCK. TDO pin outputs a high impedance signal except during the process of data scanning. Power & Ground C1, C6, C7, D2, F2, F9, G2, H2, K1, K2 A5, A7, B2, B3, L4, M4 E4, E6, L7, M8 D5, F7 L10, H12 B9, C2, D1, D6, D7, E2, E8, F3, F8, H3, L1, L2 B1, B4, B5, B7, K4, M3 E7, F4, K7, M7 D4, F6, H11, L9 D3 C3, F5, G4, G5, G6, G8, H4, H5, H6, H7, H8, J3, J4, J5, J6, J7, J8 VDDA Power - VDDAO VDDDO VDDD VDDD_1_8 Power Power Power Power VSSA Ground VSSAO VSSDO VSSD VSSCOM Ground Ground Ground Ground - VSS Ground - - VDDA: Analog Core Power - +3.3V DC nominal VDDAO: Analog Output Power - +3.3V DC nominal VDDDO: Digital Output Power - +3.3V DC nominal VDDD: Digital Core Power - +3.3V DC nominal VDDD_1_8: Digital Core Power - +1.8V DC nominal VSSA: Ground VSSAO: Ground VSSDO: Ground VSSD: Ground VSSCOM: Ground VSS: Ground Other C8, C10, E3, G3, G7, G9, L6 2.1 2.1.1 IC - - IC: Internal Connection Internal Use. This pin must be left open for normal operation. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS XTAL Inputs For applications not requiring the use of a crystal oscillator input, both _IN and _OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from _IN to ground. INPUTS Control Pins 2.1.2 All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Status Pins For applications not requiring the use of a status pin, we recommend bringing out to a test point for debugging purposes. Single-Ended Clock Inputs Single-Ended Clock Outputs For protection, unused single-ended clock inputs should be tied to ground. All unused single-ended clock outputs can be left floating, or can be brought out to a test point for debugging purposes. Differential Clock Inputs Differential Clock Outputs For applications not requiring the use of a differential input, both *_POS and *_NEG can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from _POS to ground. ©2017 Integrated Device Technology, Inc. OUTPUTS All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. 9 August 28, 2017 82P33731 Datasheet 2.2 RESET OPERATION If loading from an EEPROM, the maximum time from RSTB deassert to have stable clocks is 100ms. Note that if there is a bad EEPROM read sequence and the EEPROM loading is repeated once or twice (three times halts the device), then this time can be 2 or 3 times longer respectively. If not loading from EEPROM the maximum time from RSTB de-assert to have stable clocks is 10ms. The device must be reset properly in order to ensure operations conform with specification. To properly reset the device, the RSTB pin must be held at a low value for at least 50 usec. The device should be brought out of reset only at the time when power supplies are stabilized and the system clock is available on OSCi pin. The RSTB can be held low until this time, or pulsed low for at least 50us after this time. An on-board reset circuit or a commercially available voltage supervisory can be used to generate the reset signal. It is also feasible to use a standalone power-up RC reset circuit. When using a power-up RC reset circuit, careful consideration must be taken into account to fine tune the circuit properly based on each power supply's specification to ensure the power supply rise time is fast enough with respect to the RC time constant of the RC circuit. The bootstrap pins (XO_FREQ[2:0], MPU_MODE[1:0], I2C_AD[2:1], MS/SL, SONET/SDH) need to be held at desired states for at least 2ms after de-assertion of RSTB pin to allow correct sampling. See Figure 3 for detail. VDDD VDDA OSCI RSTB Bootstrap Pins* 50ȝs 2ms * Bootstrap pins are: XO_FREQ[2:0], MPU_MODE[1:0], I2C_AD[2:1], MS/SL, SONET/SDH Figure 2. Reset timing diagram 2.3 MS/SL PIN USAGE For more information, see AN-901, How to Implement Master/Slave for SETS and SMU Devices on Timing Redundancy Designs. The MS/SL pin is used for timing card redundancy applications where there is a primary and secondary timing card in the system. For other applications, this pin should be left unconnected or connected to an external pull-up. ©2017 Integrated Device Technology, Inc. 10 August 28, 2017 82P33731 Datasheet 3 FUNCTIONAL DESCRIPTION 3.1 SYNCHRONOUS ETHERNET (SYNCE), SONET, AND SDH SYSTEM ARCHITECTURES jitter requirement is 0.3ps from 10 kHz to 20 MHz. The 82P33731 does meet this tight jitter requirement. 82P33731integrates key features that allows the device to be used in Synchronous Ethernet, SONET and SDH applications. There are several key synchronization standards that are important to meet for such a system, they are: • ITU-T Recommendation G.8262, Timing characteristics of Synchronous Ethernet Equipment slave clock (EEC) • ITU-T Recommendation G.8264, Distribution of timing through packet networks • ITU-T Recommendation G.812, Timing requirements of slave clocks suitable for use as node clocks in synchronization networks. • ITU-T Recommendation G.813, Timing characteristics of SDH equipment slave clocks (SEC). • GR-253-CORE - Telcordia Technologies Generic Requirements Issue 5, October 2009 • GR-1244-CORE - Telcordia Technologies Generic Requirements Issue 4, October 2009 • ATIS-0900101.2006 - T1.101 - Synchronization Interface Standard Single Blade BITS/SSU SyncE-TxCK SyncE-RxCK LOS SyncE/ SONET /SDH PHY Ethernet CDR T4 TCXO Figure 3. SyncE/SONET/SDH single blade application Figure 4 shows an active/redundant architecture, as described before it is usually used in Telecom equipment that are designed to have a redundant timing card in case of primary timing card failure. The redundant timing card mimics the output of the active timing card, so in case of failure the system will still provide proper synchronization. Figure 3 shows a single blade architecture that it is usually used in simple equipment. As an example, for a specific 10G PHY, the maximum ©2017 Integrated Device Technology, Inc. SyncE (T0) A P L L 11 August 28, 2017 82P33731 Datasheet Timing Card Line Card SSU/BITS SyncE (T0) A P L L SyncE-TxCK DPLL1 T4 A P L L SyncE-TxCK SyncE-RxCK LOS SyncE/ SONET/ SDH PHY XO Active/ redundant connection Line Card DPLL1 LOS Timing Card SyncE (T0) SyncE-TxCK SyncE-RxCK DPLL2 TCXO SSU/BITS A P L L DPLL2 A P L L SyncE/ SONET/ SDH PHY XO SyncE-TxCK Line Card T4 TCXO DPLL1 A P L L SyncE-TxCK SyncE-RxCK LOS DPLL2 SyncE/ SONET/ SDH PHY XO Figure 4. SyncE/SONET/SDH active/redundant application ©2017 Integrated Device Technology, Inc. 12 August 28, 2017 82P33731 Datasheet 3.2 HARDWARE FUNCTIONAL DESCRIPTION 3.2.2 MODES OF OPERATION 3.2.1 SYSTEM CLOCK 3.2.2.1 DPLL1 Operating Mode The DPLL1 can operate in several different modes as shown in Table 3. A crystal oscillator should be used as an input on the OSCI pin. This clock is provided for the device as a system clock. The system clock is used as a reference clock for all the internal circuits. The active edge of the system clock can be selected by the OSC_EDGE bit in xo_freq_cnfg register. The DPLL1 operating mode is controlled by the DPLL1_OPERATING_MODE[4:0] bits . Table 3: DPLL1 Operating Mode Control Eight common oscillator frequencies can be used for the stable System Clock. The oscillator frequency can be set by pins or by xo_freq_cnfg register as shown in Table 2. Table 2: Oscillator Frequencies xo_freq[2:0] pins xo_freq_cnfg[2:0] bits Oscillator Frequency (MHz) 000 10.000 001 12.800 010 13.000 011 19.440 100 20.000 101 24.576 110 25.000 111 30.720 DPLL1 Operating Mode 00000 00001 00010 00011 00100 00101 00110 00111 01000-01001 Automatic Forced - Free-Run Forced - Holdover Reserved Forced - Locked Forced - Pre-Locked2 Forced - Pre-Locked Forced - Lost-Phase Reserved DCO write frequency see Chapter 3.2.2.1.6) Reserved Reserved 01010 10010 - 11111 10011-11111 When the operating mode is switched automatically, the operation of the internal state machine is shown in Figure 5. Whether the operating mode is under external control or is switched automatically, the current operating mode is always indicated by the DPLL1_DPLL_OPERATING_STS[4:0] bits. When the operating mode switches, the DPLL1_OPERATING_STS bit will be set. If the DPLL1_OPERATING_STS bit is ‘1’, an interrupt will be generated if the corresponding mask bit is set to “1”, the mask bit is set to “0” by default. An offset from the nominal frequency may be compensated by setting the NOMINAL_FREQ_VALUE[23:0] bits. The calibration range is within ±741 ppm. The crystal oscillator should be chosen accordingly to meet different applications and standard requirements. (See AN-807 Recommended Crystal Oscillators for NetSynchro WAN PLL). ©2017 Integrated Device Technology, Inc. DPLL1_OPERATING_MODE[4:0] 13 August 28, 2017 82P33731 Datasheet 1 Free-R un m ode 3 2 Pre-Locked m ode 4 5 Locked m ode 10 9 15 Pre-Locked2 m ode 8 6 H oldover m ode 7 11 12 Lost-Phase m ode 13 14 Figure 5. DPLL Automatic Operating Mode Notes to Figure 5: 1. Reset. 2. An input clock is selected. 3. The DPLL selected input clock is disqualified AND No qualified input clock is available. 4. The DPLL selected input clock is switched to another one. 5. The DPLL selected input clock is locked (the DPLL_LOCK bit is ‘1’). 6. The DPLL selected input clock is disqualified AND No qualified input clock is available. 7. The DPLL selected input clock is unlocked (the DPLL_LOCK bit is ‘0’). 8. The DPLL selected input clock is locked again (the DPLL_LOCK bit is ‘1’). 9. The DPLL selected input clock is switched to another one. 10. The DPLL selected input clock is locked (the DPLL_LOCK bit is ‘1’). 11. The DPLL selected input clock is disqualified AND No qualified input clock is available. 12. The DPLL selected input clock is switched to another one. 13. The DPLL selected input clock is disqualified AND No qualified input clock is available. 14. An input clock is selected. 15. The DPLL selected input clock is switched to another one. The causes of Item 4, 9, 12, 15 - ‘the DPLL selected input clock is switched to another one’ - are: (The DPLL selected input clock is disqualified AND Another input clock is switched to) OR (In Revertive switching, a qualified input clock with a higher priority is switched to) OR (The DPLL selected input clock is switched to another one Forced selection). ©2017 Integrated Device Technology, Inc. 14 August 28, 2017 82P33731 Datasheet 3.2.2.1.1 In the first two seconds when the DPLL1 attempts to lock to the selected input clock, the starting bandwidth and damping factor are used. They are set by the DPLL1_START_BW[4:0] bits and the DPLL1_START_DAMPING[2:0] bits respectively. Free-Run Mode In Free-Run mode, the DPLL1 output refers to the system clock and is not affected by any input clock. The accuracy of the DPLL1 output is equal to that of the system clock. 3.2.2.1.2 During the acquisition, the acquisition bandwidth and damping factor are used. They are set by the DPLL1_ACQ_BW[4:0] bits and the DPLL1_ACQ_DAMPING[2:0] bits respectively. Pre-Locked Mode In Pre-Locked mode, the DPLL1 output attempts to track the selected input clock. When the DPLL1 is locked, the locked bandwidth and damping factor are used. They are set by the DPLL1_LOCKED_BW[4:0] bits and the DPLL1_LOCKED_DAMPING[2:0] bits respectively. The Pre-Locked mode is a secondary, temporary mode. 3.2.2.1.3 Locked Mode The corresponding bandwidth and damping factor are used when the DPLL1 operates in different locking stages: starting, acquisition and locked, as controlled by the device automatically. In Locked mode, the DPLL1 is locked to the input clock. The phase and frequency offset of the DPLL1 output track those of the DPLL1 selected input clock. The locked bandwidth is selectable can be set as shown in Table 4. For a closed loop, different bandwidths and damping factors can be used depending on DPLL locking stages: starting, acquisition and locked. ©2017 Integrated Device Technology, Inc. 15 August 28, 2017 82P33731 Datasheet Table 4: DPLL1 Locked Bandwidth DPLL1_LOCKED_BW[4:0] BW 00000 0.090 mHz 00001 0.27 mHz 00010 0.90 mHz stratum 3E, BW