DUAL CHANNEL T1/E1/J1 SHORT
HAUL LINE INTERFACE UNIT
IDT82V2042E
FEATURES:
•
•
•
•
•
•
Dual channel T1/E1/J1 short haul line interfaces
Supports HPS (Hitless Protection Switching) for 1+1 protection
without external relays
Programmable T1/E1/J1 switchability allowing one bill of material for any line condition
Single 3.3 V power supply with 5 V tolerance on digital interfaces
Meets or exceeds specifications in
- ANSI T1.102, T1.403 and T1.408
- ITU I.431, G.703, G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR12/13
- AT&T Pub 62411
Software programmable or hardware selectable on:
- Wave-shaping templates
- Line terminating impedance (T1:100 Ω, J1:110 Ω, E1: 75 Ω/120 Ω)
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path or transmit path)
- Single rail/dual rail system interfaces
- B8ZS/HDB3/AMI line encoding/decoding
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
- High impedance setting for line drivers
•
•
•
•
•
•
•
•
•
- PRBS (Pseudo Random Bit Sequence) generation and detection
with 215-1 PRBS polynomials for E1
- QRSS (Quasi Random Sequence Signals) generation and detection
with 220-1 QRSS polynomials for T1/J1
- 16-bit BPV (Bipolar Pulse Violation) / Excess Zero/ PRBS or QRSS
error counter
- Analog loopback, Digital loopback, Remote loopback and Inband
loopback
Adaptive receive sensitivity up to -20 dB (Host Mode only)
Non-intrusive monitoring per ITU G.772 specification
Short circuit protection and internal protection diode for line
drivers
LOS (Loss Of Signal) detection with programmable LOS levels
(Host Mode only)
AIS (Alarm Indication Signal) detection
JTAG interface
Supports serial control interface, Motorola and Intel Non-Multiplexed interfaces and hardware control mode
Pin compatible to 82V2082 T1/E1/J1 Long Haul/Short Haul LIU
and 82V2052E E1 Short Haul LIU
Available in 80-pin TQFP
Green package options available
DESCRIPTION:
The IDT82V2042E can be configured as a dual channel T1, E1 or J1 Line
Interface Unit. The IDT82V2042E performs clock/data recovery, AMI/
B8ZS/HDB3 line decoding and detects and reports the LOS conditions. An
integrated Adaptive Equalizer is available to increase the receive sensitivity
and enable programming of LOS levels. In transmit path, there is an AMI/
B8ZS/HDB3 encoder and Waveform Shaper. There is one Jitter Attenuator,
which can be placed in either the receive path or the transmit path. The Jitter
Attenuator can also be disabled. The IDT82V2042E supports both Single
Rail and Dual Rail system interfaces. To facilitate the network maintenance,
a PRBS/QRSS generation/detection circuit is integrated in the chip, and dif-
ferent types of loopbacks can be set according to the applications. Four different kinds of line terminating impedance, 75 Ω,100 Ω, 110 Ω and 120 Ω
are selectable on a per channel basis. The chip also provides driver shortcircuit protection and internal protection diode and supports JTAG boundary scanning. The chip can be controlled by either software or hardware.
The IDT82V2042E can be used in LAN, WAN, Routers, Wireless Base
Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,
CSU/DSU equipment, etc.
.IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1
December 12, 2005
DSC-6774/1
IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL BLOCK DIAGRAM
LOSn
One of the Two Identical Channels
LOS/AIS
Detector
RCLKn
RDn/RDPn
CVn/RDNn
B8ZS/
HDB3/AMI
Decoder
PRBS Detector
IBLC Detector
TCLKn
TDn/TDPn
TDNn
Jitter
Attenuator
Remote
Loopback
B8ZS/
HDB3/AMI
Decoder
Data and
Clock
Recovery
Adaptive
Equalizer
Data
Slicer
Receiver
Internal
Termination
RRINGn
Analog
Loopback
Digital
Loopback
Jitter
Attenuator
RTIPn
Waveform
Shaper
TTIPn
Transmitter
Internal
Termination
Line
Driver
TRINGn
PRBS Generator
IBLC Generator
TAOS
JTAG TAP
TDI
TDO
Pin Control
TRST
TCK
TMS
Register
Files
MODE[1:0]
TERMn
RXTXM[1:0]
PULSn[3:0]
PATTn[1:0]
JA[1:0]
MONTn
LPn[1:0]
THZ
RCLKE
RPDn
RST
Software Control Interface
INT
CS
SDO
SCLK
R/W/WR/SDI
RD/DS/SCLKE
A[5:0]
D[7:0]
MCLK
Clock
Generator
VDDIO
VDDD
VDDA
VDDT
VDDR
G.772
Monitor
Figure-1 Block Diagram
FUNCTIONAL BLOCK DIAGRAM
2
December 12, 2005
Table of Contents
1
IDT82V2042E PIN CONFIGURATIONS ....................................................................................... 9
2
PIN DESCRIPTION ..................................................................................................................... 10
3
FUNCTIONAL DESCRIPTION .................................................................................................... 18
3.1
CONTROL MODE SELECTION ....................................................................................... 18
3.2
T1/E1/J1 MODE SELECTION .......................................................................................... 18
3.3
TRANSMIT PATH ............................................................................................................. 18
3.3.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 18
3.3.2 ENCODER .............................................................................................................. 18
3.3.3 PULSE SHAPER .................................................................................................... 18
3.3.3.1 Preset Pulse Templates .......................................................................... 18
3.3.3.2 User-Programmable Arbitrary Waveform ................................................ 20
3.3.4 TRANSMIT PATH LINE INTERFACE..................................................................... 23
3.3.5 TRANSMIT PATH POWER DOWN ........................................................................ 23
3.4
RECEIVE PATH ............................................................................................................... 24
3.4.1 RECEIVE INTERNAL TERMINATION.................................................................... 24
3.4.2 LINE MONITOR ...................................................................................................... 25
3.4.3 ADAPTIVE EQUALIZER......................................................................................... 26
3.4.4 RECEIVE SENSITIVITY ......................................................................................... 26
3.4.5 DATA SLICER ........................................................................................................ 26
3.4.6 CDR (Clock & Data Recovery)................................................................................ 26
3.4.7 DECODER .............................................................................................................. 26
3.4.8 RECEIVE PATH SYSTEM INTERFACE ................................................................ 26
3.4.9 RECEIVE PATH POWER DOWN........................................................................... 26
3.4.10 G.772 NON-INTRUSIVE MONITORING ................................................................ 27
3.5
JITTER ATTENUATOR .................................................................................................... 28
3.5.1 JITTER ATTENUATION FUNCTION DESCRIPTION ............................................ 28
3.5.2 JITTER ATTENUATOR PERFORMANCE ............................................................. 28
3.6
LOS AND AIS DETECTION ............................................................................................. 29
3.6.1 LOS DETECTION ................................................................................................... 29
3.6.2 AIS DETECTION .................................................................................................... 31
3.7
TRANSMIT AND DETECT INTERNAL PATTERNS ........................................................ 32
3.7.1 TRANSMIT ALL ONES ........................................................................................... 32
3.7.2 TRANSMIT ALL ZEROS......................................................................................... 32
3.7.3 PRBS/QRSS GENERATION AND DETECTION.................................................... 32
3.8
LOOPBACK ...................................................................................................................... 32
3.8.1 ANALOG LOOPBACK ............................................................................................ 32
3.8.2 DIGITAL LOOPBACK ............................................................................................. 32
Table of Contents
3
December 12, 2005
IDT82V2042E
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
3.8.3 REMOTE LOOPBACK............................................................................................ 33
3.8.4 INBAND LOOPBACK.............................................................................................. 34
3.8.4.1 Transmit Activate/Deactivate Loopback Code......................................... 34
3.8.4.2 Receive Activate/Deactivate Loopback Code.......................................... 34
3.8.4.3 Automatic Remote Loopback .................................................................. 35
ERROR DETECTION/COUNTING AND INSERTION ...................................................... 36
3.9.1 DEFINITION OF LINE CODING ERROR ............................................................... 36
3.9.2 ERROR DETECTION AND COUNTING ................................................................ 36
3.9.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 37
LINE DRIVER FAILURE MONITORING ........................................................................... 37
MCLK AND TCLK ............................................................................................................. 38
3.11.1 MASTER CLOCK (MCLK) ...................................................................................... 38
3.11.2 TRANSMIT CLOCK (TCLK).................................................................................... 38
MICROCONTROLLER INTERFACES ............................................................................. 39
3.12.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 39
3.12.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 39
INTERRUPT HANDLING .................................................................................................. 40
5V TOLERANT I/O PINS .................................................................................................. 41
RESET OPERATION ........................................................................................................ 41
POWER SUPPLY ............................................................................................................. 41
4
PROGRAMMING INFORMATION .............................................................................................. 42
4.1
REGISTER LIST AND MAP ............................................................................................. 42
4.2
Reserved Registers .......................................................................................................... 42
4.3
REGISTER DESCRIPTION .............................................................................................. 44
4.3.1 GLOBAL REGISTERS............................................................................................ 44
4.3.2 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 45
4.3.3 JITTER ATTENUATION CONTROL REGISTER ................................................... 45
4.3.4 TRANSMIT PATH CONTROL REGISTERS........................................................... 46
4.3.5 RECEIVE PATH CONTROL REGISTERS ............................................................. 48
4.3.6 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 49
4.3.7 INTERRUPT CONTROL REGISTERS ................................................................... 52
4.3.8 LINE STATUS REGISTERS ................................................................................... 55
4.3.9 INTERRUPT STATUS REGISTERS ...................................................................... 57
4.3.10 COUNTER REGISTERS ........................................................................................ 58
5
HARDWARE CONTROL PIN SUMMARY .................................................................................. 59
6
IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 61
6.1
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 62
6.2
JTAG DATA REGISTER ................................................................................................... 62
6.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 62
6.2.2 BYPASS REGISTER (BR)...................................................................................... 62
6.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 62
Table of Contents
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December 12, 2005
IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
6.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 62
7
TEST SPECIFICATIONS ............................................................................................................ 65
8
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 78
8.1
SERIAL INTERFACE TIMING .......................................................................................... 78
8.2
PARALLEL INTERFACE TIMING ..................................................................................... 79
Table of Contents
5
December 12, 2005
List of Tables
Table-1
Table-2
Table-3
Table-4
Table-5
Table-6
Table-7
Table-8
Table-9
Table-10
Table-11
Table-12
Table-13
Table-14
Table-15
Table-16
Table-17
Table-18
Table-19
Table-20
Table-21
Table-22
Table-23
Table-24
Table-25
Table-26
Table-27
Table-28
Table-29
Table-30
Table-31
Table-32
Table-33
Table-34
Table-35
Table-36
Table-37
Table-38
Table-39
Table-40
Table-41
List of Tables
Pin Description ..............................................................................................................
Transmit Waveform Value For E1 75 Ohm ...................................................................
Transmit Waveform Value For E1 120 Ohm .................................................................
Transmit Waveform Value For T1 0~133 ft...................................................................
Transmit Waveform Value For T1 133~266 ft...............................................................
Transmit Waveform Value For T1 266~399 ft...............................................................
Transmit Waveform Value For T1 399~533 ft...............................................................
Transmit Waveform Value For T1 533~655 ft...............................................................
Transmit Waveform Value For J1 0~655 ft ...................................................................
Impedance Matching for Transmitter ............................................................................
Impedance Matching for Receiver ................................................................................
Criteria of Starting Speed Adjustment...........................................................................
LOS Declare and Clear Criteria, Adaptive Equalizer Disabled .....................................
LOS Declare and Clear Criteria, Adaptive Equalizer Enabled ......................................
AIS Condition ................................................................................................................
Criteria for Setting/Clearing the PRBS_S Bit ................................................................
EXZ Definition ...............................................................................................................
Interrupt Event...............................................................................................................
Global Register List and Map........................................................................................
Per Channel Register List and Map ..............................................................................
ID: Device Revision Register ........................................................................................
RST: Reset Register .....................................................................................................
GCF: Global Configuration Register .............................................................................
INTCH: Interrupt Channel Indication Register...............................................................
TERM: Transmit and Receive Termination Configuration Register ..............................
JACF: Jitter Attenuation Configuration Register ...........................................................
TCF0: Transmitter Configuration Register 0 .................................................................
TCF1: Transmitter Configuration Register 1 .................................................................
TCF2: Transmitter Configuration Register 2 .................................................................
TCF3: Transmitter Configuration Register 3 .................................................................
TCF4: Transmitter Configuration Register 4 .................................................................
RCF0: Receiver Configuration Register 0.....................................................................
RCF1: Receiver Configuration Register 1.....................................................................
RCF2: Receiver Configuration Register 2.....................................................................
MAINT0: Maintenance Function Control Register 0......................................................
MAINT1: Maintenance Function Control Register 1......................................................
MAINT2: Maintenance Function Control Register 2......................................................
MAINT3: Maintenance Function Control Register 3......................................................
MAINT4: Maintenance Function Control Register 4......................................................
MAINT5: Maintenance Function Control Register 5......................................................
MAINT6: Maintenance Function Control Register 6......................................................
6
10
21
21
21
22
22
22
22
23
23
24
28
30
30
31
32
36
40
42
43
44
44
44
44
45
45
46
46
47
47
47
48
48
49
49
50
50
50
51
51
51
December 12, 2005
IDT82V2042E
Table-42
Table-43
Table-44
Table-45
Table-46
Table-47
Table-48
Table-49
Table-50
Table-51
Table-52
Table-53
Table-54
Table-55
Table-56
Table-57
Table-58
Table-59
Table-60
Table-61
Table-62
Table-63
Table-64
Table-65
Table-66
Table-67
Table-68
Table-69
Table-70
Table-71
List of Tables
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
INTM0: Interrupt Mask Register 0 .................................................................................
INTM1: Interrupt Masked Register 1 .............................................................................
INTES: Interrupt Trigger Edge Select Register .............................................................
STAT0: Line Status Register 0 (real time status monitor).............................................
STAT1: Line Status Register 1 (real time status monitor).............................................
INTS0: Interrupt Status Register 0 ................................................................................
INTS1: Interrupt Status Register 1 ................................................................................
CNT0: Error Counter L-byte Register 0.........................................................................
CNT1: Error Counter H-byte Register 1 ........................................................................
Hardware Control Pin Summary ...................................................................................
Instruction Register Description ....................................................................................
Device Identification Register Description.....................................................................
TAP Controller State Description ..................................................................................
Absolute Maximum Rating ............................................................................................
Recommended Operation Conditions ...........................................................................
Power Consumption......................................................................................................
DC Characteristics ........................................................................................................
E1 Receiver Electrical Characteristics ..........................................................................
T1/J1 Receiver Electrical Characteristics......................................................................
E1 Transmitter Electrical Characteristics ......................................................................
T1/J1 Transmitter Electrical Characteristics..................................................................
Transmitter and Receiver Timing Characteristics .........................................................
Jitter Tolerance .............................................................................................................
Jitter Attenuator Characteristics ....................................................................................
JTAG Timing Characteristics ........................................................................................
Serial Interface Timing Characteristics .........................................................................
Non-Multiplexed Motorola Read Timing Characteristics ...............................................
Non-Multiplexed Motorola Write Timing Characteristics ...............................................
Non-Multiplexed Intel Read Timing Characteristics ......................................................
Non-Multiplexed Intel Write Timing Characteristics ......................................................
7
52
53
54
55
56
57
58
58
58
59
62
62
63
65
66
66
66
67
68
69
70
71
72
74
76
78
79
80
81
82
December 12, 2005
List of Figures
Figure-1
Figure-2
Figure-3
Figure-4
Figure-5
Figure-6
Figure-7
Figure-8
Figure-9
Figure-10
Figure-11
Figure-12
Figure-13
Figure-14
Figure-15
Figure-16
Figure-17
Figure-18
Figure-19
Figure-20
Figure-21
Figure-22
Figure-23
Figure-24
Figure-25
Figure-26
Figure-27
Figure-28
Figure-29
Figure-30
Figure-31
Figure-32
Figure-33
Figure-34
Figure-35
Figure-36
List of Figures
Block Diagram ................................................................................................................. 2
IDT82V2042E TQFP80 Package Pin Assignment .......................................................... 9
E1 Waveform Template Diagram .................................................................................. 19
E1 Pulse Template Test Circuit ..................................................................................... 19
DSX-1 Waveform Template .......................................................................................... 19
T1 Pulse Template Test Circuit ..................................................................................... 19
Receive Path Function Block Diagram .......................................................................... 24
Transmit/Receive Line Circuit ....................................................................................... 24
Monitoring Receive Line in Another Chip ...................................................................... 25
Monitor Transmit Line in Another Chip .......................................................................... 25
G.772 Monitoring Diagram ............................................................................................ 27
Jitter Attenuator ............................................................................................................. 28
LOS Declare and Clear ................................................................................................. 29
Analog Loopback .......................................................................................................... 33
Digital Loopback ............................................................................................................ 33
Remote Loopback ......................................................................................................... 34
Auto Report Mode ......................................................................................................... 36
Manual Report Mode ..................................................................................................... 37
TCLK Operation Flowchart ............................................................................................ 38
Serial Microcontroller Interface Function Timing ........................................................... 39
JTAG Architecture ......................................................................................................... 61
JTAG State Diagram ..................................................................................................... 64
Transmit System Interface Timing ................................................................................ 72
Receive System Interface Timing ................................................................................. 72
E1 Jitter Tolerance Performance .................................................................................. 73
T1/J1 Jitter Tolerance Performance .............................................................................. 74
E1 Jitter Transfer Performance ..................................................................................... 75
T1/J1 Jitter Transfer Performance ................................................................................ 76
JTAG Interface Timing .................................................................................................. 77
Serial Interface Write Timing ......................................................................................... 78
Serial Interface Read Timing with SCLKE=1 ................................................................ 78
Serial Interface Read Timing with SCLKE=0 ................................................................ 78
Non-Multiplexed Motorola Read Timing ........................................................................ 79
Non-Multiplexed Motorola Write Timing ........................................................................ 80
Non-Multiplexed Intel Read Timing ............................................................................... 81
Non-Multiplexed Intel Write Timing ............................................................................... 82
8
December 12, 2005
IDT82V2042E
A5
A4 / RPD2
A3
A2 / RPD1
A1 / PATT21
A0 / PATT20
D7 / PULS13
D6 / PULS12
D5 / PULS11
D4 / PULS10
D3 / PULS23
D2 / PULS22
D1 / PULS21
D0 / PULS20
SCLK / PATT11
DS / RD / SCLKE / PATT10
R/W / WR / SDI / LP21
SDO / LP20
CS / LP11
INT / LP10
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
IDT82V2042E PIN CONFIGURATIONS
VDDT1
61
40
VDDIO
TRING1
62
39
GNDIO
TTIP1
63
38
TCLK1
GNDT1
64
37
TDP1 / TD1
GNDR1
65
36
TDN1
RRING1
66
35
RCLK1
RTIP1
67
34
RDP1 / RD1
VDDR1
68
33
RDN1 / CV1
VDDA
69
32
LOS1
IC
70
31
VDDD
REF
71
30
MCLK
GNDA
72
29
GNDD
VDDR2
73
28
LOS2
RTIP2
74
27
RDN2 / CV2
RRING2
75
26
RDP2 / RD2
GNDR2
76
25
RCLK2
GNDT2
77
24
TDN2
TTIP2
78
23
TDP2 / TD2
TRING2
79
22
TCLK2
VDDT2
80
21
RST
13
14
15
16
17
18
19
20
TERM2
TERM1
RXTXM1
RXTXM0
JA1
JA0
MONT2
MONT1
THZ
GNDIO
12
8
VDDIO
11
7
IC
RCLKE
6
TDI
9
5
TDO
10
4
TCK
MODE0
3
MODE1
2
TRST
TMS
IDT82V2042E
1
1
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
Figure-2 IDT82V2042E TQFP80 Package Pin Assignment
IDT82V2042E PIN CONFIGURATIONS
9
December 12, 2005
IDT82V2042E
2
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
PIN DESCRIPTION
Table-1 Pin Description
Name
Type
Pin No.
Description
TTIP1
TTIP2
Analog
Output
63
78
TTIPn1/TRINGn: Transmit Bipolar Tip/Ring for Channel 1~2
These pins are the differential line driver outputs and can be set to high impedance state globally or individually. A logic high
on THZ pin turns all these pins into high impedance state. When THZ bit (TCF1, 03H...)2 is set to ‘1’, the TTIPn/TRINGn in
the corresponding channel is set to high impedance state.
In summary, these pins will become high impedance in the following conditions:
•
THZ pin is high: all TTIPn/TRINGn enter high impedance;
•
THZn bit is set to 1: the corresponding TTIPn/TRINGn become high impedance;
•
Loss of MCLK: all TTIPn/TRINGn pins become high impedance;·
•
Loss of TCLKn: the corresponding TTIPn/TRINGn become HZ (exceptions: Remote Loopback; Transmit internal pattern by MCLK);
•
Transmitter path power down: the corresponding TTIPn/TRINGn become high impedance;
•
After software reset; pin reset and power on: all TTIPn/TRINGn enter high impedance.
TRING1
TRING2
RTIP1
RTIP2
62
79
Analog
Input
RRING1
RRING2
TD1/TDP1
TD2/TDP2
67
74
RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 1~2
These signals are the differential receiver inputs.
66
75
I
37
23
36
24
TDN1
TDN2
TDn: Transmit Data for Channel 1~2
When the device is in single rail mode, the NRZ data to be transmitted is input on this pin. Data on TDn pin is sampled into
the device on the active edge of TCLKn and is encoded by AMI, HDB3 or B8ZS line code rules before being transmitted. In
this mode, TDNn should be connected to ground.
TDPn/TDNn: Positive/Negative Transmit Data
When the device is in dual rail mode, the NRZ data to be transmitted for positive/negative pulse is input on these pins. Data
on TDPn/TDNn pin is sampled into the device on the active edge of TCLKn. The active polarity is also selectable. Refer to
3.3.1 TRANSMIT PATH SYSTEM INTERFACE for details. The line code in dual rail mode is as follows:
TCLK1
TCLK2
I
38
22
TDPn
TDNn
Output Pulse
0
0
Space
0
1
Positive Pulse
1
0
Negative Pulse
1
1
Space
TCLKn: Transmit Clock for Channel 1~2
This pin inputs 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode transmit clock. The transmit data at TDn/TDPn or TDNn
is sampled into the device on the active edge of TCLKn. If TCLKn is missing3 and the TCLKn missing interrupt is not masked,
an interrupt will be generated.
Notes:
1. The footprint ‘n’ (n = 1~2) represents one of the two channels.
2. The name and address of the registers that contain the preceding bit. Only the address of channel 1 register is listed, the rest addresses are represented by ‘...’. Users can find
these omitted addresses in the Register Description section.
3. TCLKn missing: the state of TCLKn continues to be high level or low level over 70 MCLK cycles.
PIN DESCRIPTION
10
December 12, 2005
IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
Type
Pin No.
RD1/RDP1
RD2/RDP2
O
34
26
RDn: Receive Data output for Channel 1~2
In single rail mode, this pin outputs NRZ data. The data is decoded according to AMI, HDB3 or B8ZS line code rules.
33
27
CVn: Code Violation indication
In single rail mode, the BPV/CV errors in received data stream will be reported by driving the CVn pin to high level for a full
clock cycle. B8ZS/HDB3 line code violation can be indicated if the B8ZS/HDB3 decoder is enabled. When AMI decoder is
selected, bipolar violation will be indicated.
In hardware control mode, the EXZ, BPV/CV errors in received data stream are always monitored by the CVn pin if single rail
mode is chosen.
CV1/RDN1
CV2/RDN2
Description
RDPn/RDNn: Positive/Negative Receive Data output for Channel 1~2
In dual rail mode, these pins output the re-timed NRZ data when CDR is enabled, or directly outputs the raw RZ slicer data
if CDR is bypassed.
Active edge and level select:
Data on RDPn/RDNn or RDn is clocked with either the rising or the falling edge of RCLKn. The active polarity is also selectable. Refer to 3.4.8 RECEIVE PATH SYSTEM INTERFACE for details.
RCLK1
RCLK2
O
35
25
RCLKn: Receive Clock output for Channel 1~2
This pin outputs 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode receive clock. Under LOS conditions with AIS enabled
(bit AISE=1), RCLKn is derived from MCLK.
In clock recovery mode, this signal provides the clock recovered from the RTIPn/RRINGn signal. The receive data (RDn in
single rail mode or RDPn and RDNn in dual rail mode) is clocked out of the device on the active edge of RCLKn.
If clock recovery is bypassed, RCLKn is the exclusive OR (XOR) output of the dual rail slicer data RDPn and RDNn. This signal
can be used in applications with external clock recovery circuitry.
MCLK
I
30
MCLK: Master Clock input
A built-in clock system that accepts selectable 2.048 MHz reference for E1 operating mode and 1.544 MHz reference for T1/
J1 operating mode. This reference clock is used to generate several internal reference signals:
•
Timing reference for the integrated clock recovery unit.
•
Timing reference for the integrated digital jitter attenuator.
•
Timing reference for microcontroller interface.
•
Generation of RCLKn signal during a loss of signal condition.
•
Reference clock to transmit All Ones, all zeros, PRBS/QRSS pattern as well as activate or deactivate Inband Loopback code if MCLK is selected as the reference clock. Note that for ATAO and AIS, MCLK is always used as the reference clock.
•
Reference clock during Transmit All Ones (TAO) condition or sending PRBS/QRSS in hardware control mode.
The loss of MCLK will turn TTIP/TRING into high impedance status.
LOS1
LOS2
O
32
28
LOSn: Loss of Signal Output for Channel 1~2
These pins are used to indicate the loss of received signals. When LOSn pin becomes high, it indicates the loss of received
signal in channel n. The LOS pin will become low automatically when valid received signal is detected again. The criteria of
loss of signal are described in 3.6 LOS AND AIS DETECTION.
REF
I
71
REF: reference resister
An external resistor (3kΩ, 1%) is used to connect this pin to ground to provide a standard reference current for internal circuit.
PIN DESCRIPTION
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DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
Type
Pin No.
MODE1
MODE0
I
9
10
Description
MODE[1:0]: operation mode of control interface select
The level on this pin determines which control mode is used to control the device as follows:
MODE[1:0]
•
•
•
Control Interface mode
00
Hardware interface
01
Serial Microcontroller Interface
10
Motorola non-multiplexed
11
Intel non-multiplexed
The serial microcontroller interface consists of CS, SCLK, SCLKE, SDI, SDO and INT pins. SCLKE is used for the
selection of the active edge of SCLK.
The parallel non-multiplexed microcontroller interface consists of CS, A[5:0], D[7:0], DS/RD, R/W/WR and INT pins.
(Refer to 3.12 MICROCONTROLLER INTERFACES for details)
Hardware interface consists of PULSn[3:0], THZ, RCLKE, LPn[1:0], PATTn[1:0], JA[1:0], MONTn, TERMn, RPDn,
MODE[1:0] and RXTXM[1:0] (n=1, 2).
RCLKE
I
11
RCLKE: the active edge of RCLKn select
In hardware control mode, this pin selects the active edge of RCLKn
•
L= update RDPn/RDNn on the rising edge of RCLKn
•
H= update RDPn/RDNn on the falling edge of RCLKn
In software control mode, this pin should be connected to GNDIO.
RXTXM1
RXTXM0
I
14
15
RXTXM[1:0]: Receive and transmit path operation mode select
In hardware control mode, these pins are used to select the single rail or dual rail operation modes as well as AMI or HDB3/
B8ZS line coding:
•
00= single rail with HDB3/B8ZS coding
•
01= single rail with AMI coding
•
10= dual rail interface with CDR enabled
•
11= slicer mode (dual rail interface with CDR disabled)
In software control mode, these pins should be connected to ground.
CS
I
42
CS: Chip Select
In serial or parallel microcontroller interface mode, this is the active low enable signal. A low level on this pin enables serial
or parallel microcontroller interface.
LP11/LP10: Loopback mode select for channel 1
When the chip is configured by hardware, this pin is used to select loopback operation modes for channel 1 (Inband Loopback
is not provided in hardware control mode).
•
00 = no loopback
•
01 = analog loopback
•
10 = digital loopback
•
11 = remote loopback
LP11
INT
O
41
INT: Interrupt Request
In software control mode, this pin outputs the general interrupt request for all interrupt sources. If INTM_GLB bit (GCF, 20H)
is set to ‘1’, all the interrupt sources will be masked. These interrupt sources can be masked individually via registers (INTM0,
13H...) and (INTM1, 14H...). The interrupt status is reported via the registers (INTCH, 21H), (INTS0, 18H...) and (INTS1,
19H...).
Output characteristics of this pin can be defined to be push-pull (active high or active low) or open-drain (active low) by setting
bits INT_PIN[1:0] (GCF, 20H)
LP10
I
PIN DESCRIPTION
LP11/LP10: Loopback mode select for channel 1
See above LP11.
12
December 12, 2005
IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
Type
Pin No.
Description
SCLK
I
46
SCLK: Shift Clock
In serial microcontroller interface mode, this signal is the shift clock for the serial interface. Configuration data on SDI pin is
sampled on the rising edge of SCLK. Configuration and status data on SDO pin is clocked out of the device on the rising edge
of SCLK if SCLKE pin is low, or on the falling edge of SCLK if SCLKE pin is high.
In parallel non-multiplexed interface mode, this pin should be connected to ground.
PATT11
SCLKE
PATT11/PATT10: Transmit pattern select for channel 1
In hardware control mode, this pin selects the transmit pattern
•
00 = normal
•
01= All Ones
•
10= PRBS
•
11= transmitter power down
I
45
SCLKE: Serial Clock Edge Select
In serial microcontroller interface mode, this signal selects the active edge of SCLK for outputting SDO. The output data is
valid after some delay from the active clock edge. It can be sampled on the opposite edge of the clock. The active clock edge
which clocks the data out of the device is selected as shown below:
SCLKE
SCLK
Low
Rising edge is the active edge.
High
Falling edge is the active edge.
DS
DS: Data Strobe
In Motorola parallel non-multiplexed interface mode, this signal is the data strobe of the parallel interface. In a write operation
(R/W = 0), the data on D[7:0] is sampled into the device. In a read operation (R/W = 1), the data is driven to D[7:0] by the
device.
RD
RD: Read Strobe
In Intel parallel non-Multiplexed interface mode, the data is driven to D[7:0] by the device during low level of RD in a read operation.
PATT11/PATT10: Transmit pattern select for channel 1
See above PATT11.
PATT10
SDI
I
44
SDI: Serial Data Input
In serial microcontroller interface mode, this signal is the input data to the serial interface. Configuration data at SDI pin is sampled by the device on the rising edge of SCLK.
R/W
R/W: Read/Write Select
In Motorola parallel non-multiplexed interface mode, this pin is low for write operation and high for read operation.
WR
WR: Write Strobe
In Intel parallel non-multiplexed interface mode, this pin is asserted low by the microcontroller to initiate a write cycle. The data
on D[7:0] is sampled into the device in a write operation.
LP21
LP21/LP20: loopback mode select for channel 2
When the chip is configured by hardware, this pin is used to select loopback operation modes for channel 2 (Inband Loopback
is not provided in hardware control mode).
•
00 = no loopback
•
01 = analog loopback
•
10 = digital loopback
•
11 = remote loopback
PIN DESCRIPTION
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December 12, 2005
IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
Type
Pin No.
Description
SDO
O
43
SDO: Serial Data Output
In serial microcontroller interface mode, this signal is the output data of the serial interface. Configuration or Status data at
SDO pin is clocked out of the device on the rising edge of SCLK if SCLKE pin is low, or on the falling edge of SCLK if SCLKE
pin is high.
In parallel non-multiplexed interface mode, this pin should be left open.
LP20
I
D7
I/O
PULS13
I
D6
I/O
PULS12
I
D5
I/O
PULS11
I
D4
I/O
PULS10
I
D3
I/O
PULS23
I
D2
I/O
PULS22
I
D1
I/O
PULS21
I
PIN DESCRIPTION
LP21/LP20: loopback mode select for channel 2
See above LP21.
54
D7: Data Bus bit7
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
PULS1[3:0]: these pins are used to select the following functions for channel 1 in hardware control mode:
•
T1/E1/J1 mode
•
Transmit pulse template
•
Internal termination impedance (75Ω/120Ω/100Ω/110Ω)
Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
Note that PULS13 to PULS10 determine the T1/E1/J1 mode of common block.
53
D6: Data Bus bit6
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
52
D5: Data Bus bit5
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
See above.
See above.
51
D4: Data Bus bit4
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
50
D3: Data Bus bit3
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
See above.
PULS2[3:0]: these pins are used to select the following functions for channel 2 in hardware control mode:·
•
T1/E1/J1 mode
•
Transmit pulse template
•
Internal termination impedance (75 Ω/120 Ω/100 Ω/110 Ω)
Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
49
D2: Data Bus bit2
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
48
D1: Data Bus bit1
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
See above.
See above.
14
December 12, 2005
IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
Type
Pin No.
D0
I/O
47
D0: Data Bus bit0
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
Description
PULS20
I
A5
I
60
A5: Address Bus bit5
In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground.
See above.
In Hardware mode, this pin has to be tied to GND.
A4
I
59
RPD2
A4: Address Bus bit4
In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground.
RPD2: Power down control for receiver2 in hardware control mode
0= receiver 2 normal operation
1= receiver 2 power down
A3
I
58
A3: Address Bus bit3
In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground.
A2
I
57
A2: Address Bus bit2
In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground.
In Hardware mode, this pin has to be tied to GND.
RPD1
A1
RPD1: Power down control for receiver1 in hardware control mode
0= receiver 1 normal operation
1= receiver 1 power down
I
56
PATT21
A0
PATT21/PATT20: Transmit pattern select for channel 2
In hardware control mode, this pin selects the transmit pattern
00 = normal
01= All Ones
10= PRBS
11= transmitter power down
I
55
A0: Address Bus bit 0
In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground.
See above
PATT20
TERM1
TERM2
A1: Address Bus bit1
In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground.
I
PIN DESCRIPTION
13
12
TERMn: Selects internal or external impedance matching for channel 1 and channel 2 in hardware control mode
0 = ternary interface with internal impedance matching network
1 = ternary interface with external impedance matching network in E1 mode; ternary interface with external impedance matching network for receiver and ternary interface with internal impedance matching network for transmitter in T1/J1 mode.
(This applies to ZB die revision only.)
In software control mode, this pin should be connected to ground.
15
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IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
Type
Pin No.
Description
JA1
I
16
JA[1:0]: Jitter attenuation position, bandwidth and the depth of FIFO select for channel 1 and channel 2 (only used
in hardware control mode)
•
00 = JA is disabled
•
01= JA in receiver, broad bandwidth, FIFO=64 bits
•
10 = JA in receiver, narrow bandwidth, FIFO=128 bits
•
11= JA in transmitter, narrow bandwidth, FIFO=128 bits
In software control mode, this pin should be connected to ground.
JA0
I
17
See above.
MONT2
I
18
MONT2: Receive Monitor gain select for channel 2
In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver:
0= 0dB
1= 26dB
In software control mode, this pin should be connected to ground.
MONT1
I
19
MONT1: Receive Monitor gain select for channel 1
In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver:
0= 0dB
1= 26dB
In software control mode, this pin should be connected to ground.
RST
I
21
RST: Hardware Reset
The chip is forced to reset state if a low signal is input on this pin for more than 100ns. MCLK must be active during reset.
THZ
I
20
THZ: Transmitter Driver High Impedance Enable
This signal enables or disables all transmitter drivers on a global basis. A low level on this pin enables the driver while a high
level on this pin places all drivers in high impedance state. Note that the functionality of the internal circuits is not affected by
this signal.
JTAG Signals
TRST
I
Pullup
1
TRST: JTAG Test Port Reset
This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resistor. To ensure deterministic operation of the test logic, TMS should be held high while the signal applied to TRST changes from low to high.
For normal signal processing, this pin should be connected to ground.
If JTAG is not used, this pin must be connected to ground.
TMS
I
Pullup
2
TMS: JTAG Test Mode Select
This pin is used to control the test logic state machine and is sampled on the rising edge of TCK. TMS has an internal pullup resistor.
If JTAG is not used, this pin may be left unconnected.
TCK
I
3
TCK: JTAG Test Clock
This is the input clock for JTAG. The data on TDI and TMS are clocked into the device on the rising edge of TCK while the
data on TDO is clocked out of the device on the falling edge of TCK. When TCK is idle at low state, all the stored-state devices
contained in the test logic will retain their state indefinitely.
If JTAG is not used, this pin may be left unconnected.
TDO
O
4
TDO: JTAG Test Data Output
This output pin is high impedance normally and is used for reading all the serial configuration and test data from the test logic.
The data on TDO is clocked out of the device on the falling edge of TCK.
If JTAG is not used, this pin should be left unconnected.
TDI
I
Pullup
5
TDI: JTAG Test Data Input
This pin is used for loading instructions and data into the test logic and has an internal pull-up resistor. The data on TDI is
clocked into the device on the rising edge of TCK.
If JTAG is not used, this pin may be left unconnected.
VDDIO
-
7,40
3.3 V I/O power supply
GNDIO
-
8,39
I/O ground
Power Supplies and Grounds
PIN DESCRIPTION
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IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
Type
Pin No.
VDDT1
VDDT2
-
61
80
3.3 V power supply for transmitter driver
Description
GNDT1
GNDT2
-
64
77
Analog ground for transmitter driver
VDDR1
VDDR2
-
68
73
Power supply for receive analog circuit
GNDR1
GNDR2
-
65
76
Analog ground for receive analog circuit
VDDD
-
31
3.3V digital core power supply
GNDD
-
29
Digital core ground
VDDA
-
69
Analog core circuit power supply
GNDA
-
72
Analog core circuit ground
IC
-
70
IC: Internal Connection
Internal Use. This pin should be left open in normal operation.
IC
-
6
IC: Internal Connection
Internal Use. This pin should be connected to ground in normal operation.
Others
PIN DESCRIPTION
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DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
3
FUNCTIONAL DESCRIPTION
3.1
CONTROL MODE SELECTION
and TDNn can be selected by the TD_INV bit (TCF0, 04H...). In hardware
control mode, the falling edge of TCLKn and the active high of transmit data
are always used.
The transmit data from the system side can be provided in two different
ways: Single Rail and Dual Rail. In Single Rail mode, only TDn pin is used
for transmitting data and the T_MD[1] bit (TCF0, 04H...) should be set to
‘0’. In Dual Rail Mode, both TDPn pin and TDNn pin are used for transmitting
data, the T_MD[1] bit (TCF0, 04H...) should be set to ‘1’.
The IDT82V2042E can be configured by software or by hardware. The
software control mode supports Serial Control Interface, Motorola non-Multiplexed Control Interface and Intel non-Multiplexed Control Interface. The
Control mode is selected by MODE1 and MODE0 pins as follows:
3.3.2
Control Interface Mode
•
00
Hardware interface
01
Serial Microcontroller Interface.
10
Parallel -non-Multiplexed -Motorola Interface
11
Parallel -non-Multiplexed -Intel Interface
In Single Rail mode, when T1/J1 mode is selected, the Encoder can be
selected to be a B8ZS encoder or an AMI encoder by setting T_MD[0] bit
(TCF0, 04H...).
In Single Rail mode, when E1 mode is selected, the Encoder can be configured to be a HDB3 encoder or an AMI encoder by setting T_MD[0] bit
(TCF0, 04H...).
The serial microcontroller Interface consists of CS, SCLK, SCLKE,
SDI, SDO and INT pins. SCLKE is used for the selection of active
edge of SCLK.
The parallel non-Multiplexed microcontroller Interface consists of
CS, A[5:0], D[7:0], DS/RD, R/W/WR and INT pins.
Hardware interface consists of PULSn[3:0], THZ, RCLKE, LPn[1:0],
PATTn[1:0], JA[1:0], MONTn, TERMn, RPDn, MODE[1:0] and
RXTXM[1:0] (n=1, 2). Refer to 5 HARDWARE CONTROL PIN SUMMARY for details about hardware control.
•
•
3.2
In both T1/J1 mode and E1 mode, when Dual Rail mode is selected (bit
T_MD[1] is ‘1’), the Encoder is by-passed. In Dual Rail mode, a logic ‘1’ on
the TDPn pin and a logic ‘0’ on the TDNn pin results in a negative pulse on
the TTIPn/TRINGn; a logic ‘0’ on TDPn pin and a logic ‘1’ on TDNn pin
results in a positive pulse on the TTIPn/TRINGn. If both TDPn and TDNn
are high or low, the TTIPn/TRINGn outputs a space (Refer to TDn/TDPn,
TDNn Pin Description).
In hardware control mode, the operation mode of receive and transmit
path can be selected by setting RXTXM1 and RXTXM0 pins on a global
basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
T1/E1/J1 MODE SELECTION
When the chip is configured by software, T1/E1/J1 mode is selected by
the T1E1 bit (GCF, 20H). In E1 application, the T1E1 bit (GCF, 20H) should
be set to ‘0’. In T1/J1 application, the T1E1 bit should be set to ‘1’.
3.3.3
In software control mode, the pulse shape can be selected by setting
the related registers.
TRANSMIT PATH
In hardware control mode, the pulse shape can be selected by setting
PULSn[3:0] pins on a per channel basis. Refer to 5 HARDWARE CONTROL
PIN SUMMARY for details.
The transmit path of each channel of IDT82V2042E consists of an
Encoder, an optional Jitter Attenuator, a Waveform Shaper, a Line Driver
and a Programmable Transmit Termination.
3.3.1
3.3.3.1 Preset Pulse Templates
TRANSMIT PATH SYSTEM INTERFACE
For E1 applications, the pulse shape is shown in Figure-3 according to
the G.703 and the measuring diagram is shown in Figure-4. In internal
impedance matching mode, if the cable impedance is 75 Ω, the PULS[3:0]
bits (TCF1, 05H...) should be set to ‘0000’; if the cable impedance is 120
Ω, the PULS[3:0] bits (TCF1, 05H...) should be set to ‘0001’. In external
impedance matching mode, for both E1/75 Ω and E1/120 Ω cable impedance, PULS[3:0] should be set to ‘0001’.
The transmit path system interface consists of TCLKn pin, TDn/TDPn
pin and TDNn pin. In E1 mode, TCLKn is a 2.048 MHz clock. In T1/J1 mode,
TCLKn is a 1.544 MHz clock. If TCLKn is missing for more than 70 MCLK
cycles, an interrupt will be generated if it is not masked.
Transmit data is sampled on the TDn/TDPn and TDNn pins by the active
edge of TCLKn. The active edge of TCLKn can be selected by the
TCLK_SEL bit (TCF0, 04H...). And the active level of the data on TDn/TDPn
FUNCTIONAL DESCRIPTION
PULSE SHAPER
The IDT82V2042E provides two ways of manipulating the pulse shape
before sending it. One is to use preset pulse templates; the other is to use
user-programmable arbitrary waveform template.
When the chip is configured by hardware, T1/E1/J1 mode is selected
by PULSn[3:0] pins on a per channel basis. These pins also determine
transmit pulse template and internal termination impedance. Refer to 5
HARDWARE CONTROL PIN SUMMARY for details.
3.3
ENCODER
18
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IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
grades, and there are five pulse templates used for each of the cable length.
The pulse template is selected by PULS[3:0] bits (TCF1, 05H...).
1 .2 0
1 .0 0
1.2
1
0 .6 0
0.8
Normalized Amplitude
Normalized Amplitude
0 .8 0
0 .4 0
0 .2 0
0 .0 0
- 0 .2 0
-0 .6
- 0 .4
- 0 .2
0
0 .2
0 .4
0 .6
0.6
0.4
0.2
0
-0.2
T im e in U n it In te rv a ls
-0.4
Figure-3 E1 Waveform Template Diagram
-0.6
0
250
500
750
1000
1250
Time (ns)
Figure-5 DSX-1 Waveform Template
TTIPn
IDT82V2042E
RLOAD
VOUT
TTIPn
TRINGn
Cable
IDT82V2042E
Note: 1. For RLOAD = 75 Ω (nom), Vout (Peak)=2.37V (nom)
2. For RLOAD =120 Ω (nom), Vout (Peak)=3.00V (nom)
TRINGn
Figure-4 E1 Pulse Template Test Circuit
Note: RLOAD = 100 Ω ± 5%
Figure-6 T1 Pulse Template Test Circuit
For T1 applications, the pulse shape is shown in Figure-5 according to
the T1.102 and the measuring diagram is shown in Figure-6. This also
meets the requirement of G.703, 2001. The cable length is divided into five
FUNCTIONAL DESCRIPTION
RLOAD VOUT
For J1 applications, the PULS[3:0] (TCF1, 05H...) should be set to
‘0111’. Table-10 lists these values.
19
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DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
against the standard pulse amplitude if needed. For different pulse shapes,
the value of SCAL[5:0] bits and the scaling percentage ratio are different.
The following eight tables list these values.
3.3.3.2 User-Programmable Arbitrary Waveform
When the PULS[3:0] bits are set to ‘11xx’, user-programmable arbitrary
waveform generator mode can be used in the corresponding channel. This
allows the transmitter performance to be tuned for a wide variety of line condition or special application.
Do the followings step by step, the desired waveform can be programmed, based on the selected waveform template:
(1).Select the UI by UI[1:0] bits (TCF3, 07H...)
(2).Specify the sample address in the selected UI by SAMP [3:0] bits
(TCF3, 07H...)
(3).Write sample data to WDAT[6:0] bits (TCF4, 08H...). It contains the
data to be stored in the RAM, addressed by the selected UI and the
corresponding sample address.
(4).Set the RW bit (TCF3, 07H...) to ‘0’ to implement writing data to RAM,
or to ‘1’ to implement read data from RAM
(5).Implement the Read from RAM/Write to RAM by setting the DONE
bit (TCF3, 07H...)
Each pulse shape can extend up to 4 UIs (Unit Interval), addressed by
UI[1:0] bits (TCF3, 07H...) and each UI is divided into 16 sub-phases,
addressed by the SAMP[3:0] bits (TCF3, 07H...). The pulse amplitude of
each phase is represented by a binary byte, within the range from +63 to 63, stored in WDAT[6:0] bits (TCF4, 08H...) in signed magnitude form. The
most positive number +63 (D) represents the maximum positive amplitude
of the transmit pulse while the most negative number -63 (D) represents the
maximum negative amplitude of the transmit pulse. Therefore, up to 64
bytes are used. For each channel, a 64 bytes RAM is available.
There are eight standard templates which are stored in an on-chip ROM.
User can select one of them as reference and make some changes to get
the desired waveform.
Repeat the above steps until all the sample data are written to or read
from the internal RAM.
(6).Write the scaling data to SCAL[5:0] bits (TCF2, 06H...) to scale the
amplitude of the waveform based on the selected standard pulse
amplitude
User can change the wave shape and the amplitude to get the desired
pulse shape. In order to do this, firstly, users can choose a set of waveform
value from the following eight tables, which is the most similar to the desired
pulse shape. Table-2, Table-3, Table-4, Table-5, Table-6, Table-7, Table-8
and Table-9 list the sample data and scaling data of each of the eight templates. Then modify the corresponding sample data to get the desired transmit pulse shape.
When more than one UI is used to compose the pulse template, the overlap of two consecutive pulses could make the pulse amplitude overflow
(exceed the maximum limitation) if the pulse amplitude is not set properly.
This overflow is captured by DAC_OV_IS bit (INTS1, 19H...), and, if
enabled by the DAC_OV_IM bit (INTM1, 14H...), an interrupt will be generated.
Secondly, through the value of SCAL[5:0] bits increased or decreased
by 1, the pulse amplitude can be scaled up or down at the percentage ratio
FUNCTIONAL DESCRIPTION
20
December 12, 2005
IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
The following tables give all the sample data based on the preset pulse
templates in detail for reference. For preset pulse templates, scaling up/
down against the pulse amplitude is not supported.
1.Table-2 Transmit Waveform Value for E1 75 Ω
2.Table-3 Transmit Waveform Value for E1 120 Ω
3.Table-4 Transmit Waveform Value for T1 0~133 ft
4.Table-5 Transmit Waveform Value for T1 133~266 ft
5.Table-6 Transmit Waveform Value for T1 266~399 ft
6.Table-7 Transmit Waveform Value for T1 399~533 ft
7.Table-8 Transmit Waveform Value for T1 533~655 ft
8.Table-9 Transmit Waveform Value for J1 0~655 ft
Table-3 Transmit Waveform Value For E1 120 Ohm
Table-2 Transmit Waveform Value For E1 75 Ohm
Sample
UI 1
UI 2
UI 3
UI 4
1
0000000
0000000
0000000
0000000
2
0000000
0000000
0000000
0000000
3
0000000
0000000
0000000
0000000
4
0001111
0000000
0000000
0000000
5
0111100
0000000
0000000
0000000
6
0111100
0000000
0000000
0000000
7
0111100
0000000
0000000
0000000
8
0111100
0000000
0000000
0000000
9
0111100
0000000
0000000
0000000
10
0111100
0000000
0000000
0000000
Sample
UI 1
UI 2
UI 3
UI 4
1
0000000
0000000
0000000
0000000
11
0111100
0000000
0000000
0000000
2
0000000
0000000
0000000
0000000
12
0111100
0000000
0000000
0000000
3
0000000
0000000
0000000
0000000
13
0000000
0000000
0000000
0000000
4
0001100
0000000
0000000
0000000
14
0000000
0000000
0000000
0000000
5
0110000
0000000
0000000
0000000
15
0000000
0000000
0000000
0000000
6
0110000
0000000
0000000
0000000
16
0000000
0000000
0000000
0000000
7
0110000
0000000
0000000
0000000
8
0110000
0000000
0000000
0000000
9
0110000
0000000
0000000
0000000
10
0110000
0000000
0000000
0000000
11
0110000
0000000
0000000
0000000
12
0110000
0000000
0000000
0000000
13
0000000
0000000
0000000
0000000
14
0000000
0000000
0000000
0000000
15
0000000
0000000
0000000
0000000
16
0000000
0000000
0000000
0000000
SCAL[5:0] = 100001 (default), One step change of this value of SCAL[5:0]
results in 3% scaling up/down against the pulse amplitude.
Table-4 Transmit Waveform Value For T1 0~133 ft
SCAL[5:0] = 100001 (default), One step change of this value of SCAL[5:0]
results in 3% scaling up/down against the pulse amplitude.
Sample
UI 1
UI 2
UI 3
UI 4
1
0010111
1000010
0000000
0000000
2
0100111
1000001
0000000
0000000
3
0100111
0000000
0000000
0000000
4
0100110
0000000
0000000
0000000
5
0100101
0000000
0000000
0000000
6
0100101
0000000
0000000
0000000
7
0100101
0000000
0000000
0000000
8
0100100
0000000
0000000
0000000
9
0100011
0000000
0000000
0000000
10
1001010
0000000
0000000
0000000
11
1001010
0000000
0000000
0000000
12
1001001
0000000
0000000
0000000
13
1000111
0000000
0000000
0000000
14
1000101
0000000
0000000
0000000
15
1000100
0000000
0000000
0000000
16
1000011
0000000
0000000
0000000
1
SCAL[5:0] = 110110 (default), One step change of this value of SCAL[5:0]
results in 2% scaling up/down against the pulse amplitude.
1. In T1 mode, when arbitrary pulse for short haul application is configured,
users should write ‘110110’ to SCAL[5:0] bits if no scaling is required.
FUNCTIONAL DESCRIPTION
21
December 12, 2005
IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
Table-5 Transmit Waveform Value For T1 133~266 ft
Sample
UI 1
UI 2
1
0011011
1000011
2
0101110
1000010
3
0101100
1000001
4
0101010
0000000
5
0101001
6
0101000
7
8
UI 3
Table-7 Transmit Waveform Value For T1 399~533 ft
UI 4
Sample
UI 1
UI 2
UI 3
UI 4
0000000
0000000
1
0100000
1000011
0000000
0000000
0000000
0000000
2
0111011
1000010
0000000
0000000
0000000
0000000
3
0110101
1000001
0000000
0000000
0000000
0000000
4
0101111
0000000
0000000
0000000
0000000
0000000
0000000
5
0101110
0000000
0000000
0000000
0000000
0000000
0000000
6
0101101
0000000
0000000
0000000
0100111
0000000
0000000
0000000
7
0101100
0000000
0000000
0000000
0100110
0000000
0000000
0000000
8
0101010
0000000
0000000
0000000
9
0100101
0000000
0000000
0000000
9
0101000
0000000
0000000
0000000
10
1010000
0000000
0000000
0000000
10
1011000
0000000
0000000
0000000
11
1001111
0000000
0000000
0000000
11
1011000
0000000
0000000
0000000
12
1001101
0000000
0000000
0000000
12
1010011
0000000
0000000
0000000
13
1001010
0000000
0000000
0000000
13
1001100
0000000
0000000
0000000
14
1001000
0000000
0000000
0000000
14
1001000
0000000
0000000
0000000
15
1000110
0000000
0000000
0000000
15
1000110
0000000
0000000
0000000
16
1000100
0000000
0000000
0000000
16
1000100
0000000
0000000
0000000
See Table-4
See Table-4
Table-6 Transmit Waveform Value For T1 266~399 ft
Sample
UI 1
UI 2
UI 3
Table-8 Transmit Waveform Value For T1 533~655 ft
UI 4
Sample
UI 1
UI 2
UI 3
UI 4
1
0011111
1000011
0000000
0000000
1
0100000
1000011
0000000
0000000
2
0110100
1000010
0000000
0000000
2
0111111
1000010
0000000
0000000
3
0101111
1000001
0000000
0000000
3
0111000
1000001
0000000
0000000
4
0101100
0000000
0000000
0000000
4
0110011
0000000
0000000
0000000
5
0101011
0000000
0000000
0000000
5
0101111
0000000
0000000
0000000
6
0101010
0000000
0000000
0000000
6
0101110
0000000
0000000
0000000
7
0101001
0000000
0000000
0000000
7
0101101
0000000
0000000
0000000
8
0101000
0000000
0000000
0000000
8
0101100
0000000
0000000
0000000
9
0100101
0000000
0000000
0000000
9
0101001
0000000
0000000
0000000
10
1010111
0000000
0000000
0000000
10
1011111
0000000
0000000
0000000
11
1010011
0000000
0000000
0000000
11
1011110
0000000
0000000
0000000
12
1010000
0000000
0000000
0000000
12
1010111
0000000
0000000
0000000
13
1001011
0000000
0000000
0000000
13
1001111
0000000
0000000
0000000
14
1001000
0000000
0000000
0000000
14
1001001
0000000
0000000
0000000
15
1000110
0000000
0000000
0000000
15
1000111
0000000
0000000
0000000
16
1000100
0000000
0000000
0000000
16
1000100
0000000
0000000
0000000
See Table-4
FUNCTIONAL DESCRIPTION
See Table-4
22
December 12, 2005
IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
to ‘1’, the internal impedance matching circuit will be disabled. In this case,
the external impedance matching circuit will be used to realize the impedance matching. For T1/J1 mode, the external impedance matching circuit
for the transmitter is not supported.
Table-9 Transmit Waveform Value For J1 0~655 ft
Sample
UI 1
UI 2
UI 3
UI 4
1
0010111
1000010
0000000
0000000
2
0100111
1000001
0000000
0000000
3
0100111
0000000
0000000
0000000
4
0100110
0000000
0000000
0000000
5
0100101
0000000
0000000
0000000
6
0100101
0000000
0000000
0000000
7
0100101
0000000
0000000
0000000
8
0100100
0000000
0000000
0000000
9
0100011
0000000
0000000
0000000
10
1001010
0000000
0000000
0000000
11
1001010
0000000
0000000
0000000
12
1001001
0000000
0000000
0000000
13
1000111
0000000
0000000
0000000
14
1000101
0000000
0000000
0000000
15
1000100
0000000
0000000
0000000
16
1000011
0000000
0000000
0000000
Figure-8 shows the appropriate external components to connect with
the cable for one channel. Table-10 is the list of the recommended impedance matching for transmitter.
In hardware control mode, TERMn pin can be used to select impedance
matching for both receiver and transmitter on a per channel basis. If TERMn
pin is low, internal impedance network will be used. If TERMn pin is high,
external impedance network will be used in E1 mode, or external impedance network for receiver and internal impedance network for transmitter
will be used in T1/J1 mode. (This applies to ZB die revision only). When
internal impedance network is used, PULSn[3:0] pins should be set to
select the specific internal impedance in the corresponding channel. Refer
to 5 HARDWARE CONTROL PIN SUMMARY for details.
The TTIPn/TRINGn can also be turned into high impedance globally by
pulling THZ pin to high or individually by setting the THZ bit (TCF1, 05H...)
to ‘1’. In this state, the internal transmit circuits are still active.
In hardware control mode, TTIPn/TRINGn pins can be turned into high
impedance globally by pulling THZ pin to high. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
SCAL[5:0] = 110110 (default), One step change of this value of SCAL[5:0]
results in 2% scaling up/down against the pulse amplitude.
3.3.4
Besides, in the following cases, TTIPn/TRINGn will also become high
impedance:
•
Loss of MCLK;
•
Loss of TCLKn (exceptions: Remote Loopback; Transmit internal
pattern by MCLK);
•
Transmit path power down;
•
After software reset; pin reset and power on.
TRANSMIT PATH LINE INTERFACE
The transmit line interface consists of TTIPn and TRINGn pins. The
impedance matching can be realized by the internal impedance matching
circuit or the external impedance matching circuit. If T_TERM[2] is set to
‘0’, the internal impedance matching circuit will be selected. In this case,
the T_TERM[1:0] bits (TERM, 02H...) can be set to choose 75 Ω, 100 Ω,
110 Ω or 120 Ω internal impedance of TTIPn/TRINGn. If T_TERM[2] is set
Table-10 Impedance Matching for Transmitter
Cable Configuration
Internal Termination
T_TERM[2:0]
PULS[3:0]
RT
T_TERM[2:0]
PULS[3:0]
RT
0Ω
1XX
0001
9.4 Ω
E1/75 Ω
000
0000
E1/120 Ω
001
0001
T1/0~133 ft
010
0010
T1/133~266 ft
0011
T1/266~399 ft
0100
T1/399~533 ft
0101
T1/533~655 ft
J1/0~655 ft
External Termination
0001
-
-
-
0110
011
0111
Note: The precision of the resistors should be better than ± 1%
3.3.5
In hardware control mode, the transmit path can be powered down by
setting PATTn[1:0] pins to ‘11’ on a per channel basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
TRANSMIT PATH POWER DOWN
The transmit path can be powered down individually by setting the
T_OFF bit (TCF0, 04H...) to ‘1’. In this case, the TTIPn/TRINGn pins are
turned into high impedance.
FUNCTIONAL DESCRIPTION
23
December 12, 2005
IDT82V2042E
3.4
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
RECEIVE PATH
is set to ‘0’, the internal impedance matching circuit will be selected. In this
case, the R_TERM[1:0] bits (TERM, 02H...) can be set to choose 75 Ω, 100
Ω, 110 Ω or 120 Ω internal impedance of RTIPn/RRINGn. If R_TERM[2]
is set to ‘1’, the internal impedance matching circuit will be disabled. In this
case, the external impedance matching circuit will be used to realize the
impedance matching.
The receive path consists of Receive Internal Termination, Monitor
Gain, Amplitude/Wave Shape Detector, Digital Tuning Controller, Adaptive
Equalizer, Data Slicer, CDR (Clock & Data Recovery), Optional Jitter Attenuator, Decoder and LOS/AIS Detector. Refer to Figure-7.
3.4.1
RECEIVE INTERNAL TERMINATION
Figure-8 shows the appropriate external components to connect with
the cable for one channel. Table-11 is the list of the recommended impedance matching for receiver.
The impedance matching can be realized by the internal impedance
matching circuit or the external impedance matching circuit. If R_TERM[2]
LOS/AIS
Detector
RTIP
RRING
Receive
Internal
termination
Monitor Gain/
Adaptive Equalizer
Clock
and Data
Recovery
Data Slicer
LOS
RCLK
Jitter
Attenuator
Decoder
RDP
RDN
Figure-7 Receive Path Function Block Diagram
Table-11 Impedance Matching for Receiver
Cable Configuration
Internal Termination
External Termination
R_TERM[2:0]
RR
R_TERM[2:0]
120 Ω
1XX
RR
E1/75 Ω
000
E1/120 Ω
001
120 Ω
T1
010
100 Ω
J1
011
110 Ω
•
RX Line
RR4
B
2:1
• •
TX Line
VDDRn
One of the Two Identical Channels
D8
·• RTIPn
VDDRn
D7
VDDRn
D6
•
•·
D5 VDDTn
D4
RT4
•·
D3
3.3 V
68µF1
0.1µF
RRINGn
TTIPn
2
IDT82V2042E
A
1:1
• •
75 Ω
•
GNDRn
3.3 V
VDDTn
Cp
68µF 1
0.1µF
VDDTn
D2
RT4
3
D1
GNDTn
•·
•
TRINGn
Note:
1. Common decoupling capacitor. One per chip
2. Cp 0-560 (pF)
3. D1 - D8, Motorola - MBR0540T1; International Rectifier - 11DQ04 or 10BQ060
4. RT/ RR: refer toTable-10 and Table-11 respecivley for RT and RR values
Figure-8 Transmit/Receive Line Circuit
FUNCTIONAL DESCRIPTION
24
December 12, 2005
IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
In hardware control mode, TERMn, PULSn[3:0] pins can be used to
select impedance matching for both receiver and transmitter on a per channel basis. If TERMn pin is low, internal impedance network will be used. If
TERMn pin is high, external impedance network will be used in E1 mode,
or external impedance network for receiver and internal impedance network for transmitter will be used in T1/J1 mode. (This applies to ZB die revision only). When internal impedance network is used, PULSn[3:0] pins
should be set to select specific internal impedance for the corresponding
channel. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.4.2
DSX cross connect
point
RTIP
monitor
gain=0dB
RRING
R
normal receive mode
RTIP
LINE MONITOR
monitor gain
=22/26/32dB
In both T1/J1 and E1 short haul applications, the non-intrusive monitoring on channels located in other chips can be performed by tapping the monitored channel through a high impedance bridging circuit. Refer to Figure9 and Figure-10.
RRING
monitor mode
Figure-9 Monitoring Receive Line in Another Chip
After a high resistance bridging circuit, the signal arriving at the RTIPn/
RRINGn is dramatically attenuated. To compensate this attenuation, the
Monitor Gain can be used to boost the signal by 22 dB, 26 dB and 32 dB,
selected by MG[1:0] bits (RCF2, 0BH...). For normal operation, the Monitor
Gain should be set to 0 dB.
DSX cross connect
point
TTIP
In hardware control mode, MONTn pin can be used to set the Monitor
Gain on a per channel basis. When MONTn pin is low, the Monitor Gain for
the specific channel is 0 dB. When MONTn pin is high, the Monitor Gain for
the specific channel is 26 dB. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
TRING
R
normal transmit mode
RTIP
monitor gain
monitor gain
=22/26/32dB
RRING
monitor mode
Figure-10 Monitor Transmit Line in Another Chip
FUNCTIONAL DESCRIPTION
25
December 12, 2005
IDT82V2042E
3.4.3
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
3.4.8
ADAPTIVE EQUALIZER
The receive path system interface consists of RCLKn pin, RDn/RDPn
pin and RDNn pin. In E1 mode, the RCLKn outputs a recovered 2.048 MHz
clock. In T1/J1 mode, the RCLKn outputs a recovered 1.544 MHz clock. The
received data is updated on the RDn/RDPn and RDNn pins on the active
edge of RCLKn. The active edge of RCLKn can be selected by the
RCLK_SEL bit (RCF0, 09H...). And the active level of the data on RDn/
RDPn and RDNn can be selected by the RD_INV bit (RCF0, 09H...).
The Adaptive Equalizer can be enabled to increase the receive sensitivity and to allow programming of the LOS level up to -24 dB. See section
3.6 LOS AND AIS DETECTION. It can be enabled or disabled by setting
EQ_ON bit to ‘1’ or ‘0’ (RCF1, 0AH...).
3.4.4
RECEIVE SENSITIVITY
In Host mode, the Receive Sensitivity for both E1 and T1/J1 is -10 dB.
With the Adaptive Equalizer enabled, the receive sensitivity will be -20 dB.
In hardware control mode, only the active edge of RCLKn can be
selected. If RCLKE is set to high, the falling edge will be chosen as the active
edge of RCLKn. If RCLKE is set to low, the rising edge will be chosen as
the active edge of RCLKn. The active level of the data on RDn/RDPn and
RDNn is the same as that in software control mode.
In Hardware mode, the Adaptive Equalizer can not be enabled and the
receive sensitivity is fixed at -10 dB for both E1 and T1/J1. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.4.5
DATA SLICER
The received data can be output to the system side in two different ways:
Single Rail or Dual Rail, as selected by R_MD bit [1] (RCF0, 09H...). In Single Rail mode, only RDn pin is used to output data and the RDNn/CVn pin
is used to report the received errors. In Dual Rail Mode, both RDPn pin and
RDNn pin are used for outputting data.
The Data Slicer is used to generate a standard amplitude mark or a
space according to the amplitude of the input signals. The threshold can
be 40%, 50%, 60% or 70%, as selected by the SLICE[1:0] bits (RCF2,
0BH...). The output of the Data Slicer is forwarded to the CDR (Clock & Data
Recovery) unit or to the RDPn/RDNn pins directly if the CDR is disabled.
3.4.6
In the receive Dual Rail mode, the CDR unit can be by-passed by setting
R_MD[1:0] to ‘11’ (binary). In this situation, the output data from the Data
Slicer will be output to the RDPn/RDNn pins directly, and the RCLKn outputs the exclusive OR (XOR) of the RDPn and RDNn. This is called receiver
slicer mode. In this case, the transmit path is still operating in Dual Rail
mode.
CDR (Clock & Data Recovery)
The CDR is used to recover the clock and data from the received signal.
The recovered clock tracks the jitter in the data output from the Data Slicer
and keeps the phase relationship between data and clock during the
absence of the incoming pulse. The CDR can also be by-passed in the Dual
Rail mode. When CDR is by-passed, the data from the Data Slicer is output
to the RDPn/RDNn pins directly.
3.4.7
3.4.9
RECEIVE PATH POWER DOWN
The receive path can be powered down individually by setting R_OFF
bit (RCF0, 09H...) to ‘1’. In this case, the RCLKn, RDn/RDPn, RDNn and
LOSn will be logic low.
DECODER
In T1/J1 applications, the R_MD[1:0] bits (RCF0, 09H...) is used to
select the AMI decoder or B8ZS decoder. In E1 applications, the R_MD[1:0]
bits (RCF0, 09H...) are used to select the AMI decoder or HDB3 decoder.
In hardware control mode, receiver power down can be selected by pulling RPDn pin to high on a per channel basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for more details.
When the chip is configured by hardware, the operation mode of receive
and transmit path can be selected by setting RXTXM[1:0] pins on a global
basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
FUNCTIONAL DESCRIPTION
RECEIVE PATH SYSTEM INTERFACE
26
December 12, 2005
IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
The monitored line signal (transmit or receive) goes through Channel
1’s Clock and Data Recovery. The signal can be observed digitally at the
RCLK1, RD1/RDP1 and RDN1. If Channel 1 is configured to Remote Loopback while in the Monitoring mode, the monitored data will be output on
TTIP1/TRING1.
3.4.10 G.772 NON-INTRUSIVE MONITORING
In applications using only one channel, channel 1 can be configured to
monitor the data received or transmitted in channel 2. The MONT[1:0] bits
(GCF, 20H) determine which direction (transmit/receive) will be monitored.
The monitoring is non-intrusive per ITU-T G.772. Figure-11 illustrates the
concept.
Channel 2
LOS2
LOS/AIS
Detection
RCLK2
RD2/RDP2
CV2/RDN2
B8ZS/
HDB3/AMI
Decoder
Jitter
Attenuator
TCLK2
TD2/TDP2
TDN2
B8ZS/
HDB3/AMI
Encoder
Jitter
Attenuator
Clock and
Data
Recovery
Data
Slicer
Adaptive
Equalizer
Line
Driver
Waveform
Shaper
Receiver
Internal
Termination
RTIP2
Transmitter
Internal
Termination
TTIP2
Channel 1
LOS1
RCLK1
RD1/RDP1
CV1/RDN1
DLOS/AIS
Detection
B8ZS/
HDB3/AMI
Decoder
ALOS
Detection
Jitter
Attenuator
Clock and
Data
Recovery
Data
Slicer
Adaptive
Equalizer
RRING2
TRING2
G.772
Monitor
Receiver
Internal
Termination
RTIP1
Transmitter
Internal
Termination
TTIP1
RRING1
Remote
Loopback
TCLK1
TD1/TDP1
TDN1
B8ZS/
HDB3/AMI
Encoder
Jitter
Attenuator
Line
Driver
Waveform
Shaper
TRING1
Figure-11 G.772 Monitoring Diagram
FUNCTIONAL DESCRIPTION
27
December 12, 2005
IDT82V2042E
3.5
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
JITTER ATTENUATOR
In E1 applications, the Corner Frequency of the DPLL can be 0.9 Hz or
6.8 Hz, as selected by the JABW bit (JACF, 03H...). In T1/J1 applications,
the Corner Frequency of the DPLL can be 1.25 Hz or 5.00 Hz, as selected
by the JABW bit (JACF, 03H...). The lower the Corner Frequency is, the
longer time is needed to achieve synchronization.
There is one Jitter Attenuator in each channel of the LIU. The Jitter Attenuator can be deployed in the transmit path or the receive path, and can also
be disabled. This is selected by the JACF[1:0] bits (JACF, 03H...).
In hardware control mode, Jitter Attenuator position, bandwidth and the
depth of FIFO can be selected by JA[1:0] pins on a global basis. Refer to 5
HARDWARE CONTROL PIN SUMMARY for details.
3.5.1
When the incoming data moves faster than the outgoing data, the FIFO
will overflow. This overflow is captured by the JAOV_IS bit (INTS1, 19H...).
If the incoming data moves slower than the outgoing data, the FIFO will
underflow. This underflow is captured by the JAUD_IS bit (INTS1, 19H...).
For some applications that are sensitive to data corruption, the JA limit
mode can be enabled by setting JA_LIMIT bit (JACF, 03H...) to ‘1’. In the
JA limit mode, the speed of the outgoing data will be adjusted automatically
when the FIFO is close to its full or emptiness. The criteria of starting speed
adjustment are shown in Table-12. The JA limit mode can reduce the possibility of FIFO overflow and underflow, but the quality of jitter attenuation
is deteriorated.
JITTER ATTENUATION FUNCTION DESCRIPTION
The Jitter Attenuator is composed of a FIFO and a DPLL, as shown in
Figure-12. The FIFO is used as a pool to buffer the jittered input data, then
the data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the JADP[1:0] bits
(JACF, 03H...). In hardware control mode, the depth of FIFO can be selected
by JA[1:0] pins on a global basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details. Consequently, the constant delay of the Jitter Attenuator
will be 16 bits, 32 bits or 64 bits. Deeper FIFO can tolerate larger jitter, but
at the cost of increasing data latency time.
Jittered Clock
W
Criteria for Adjusting Data Outgoing Speed
32 Bits
2 bits close to its full or emptiness
3 bits close to its full or emptiness
4 bits close to its full or emptiness
De-jittered Data
RDNn
3.5.2
JITTER ATTENUATOR PERFORMANCE
The performance of the Jitter Attenuator in the IDT82V2042E meets the
ITU-T I.431, G.703, G.736-739, G.823, G.824, ETSI 300011, ETSI TBR12/
13, AT&T TR62411 specifications. Details of the Jitter Attenuator performance is shown in Table-64 Jitter Tolerance and Table-65 Jitter Attenuator
Characteristics.
R
DPLL
FIFO Depth
RDn/RDPn
FIFO
32/64/128
Jittered Data
Table-12 Criteria of Starting Speed Adjustment
De-jittered Clock
RCLKn
MCLK
Figure-12 Jitter Attenuator
FUNCTIONAL DESCRIPTION
28
December 12, 2005
IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
3.6
LOS AND AIS DETECTION
3.6.1
LOS DETECTION
• LOS detect level threshold
With the Adaptive Equalizer off, the amplitude threshold Q is fixed on
800 mVpp, while P=Q+200 mVpp (200 mVpp is the LOS level detect hysteresis).
The Loss of Signal Detector monitors the amplitude of the incoming signal level and pulse density of the received signal on RTIPn and RRINGn.
With the Adaptive Equalizer on, the value of Q can be selected by
LOS[4:0] bit (RCF1, 0AH...), while P=Q+4 dB (4 dB is the LOS level detect
hysteresis). Refer to Table 33, “RCF1: Receiver Configuration Register 1,”
on page 48 for LOS[4:0] bit values available.
• LOS declare (LOS=1)
A LOS is detected when the incoming signal has “no transitions”, i.e.,
when the signal level is less than Q dB below nominal for N consecutive
pulse intervals. Here N is defined by LAC bit (MAINT0, 0CH...). LOS will be
declared by pulling LOSn pin to high (LOS=1) and LOS interrupt will be generated if it is not masked.
When the chip is configured by hardware, the Adaptive Equalizer can
not be enabled and Programmable LOS levels are not available (pin 58 &
pin 60 have to be set to ‘0’).
• LOS clear (LOS=0)
The LOS is cleared when the incoming signal has “transitions”, i.e.,
when the signal level is greater than P dB below nominal and has an average pulse density of at least 12.5% for M consecutive pulse intervals, starting with the receipt of a pulse. Here M is defined by LAC bit (MAINT0,
0CH...). LOS status is cleared by pulling LOSn pin to low.
• Criteria for declare and clear of a LOS detect
The detection supports the ANSI T1.231 and I.431 for T1/J1 mode and
G.775 and ETSI 300233/I.431 for E1 mode. The criteria can be selected
by LAC bit (MAINT0, 0CH...) and T1E1 bit (GCF, 20H).
Table-13 and Table-14 summarize LOS declare and clear criteria for
both with and without the Adaptive Equalizer enabled.
• All Ones output during LOS
On the system side, the RDPn/RDNn will reflect the input pulse “transition” at the RTIPn/RRINGn side and output recovered clock (but the quality
of the output clock can not be guaranteed when the input level is lower than
the maximum receive sensitivity) when AISE bit (MAINT0, 0CH...) is 0; or
output All Ones as AIS when AISE bit (MAINT0, 0CH...) is 1. In this case
RCLKn output is replaced by MCLK.
LOS=1
signal level>P
density=OK
signal level 1 Vpp
M=128 bits
12.5% mark density
1 Vpp
M=128 bits
12.5% mark density
1 Vpp
M=32 bits
12.5% mark density
1 Vpp
M=32 bits
12.5% mark density
Q+ 4dB
M=128 bits
12.5% mark density
Q+ 4dB
M=128 bits
I.431 Level detect range is -18 to -30 dB.
12.5% mark density
Q+ 4dB
M=32 bits
12.5% mark density
Q+ 4dB
M=32 bits
12.5% mark density
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