82V2044EPFG8

QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT IDT82V2044E FEATURES: • • • • • • Four channel T1/E1/J1 short haul line interfaces Supports HPS (Hitless Protection Switching) for 1+1 protection without external relays Programmable T1/E1/J1 switchability allowing one bill of material for any line condition Single 3.3 V power supply with 5 V tolerance on digital interfaces Meets or exceeds specifications in - ANSI T1.102, T1.403 and T1.408 - ITU I.431, G.703,G.736, G.775 and G.823 - ETSI 300-166, 300-233 and TBR 12/13 - AT&T Pub 62411 Per channel software selectable on: - Wave-shaping templates - Line terminating impedance (T1:100 Ω, J1:110 Ω, E1:75 Ω/120 Ω) - Adjustment of arbitrary pulse shape - JA (Jitter Attenuator) position (receive path or transmit path) - Single rail/dual rail system interfaces - B8ZS/HDB3/AMI line encoding/decoding - Active edge of transmit clock (TCLK) and receive clock (RCLK) • • • • • • • • - Active level of transmit data (TDATA) and receive data (RDATA) - Receiver or transmitter power down - High impedance setting for line drivers - PRBS (Pseudo Random Bit Sequence) generation and detection with 215-1 PRBS polynomials for E1 - QRSS (Quasi Random Sequence Signals) generation and detection with 220-1 QRSS polynomials for T1/J1 - 16-bit BPV (Bipolar Pulse Violation)/Excess Zero/PRBS or QRSS error counter - Analog loopback, Digital loopback, Remote loopback and Inband loopback Adaptive receive sensitivity up to -20 dB Non-intrusive monitoring per ITU G.772 specification Short circuit protection for line drivers LOS (Loss Of Signal) detection with programmable LOS levels AIS (Alarm Indication Signal) detection JTAG interface Supports serial control interface, Motorola and Intel Non-Multiplexed interfaces Package: IDT82V2044E: 128-pin TQFP DESCRIPTION: The IDT82V2044E can be configured as a quad T1, quad E1 or quad J1 Line Interface Unit. The IDT82V2044E performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and detects and reports the LOS conditions. An integrated Adaptive Equalizer is available to increase the receive sensitivity and enable programming of LOS levels. In transmit path, there is an AMI/B8ZS/HDB3 encoder and Waveform Shaper. There is one Jitter Attenuator for each channel, which can be placed in either the receive path or the transmit path. The Jitter Attenuator can also be disabled. The IDT82V2044E supports both Single Rail and Dual Rail system interfaces and both serial and parallel control interfaces. To facilitate the network maintenance, a PRBS/QRSS generation/detection circuit is integrated in each channel, and different types of loopbacks can be set on a per channel basis. Four different kinds of line terminating impedance, 75Ω, 100 Ω, 110 Ω and 120 Ω are selectable on a per channel basis. The chip also provides driver short-circuit protection and supports JTAG boundary scanning. The IDT82V2044E can be used in SDH/SONET, LAN, WAN, Routers, Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices, CSU/DSU equipment, etc. The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGES August 2004 1  2003 Integrated Device Technology, Inc. All rights reserved. DSC-6533/- TCLKn TDn/TDPn TDNn RCLKn RDn/RDPn CVn/RDNn LOSn Figure-1 Block Diagram 2 Clock Generator PRBS Generator IBLC Generator TAOS PRBS Detector IBLC Detector Waveform Shaper Data Slicer Line Driver Adaptive Equalizer Transmitter Internal Termination Receiver Internal Termination JTAG TAP Digital Loopback Clock and Data Recovery Basic Control Jitter Attenuator Jitter Attenuator VDDD VDDIO VDDA VDDT VDDR Analog Loopback One of the Four Identical Channels TDO TDI TMS TCK TRST RST REF THZ Microprocessor Interface B8ZS/ HDB3/AMI Encoder Remote Loopback B8ZS/ HDB3/AMI Decoder LOS/AIS Detector G.772 Monitor TRINGn TTIPn RRINGn RTIPn QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT INDUSTRIAL TEMPERATURE RANGES FUNCTIONAL BLOCK DIAGRAM SCLKE INT/MOT P/S A[7:0] D[7:0] INT SDO SDI/R/W/WR DS/RD SCLK CS MCLKS MCLK QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT INDUSTRIAL TEMPERATURE RANGES TABLE OF CONTENTS 1 IDT82V2044E PIN CONFIGURATIONS ....................................................................................... 8 2 PIN DESCRIPTION ....................................................................................................................... 9 3 FUNCTIONAL DESCRIPTION .................................................................................................... 14 3.1 T1/E1/J1 MODE SELECTION .......................................................................................... 14 3.2 TRANSMIT PATH ............................................................................................................. 14 3.2.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 14 3.2.2 ENCODER .............................................................................................................. 14 3.2.3 PULSE SHAPER .................................................................................................... 14 3.2.3.1 Preset Pulse Templates .......................................................................... 14 3.2.3.2 User-Programmable Arbitrary Waveform ................................................ 15 3.2.4 TRANSMIT PATH LINE INTERFACE..................................................................... 18 3.2.5 TRANSMIT PATH POWER DOWN ........................................................................ 18 3.3 RECEIVE PATH ............................................................................................................... 19 3.3.1 RECEIVE INTERNAL TERMINATION.................................................................... 19 3.3.2 LINE MONITOR ...................................................................................................... 20 3.3.3 ADAPTIVE EQUALIZER......................................................................................... 20 3.3.4 RECEIVE SENSITIVITY ......................................................................................... 20 3.3.5 DATA SLICER ........................................................................................................ 20 3.3.6 CDR (Clock & Data Recovery)................................................................................ 20 3.3.7 DECODER .............................................................................................................. 20 3.3.8 RECEIVE PATH SYSTEM INTERFACE ................................................................ 20 3.3.9 RECEIVE PATH POWER DOWN........................................................................... 20 3.3.10 G.772 NON-INTRUSIVE MONITORING ................................................................ 21 3.4 JITTER ATTENUATOR .................................................................................................... 22 3.4.1 JITTER ATTENUATION FUNCTION DESCRIPTION ............................................ 22 3.4.2 JITTER ATTENUATOR PERFORMANCE ............................................................. 22 3.5 LOS AND AIS DETECTION ............................................................................................. 23 3.5.1 LOS DETECTION ................................................................................................... 23 3.5.2 AIS DETECTION .................................................................................................... 24 3.6 TRANSMIT AND DETECT INTERNAL PATTERNS ........................................................ 25 3.6.1 TRANSMIT ALL ONES ........................................................................................... 25 3.6.2 TRANSMIT ALL ZEROS......................................................................................... 25 3.6.3 PRBS/QRSS GENERATION AND DETECTION.................................................... 25 3.7 LOOPBACK ...................................................................................................................... 25 3.7.1 ANALOG LOOPBACK ............................................................................................ 25 3.7.2 DIGITAL LOOPBACK ............................................................................................. 25 3.7.3 REMOTE LOOPBACK............................................................................................ 25 3.7.4 INBAND LOOPBACK.............................................................................................. 27 3.7.4.1 Transmit Activate/Deactivate Loopback Code......................................... 27 3.7.4.2 Receive Activate/Deactivate Loopback Code.......................................... 27 3.7.4.3 Automatic Remote Loopback .................................................................. 27 3.8 ERROR DETECTION/COUNTING AND INSERTION ...................................................... 28 3 QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT 3.9 3.10 3.11 3.12 3.13 3.14 3.15 INDUSTRIAL TEMPERATURE RANGES 3.8.1 DEFINITION OF LINE CODING ERROR ............................................................... 28 3.8.2 ERROR DETECTION AND COUNTING ................................................................ 28 3.8.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 29 LINE DRIVER FAILURE MONITORING ........................................................................... 29 MCLK AND TCLK ............................................................................................................. 30 3.10.1 MASTER CLOCK (MCLK) ...................................................................................... 30 3.10.2 TRANSMIT CLOCK (TCLK).................................................................................... 30 MICROCONTROLLER INTERFACES ............................................................................. 31 3.11.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 31 3.11.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 31 INTERRUPT HANDLING .................................................................................................. 32 5V TOLERANT I/O PINS .................................................................................................. 32 RESET OPERATION ........................................................................................................ 32 POWER SUPPLY ............................................................................................................. 32 4 PROGRAMMING INFORMATION .............................................................................................. 33 4.1 REGISTER LIST AND MAP ............................................................................................. 33 4.2 REGISTER DESCRIPTION .............................................................................................. 35 4.2.1 GLOBAL REGISTERS............................................................................................ 35 4.2.2 JITTER ATTENUATION CONTROL REGISTER ................................................... 37 4.2.3 TRANSMIT PATH CONTROL REGISTERS........................................................... 38 4.2.4 RECEIVE PATH CONTROL REGISTERS ............................................................. 40 4.2.5 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 42 4.2.6 INTERRUPT CONTROL REGISTERS ................................................................... 45 4.2.7 LINE STATUS REGISTERS ................................................................................... 47 4.2.8 INTERRUPT STATUS REGISTERS ...................................................................... 49 4.2.9 COUNTER REGISTERS ........................................................................................ 50 4.2.10 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 51 5 IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 52 5.1 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 53 5.2 JTAG DATA REGISTER ................................................................................................... 53 5.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 53 5.2.2 BYPASS REGISTER (BR)...................................................................................... 53 5.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 53 5.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 54 6 TEST SPECIFICATIONS ............................................................................................................ 56 7 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 68 7.1 SERIAL INTERFACE TIMING .......................................................................................... 68 7.2 PARALLEL INTERFACE TIMING ..................................................................................... 69 4 QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT INDUSTRIAL TEMPERATURE RANGES LIST OF TABLES Table-1 Table-2 Table-3 Table-4 Table-5 Table-6 Table-7 Table-8 Table-9 Table-10 Table-11 Table-12 Table-13 Table-14 Table-15 Table-16 Table-17 Table-18 Table-19 Table-20 Table-21 Table-22 Table-23 Table-24 Table-25 Table-26 Table-27 Table-28 Table-29 Table-30 Table-31 Table-32 Table-33 Table-34 Table-35 Table-36 Table-37 Table-38 Table-39 Table-40 Pin Description ................................................................................................................ 9 Transmit Waveform Value For E1 75 Ω ........................................................................ 15 Transmit Waveform Value For E1 120 Ω ...................................................................... 16 Transmit Waveform Value For T1 0~133 ft................................................................... 16 Transmit Waveform Value For T1 133~266 ft............................................................... 16 Transmit Waveform Value For T1 266~399 ft............................................................... 16 Transmit Waveform Value For T1 399~533 ft............................................................... 17 Transmit Waveform Value For T1 533~655 ft............................................................... 17 Transmit Waveform Value For J1 0~655 ft ................................................................... 17 Impedance Matching for Transmitter ............................................................................ 18 Impedance Matching for Receiver ................................................................................ 19 Criteria of Starting Speed Adjustment........................................................................... 22 LOS Declare and Clear Criteria, Adaptive Equalizer Disabled ..................................... 23 LOS Declare and Clear Criteria, Adaptive Equalizer Enabled ...................................... 24 AIS Condition ................................................................................................................ 24 Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 25 EXZ Definition ............................................................................................................... 28 Interrupt Event............................................................................................................... 32 Global Register List and Map........................................................................................ 33 Per Channel Register List and Map .............................................................................. 34 ID: Chip Revision Register ............................................................................................ 35 RST: Reset Register ..................................................................................................... 35 GCF0: Global Configuration Register 0 ........................................................................ 35 GCF1: Global Configuration Register 1 ........................................................................ 36 INTCH: Interrupt Channel Indication Register............................................................... 36 JACF: Jitter Attenuator Configuration Register ............................................................. 37 TCF0: Transmitter Configuration Register 0 ................................................................. 38 TCF1: Transmitter Configuration Register 1 ................................................................. 38 TCF2: Transmitter Configuration Register 2 ................................................................. 39 TCF3: Transmitter Configuration Register 3 ................................................................. 39 TCF4: Transmitter Configuration Register 4 ................................................................. 39 RCF0: Receiver Configuration Register 0..................................................................... 40 RCF1: Receiver Configuration Register 1..................................................................... 40 RCF2: Receiver Configuration Register 2..................................................................... 41 MAINT0: Maintenance Function Control Register 0...................................................... 42 MAINT1: Maintenance Function Control Register 1...................................................... 42 MAINT2: Maintenance Function Control Register 2...................................................... 43 MAINT3: Maintenance Function Control Register 3...................................................... 43 MAINT4: Maintenance Function Control Register 4...................................................... 43 MAINT5: Maintenance Function Control Register 5...................................................... 43 5 QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT Table-41 Table-42 Table-43 Table-44 Table-45 Table-46 Table-47 Table-48 Table-49 Table-50 Table-51 Table-52 Table-53 Table-54 Table-55 Table-56 Table-57 Table-58 Table-59 Table-60 Table-61 Table-62 Table-63 Table-64 Table-65 Table-66 Table-67 Table-68 Table-69 Table-70 Table-71 INDUSTRIAL TEMPERATURE RANGES MAINT6: Maintenance Function Control Register 6...................................................... INTM0: Interrupt Mask Register 0 ................................................................................. INTM1: Interrupt Mask Register 1 ................................................................................. INTES: Interrupt Trigger Edges Select Register ........................................................... STAT0: Line Status Register 0 (real time status monitor)............................................. STAT1: Line Status Register 1 (real time status monitor)............................................. INTS0: Interrupt Status Register 0 ................................................................................ INTS1: Interrupt Status Register 1 ................................................................................ CNT0: Error Counter L-byte Register 0......................................................................... CNT1: Error Counter H-byte Register 1 ........................................................................ TERM: Transmit and Receive Termination Configuration Register .............................. Instruction Register Description .................................................................................... Device Identification Register Description..................................................................... TAP Controller State Description .................................................................................. Absolute Maximum Rating ............................................................................................ Recommended Operation Conditions ........................................................................... Power Consumption...................................................................................................... DC Characteristics ........................................................................................................ E1 Receiver Electrical Characteristics .......................................................................... T1/J1 Receiver Electrical Characteristics...................................................................... E1 Transmitter Electrical Characteristics ...................................................................... T1/J1 Transmitter Electrical Characteristics.................................................................. Transmitter and Receiver Timing Characteristics ......................................................... Jitter Tolerance ............................................................................................................. Jitter Attenuator Characteristics .................................................................................... JTAG Timing Characteristics ........................................................................................ Serial Interface Timing Characteristics ......................................................................... Non_multiplexed Motorola Read Timing Characteristics .............................................. Non_multiplexed Motorola Write Timing Characteristics .............................................. Non_multiplexed Intel Read Timing Characteristics ..................................................... Non_multiplexed Intel Write Timing Characteristics...................................................... 6 44 45 45 46 47 48 49 49 50 50 51 53 53 54 56 56 57 57 58 59 60 61 62 63 65 67 68 69 70 71 72 QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT INDUSTRIAL TEMPERATURE RANGES LIST OF FIGURES Figure-1 Figure-2 Figure-3 Figure-4 Figure-5 Figure-6 Figure-7 Figure-8 Figure-9 Figure-10 Figure-11 Figure-12 Figure-13 Figure-14 Figure-15 Figure-16 Figure-17 Figure-18 Figure-19 Figure-20 Figure-21 Figure-22 Figure-23 Figure-24 Figure-25 Figure-26 Figure-27 Figure-28 Figure-29 Figure-30 Figure-31 Figure-32 Figure-33 Figure-34 Figure-35 Figure-36 Block Diagram ................................................................................................................. 2 IDT82V2044E TQFP128 Package Pin Assignment ........................................................ 8 E1 Waveform Template Diagram .................................................................................. 14 E1 Pulse Template Test Circuit ..................................................................................... 14 DSX-1 Waveform Template .......................................................................................... 14 T1 Pulse Template Test Circuit ..................................................................................... 15 Receive Path Function Block Diagram .......................................................................... 19 Transmit/Receive Line Circuit ....................................................................................... 19 Monitoring Receive Line in Another Chip ...................................................................... 20 Monitor Transmit Line in Another Chip .......................................................................... 20 G.772 Monitoring Diagram ............................................................................................ 21 Jitter Attenuator ............................................................................................................. 22 LOS Declare and Clear ................................................................................................. 23 Analog Loopback .......................................................................................................... 26 Digital Loopback ............................................................................................................ 26 Remote Loopback ......................................................................................................... 26 Auto Report Mode ......................................................................................................... 28 Manual Report Mode ..................................................................................................... 29 TCLK Operation Flowchart ............................................................................................ 30 Serial Processor Interface Function Timing .................................................................. 31 JTAG Architecture ......................................................................................................... 52 JTAG State Diagram ..................................................................................................... 55 Transmit System Interface Timing ................................................................................ 63 Receive System Interface Timing ................................................................................. 63 E1 Jitter Tolerance Performance .................................................................................. 64 T1/J1 Jitter Tolerance Performance .............................................................................. 64 E1 Jitter Transfer Performance ..................................................................................... 66 T1/J1 Jitter Transfer Performance ................................................................................ 66 JTAG Interface Timing .................................................................................................. 67 Serial Interface Write Timing ......................................................................................... 68 Serial Interface Read Timing with SCLKE=1 ................................................................ 68 Serial Interface Read Timing with SCLKE=0 ................................................................ 68 Non_multiplexed Motorola Read Timing ....................................................................... 69 Non_multiplexed Motorola Write Timing ....................................................................... 70 Non_multiplexed Intel Read Timing .............................................................................. 71 Non_multiplexed Intel Write Timing .............................................................................. 72 7 QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VDDT1 VDDT1 NC VDDIO GNDIO TCLK1 TD1/TDP1 TDN1 RCLK1 RD1/RDP1 CV1/RDN1 TCLK2 TD2/TDP2 TDN2 RCLK2 RD2/RDP2 CV2/RDN2 VDDD GNDD GNDIO TCLK3 VDDIO TD3/TDP3 TDN3 RCLK3 RD3/RDP3 CV3/RDN3 TCLK4 TD4/TDP4 TDN4 RCLK4 RD4/RDP4 CV4/RDN4 GNDIO VDDIO NC NC NC IDT82V2044E PIN CONFIGURATIONS 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 IDT82V2044E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 TRING1 TTIP1 GNDT1 GNDT1 GNDR1 RRING1 RTIP1 VDDR1 VDDT2 VDDT2 TRING2 TTIP2 GNDT2 GNDT2 GNDR2 RRING2 RTIP2 VDDR2 VDDA GNDA TRST TMS TDI TDO TCK LOS1 LOS2 LOS3 LOS4 THZ SCLKE INT/MOT IC P/S VDDD MCLK GNDD GNDIO VDDIO D7 D6 D5 D4 D3 D2 D1 D0 VDDIO GNDIO A7 A6 A5 A4 A3 A2 A1 A0 CS SCLK DS/RD SDI/R/W/WR SDO INT RST 1 INDUSTRIAL TEMPERATURE RANGES Figure-2 IDT82V2044E TQFP128 Package Pin Assignment 8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 VDDR4 RTIP4 RRING4 GNDR4 GNDT4 GNDT4 TTIP4 TRING4 VDDT4 VDDT4 VDDR3 RTIP3 RRING3 GNDR3 GNDT3 GNDT3 TTIP3 TRING3 VDDT3 VDDT3 VDDA REF IC GNDA MCLKS IC INDUSTRIAL TEMPERATURE RANGES QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT 2 PIN DESCRIPTION Table-1 Pin Description Name Type TQFP128 Description Transmit and Receive Line Interface TTIP1 TTIP2 TTIP3 TTIP4 Output Analog TRING1 TRING2 TRING3 TRING4 RTIP1 RTIP2 RTIP3 RTIP4 104 114 48 58 103 113 47 57 Input Analog RRING1 RRING2 RRING3 RRING4 109 119 53 63 TTIPn1/TRINGn: Transmit Bipolar Tip/Ring for Channel 1~4 These pins are the differential line driver outputs and can be set to high impedance state globally or individually. A logic high on THZ pin turns all these pins into high impedance state. When THZ bit (TCF1, 03H...)2 is set to ‘1’, the TTIPn/TRINGn in the corresponding channel is set to high impedance state. In summary, these pins will become high impedance in the following conditions: • THZ pin is high: all TTIPn/TRINGn enter high impedance. • THZn bit is set to 1: the corresponding TTIPn/TRINGn become high impedance; • Loss of MCLK: all TTIPn/TRINGn pins become high impedance; • Loss of TCLKn: the corresponding TTIPn/TRINGn become high impedance (exceptions: Remote Loopback; Transmit internal pattern by MCLK); • Transmitter path power down: the corresponding TTIPn/TRINGn become high impedance; • After software reset; pin reset and power on: all TTIPn/TRINGn enter high impedance. RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 1~4 These pins are the differential line receiver inputs. 108 118 52 62 Transmit and Receive Digital Data Interface TD1/TDP1 TD2/TDP2 TD3/TDP3 TD4/TDP4 Input TDN1 TDN2 TDN3 TDN4 TCLK1 TCLK2 TCLK3 TCLK4 96 90 80 74 95 89 79 73 Input 97 91 82 75 TDn: Transmit Data for Channel 1~4 In Single Rail Mode, the NRZ data to be transmitted is input on these pins. Data on TDn is sampled into the device on the active edge of TCLKn. The active edge of TCLKn is selected by the TCLK_SEL bit (TCF0, 02H...). Data is encoded by AMI, HDB3 or B8ZS line code rules before being transmitted to the line. In this mode, TDNn should be connected to ground. TDPn/TDNn: Positive/Negative Transmit Data for Channel 1~4 In Dual Rail Mode, the NRZ data to be transmitted is input on these pins. Data on TDPn/TDNn is sampled into the device on the active edge of TCLKn. The active edge of the TCLKn is selected by the TCLK_SEL bit (TCF0, 02H...) The line code in Dual Rail Mode is as follows: TDPn TDNn 0 0 Space Output Pulse 0 1 Positive Pulse 1 0 Negative Pulse 1 1 Space TCLKn: Transmit Clock for Channel 1~4 These pins input 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode transmit clock. The transmit data on TDn/TDPn or TDNn is sampled into the device on the active edge of TCLKn. If TCLKn is missing3 and the TCLKn missing interrupt is not masked, an interrupt will be generated. Notes: 1. The footprint ‘n’ (n = 1~4) represents one of the four channels. 2. The name and address of the registers that contain the preceding bit. Only the address of channel 1 register is listed, the rest addresses are represented by '...'. Users can find these omitted addresses in the Register Description section. 3. TCLKn missing: the state of TCLKn continues to be high level or low level over 70 clock cycles. 9 INDUSTRIAL TEMPERATURE RANGES QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Name Type TQFP128 Description RD1/RDP1 RD2/RDP2 RD3/RDP3 RD4/RDP4 Output 93 87 77 71 RDn: Receive Data for Channel 1~4 In Single Rail Mode, the NRZ receive data is output on these pins. Data is decoded according to AMI, HDB3 or B8ZS line code rules. The active level on RDn pin is selected by the RD_INV bit (RCF0, 07H...). CV1/RDN1 CV2/RDN2 CV3/RDN3 CV4/RDN4 92 86 76 70 CVn: Code Violation for Channel 1~4 In Single Rail Mode, the BPV/CV errors in received data streams will be reported by driving pin CVn to high level for a full clock cycle. The B8ZS/HDB3 line code violation can be indicated when the B8ZS/HDB3 decoder is enabled. When AMI decoder is selected, the bipolar violation can be indicated. RDPn/RDNn: Positive/Negative Receive Data for Channel 1~4 In Dual Rail Mode with Clock & Data Recovery (CDR), these pins output the NRZ data with the recovered clock. An active level on RDPn indicates the receipt of a positive pulse on RTIPn/RRINGn while an active level on RDNn indicates the receipt of a negative pulse on RTIPn/RRINGn. The active level on RDPn/RDNn is selected by the RD_INV bit (RCF0, 07H...). When CDR is disabled, these pins directly output the raw RZ sliced data. The output data on RDn and RDPn/RDNn is updated on the active edge of RCLKn. RCLK1 RCLK2 RCLK3 RCLK4 Output 94 88 78 72 RCLKn: Receive Clock for Channel 1~4 These pins output 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode receive clock. Under LOS conditions, if AISE bit (MAINT0, 0AH...) is ‘1’, RCLKn is derived from MCLK. In clock recovery mode, these pins provide the clock recovered from the signal received on RTIPn/RRINGn. The receive data (RDn in Single Rail Mode or RDPn/RDNn in Dual Rail Mode) is updated on the active edge of RCLKn. The active edge is selected by the RCLK_SEL bit (RCF0, 07H...). If clock recovery is bypassed, RCLKn is the exclusive OR(XOR) output of the Dual Rail sliced data RDPn and RDNn. This signal can be used in the applications with external clock recovery circuitry. MCLK Input 10 MCLK: Master Clock MCLK is an independent, free-running reference clock. It is a single reference for all operation modes and provides selectable 1.544 MHz or 37.056 MHz for T1/J1 operating mode, while 2.048 MHz or 49.152 MHz for E1 operating mode. The reference clock is used to generate several internal reference signals: • Timing reference for the integrated clock recovery unit. • Timing reference for the integrated digital jitter attenuator. • Timing reference for microcontroller interface. • Generation of RCLKn signal during a loss of signal condition. • Reference clock during Transmit All Ones (TAO) and all zeros condition. When sending PRBS/QRSS or Inband Loopback code, either MCLK or TCLKn can be selected as the reference clock. • Reference clock for ATAO and AIS. The loss of MCLK will turn all the four TTIP/TRING into high impedance status. MCLKS Input 40 MCLKS: Master Clock Select If 2.048 MHz (E1) or 1.544 MHz (T1/J1) is selected as the MCLK, this pin should be connected to ground; and if the 49.152 MHz (E1) or 37.056 MHz (T1/J1) is selected as the MCLK, this pin should be pulled high. LOS1 LOS2 LOS3 LOS4 Output 128 1 2 3 LOSn: Loss of Signal Output for Channel 1~4 These pins are used to indicate the loss of received signals. When LOSn pin becomes high, it indicates the loss of received signals in channel n. The LOSn pin will become low automatically when valid received signal is detected again. The criteria of loss of signal are described in 3.5 LOS AND AIS DETECTION. Control Interface P/S Input 8 P/S: Parallel or Serial Control Interface Select Level on this pin determines which control mode is selected to control the device as follows: P/S Control Interface High Parallel Microcontroller Interface Low Serial Microcontroller Interface The serial microcontroller interface consists of CS, SCLK, SDI, SDO and SCLKE pins. Parallel microcontroller interface consists of CS, A[7:0], D[7:0], DS/RD and R/W/WR pins. The device supports non-multiplexed parallel interface as follows: P/S, INT/MOT Microcontroller Interface 10 Motorola non-multiplexed 11 Intel non-multiplexed 10 INDUSTRIAL TEMPERATURE RANGES QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Name Type TQFP128 Description INT/MOT Input 6 INT/MOT: Intel or Motorola Microcontroller Interface Select In microcontroller mode, the parallel microcontroller interface is configured for Motorola compatible microcontrollers when this pin is low, or for Intel compatible microcontrollers when this pin is high. CS Input 32 CS: Chip Select In microcontroller mode, this pin is asserted low by the microcontroller to enable microcontroller interface. For each read or write operation, this pin must be changed from high to low, and will remain low until the operation is over. SCLK Input 33 SCLK: Shift Clock In serial microcontroller mode, signal on this pin is the shift clock for the serial interface. Configuration data on pin SDI is sampled on the rising edges of SCLK. Configuration and status data on pin SDO is clocked out of the device on the rising edges of SCLK if pin SCLKE is low, or on the falling edges of SCLK if pin SCLKE is high. DS/RD Input 34 DS: Data Strobe In parallel Motorola microcontroller interface mode, signal on this pin is the data strobe of the parallel interface. During a write operation (R/W =0), data on D[7:0] is sampled into the device. During a read operation (R/W =1), data is output to D[7:0] from the device. RD: Read Operation In parallel Intel microcontroller interface mode, this pin is asserted low by the microcontroller to initiate a read cycle. Data is output to D[7:0] from the device during a read operation. SDI/R/W/WR Input 35 SDI: Serial Data Input In serial microcontroller mode, data is input on this pin. Input data is sampled on the rising edges of SCLK. R/W: Read/Write Select In parallel Motorola microcontroller interface mode, this pin is low for write operation and high for read operation. WR: Write Operation In parallel Intel microcontroller interface mode, this pin is asserted low by the microcontroller to initiate a write cycle. Data on D[7:0] is sampled into the device during a write operation. SDO Output 36 SDO: Serial Data Output In serial microcontroller mode, signal on this pin is the output data of the serial interface. Configuration and status data on pin SDO is clocked out of the device on the active edge of SCLK. INT Output 37 INT: Interrupt Request This pin outputs the general interrupt request for all interrupt sources. If INTM_GLB bit (GCF0, 40H) is set to ‘1’ all the interrupt sources will be masked. And these interrupt sources also can be masked individually via registers (INTM0, 11H) and (INTM1, 12H). Interrupt status is reported via byte INT_CH (INTCH, 80H), registers (INTS0, 16H) and (INTS1, 17H). Output characteristics of this pin can be defined to be push-pull (active high or low) or be open-drain (active low) by bits INT_PIN[1:0] (GCF0, 40H). D7 D6 D5 D4 D3 D2 D1 D0 I/O Tri-state 14 15 16 17 18 19 20 21 Dn: Data Bus 7~0 These pins function as a bi-directional data bus of the microcontroller interface. A7 A6 A5 A4 A3 A2 A1 A0 Input 24 25 26 27 28 29 30 31 An: Address Bus 7~0 These pins function as an address bus of the microcontroller interface. RST Input 38 RST: Hardware Reset The chip is reset if a low signal is applied on this pin for more than 100ns. All the drivers output are in high-impedance state, all the internal flip-flops are reset and all the registers are initialized to their default values. 11 INDUSTRIAL TEMPERATURE RANGES QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Name Type TQFP128 Description THZ Input 4 THZ: Transmit Driver Enable This pin enables or disables all transmitter drivers on a global basis. A low level on this pin enables the drivers while a high level turns all drivers into high impedance state. Note that functionality of internal circuits is not affected by signal on this pin. REF Input 43 REF: Reference Resistor An external resistor (3 KΩ, 1%) is used to connect this pin to ground to provide a standard reference current for internal circuit. SCLKE Input 5 SCLKE: Serial Clock Edge Select Signal on this pin determines the active edge of SCLK to output SDO. The active clock edge is selected as shown below: SCLKE SCLK Low Rising edge is active edge High Falling edge is active edge JTAG Signals TRST Input Pullup 123 TRST: JTAG Test Port Reset This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resistor. To ensure deterministic operation of the test logic, TMS should be held high while the signal applied to TRST changes from low to high. For normal signal processing, this pin should be connected to ground. TMS Input Pullup 124 TMS: JTAG Test Mode Select This pin is used to control the test logic state machine and is sampled on the rising edges of TCK. TMS has an internal pull-up resistor. TCK Input 127 TCK: JTAG Test Clock This pin is the input clock for JTAG. The data on TDI and TMS is clocked into the device on the rising edges of TCK while the data on TDO is clocked out of the device on the falling edges of TCK. When TCK is idle at a low level, all stored-state devices contained in the test logic will retain their state indefinitely. TDO Output Tri-state 126 TDO: JTAG Test Data Output This is a tri-state output signal and used for reading all the serial configuration and test data from the test logic. The data on TDO is clocked out of the device on the falling edges of TCK. TDI Input Pullup 125 TDI: JTAG Test Data Input This pin is used for loading instructions and data into the test logic and has an internal pullup resistor. The data on TDI is clocked into the device on the rising edges of TCK. Power Supplies and Grounds VDDIO - 13, 22 68, 81 99 3.3V I/O Power Supply GNDIO - 12, 23 69, 83 98 I/O Ground VDDT1 VDDT2 VDDT3 VDDT4 - 101, 102 3.3V Power Supply for Transmitter Driver 111, 112 45, 46 55, 56 GNDT1 GNDT2 GNDT3 GNDT4 - 105, 106 Analog Ground for Transmitter Driver 115, 116 49, 50 59, 60 VDDA - 44, 121 3.3V Analog Core Power Supply GNDA - 41, 122 Core Analog Ground VDDD - 9, 85 3.3V Digital Core Power Supply GNDD - 11, 84 Core Digital Ground VDDR1 VDDR2 VDDR3 VDDR4 - 110 120 54 64 3.3V Power Supply for Receiver 12 INDUSTRIAL TEMPERATURE RANGES QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Name Type TQFP128 GNDR1 GNDR2 GNDR3 GNDR4 - 107 117 51 61 Analog Ground for Receiver Description IC - 39 7 IC: Internal Connection Internal Use. These pins should be connected to ground when in normal operation. IC - 42 IC: Internal Connection Internal Use. This pin should be left open when in normal operation. NC - Others 65, 66 NC: No Connection 67, 100 13 INDUSTRIAL TEMPERATURE RANGES QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT 3 FUNCTIONAL DESCRIPTION 3.1 T1/E1/J1 MODE SELECTION Ω, the PULS[3:0] bits (TCF1, 03H...) should be set to ‘0001’. In external impedance matching mode, for both E1/75 Ω and E1/120 Ω cable impedance, PULS[3:0] should be set to ‘0001’. The IDT82V2044E can be used as a four-channel E1 LIU or a four-channel T1/J1 LIU. In E1 application, the T1E1 bit (GCF0, 40H) should be set to ‘0’. In T1/J1 application, the T1E1 bit should be set to ‘1’. 1 .0 0 TRANSMIT PATH 0 .8 0 Normalized Amplitude 3.2 1 .2 0 The transmit path of each channel of the IDT82V2044E consists of an Encoder, an optional Jitter Attenuator, a Waveform Shaper, a Line Driver and a Programmable Transmit Termination. 3.2.1 TRANSMIT PATH SYSTEM INTERFACE 0 .6 0 0 .4 0 0 .2 0 The transmit path system interface consists of TCLKn pin, TDn/TDPn pin and TDNn pin. In E1 mode, the TCLKn is a 2.048 MHz clock. In T1/J1 mode, the TCLKn is a 1.544 MHz clock. If the TCLKn is missing for more than 70 MCLK cycles, an interrupt will be generated if it is not masked. 0 .0 0 -0 .2 0 -0 .6 - 0 .4 - 0 .2 0 0 .2 0 .4 0 .6 T im e in U n it In te rv a ls Transmit data is sampled on the TDn/TDPn and TDNn pins by the active edge of TCLKn. The active edge of TCLKn can be selected by the TCLK_SEL bit (TCF0, 02H...). And the active level of the data on TDn/TDPn and TDNn can be selected by the TD_INV bit (TCF0, 02H...). Figure-3 E1 Waveform Template Diagram The transmit data from the system side can be provided in two different ways: Single Rail and Dual Rail. In Single Rail mode, only TDn pin is used for transmitting data and the T_MD[1] bit (TCF0, 02H...) should be set to ‘0’. In Dual Rail Mode, both TDPn and TDNn pins are used for transmitting data, the T_MD[1] bit (TCF0, 02H...) should be set to ‘1’. IDT82V2044E 3.2.2 TTIPn VOUT TRINGn Note: 1. For RLOAD = 75 Ω (nom), Vout (Peak)=2.37V (nom) 2. For RLOAD =120 Ω (nom), Vout (Peak)=3.00V (nom) ENCODER Figure-4 E1 Pulse Template Test Circuit When T1/J1 mode is selected, in Single Rail mode, the Encoder can be selected to be a B8ZS encoder or an AMI encoder by setting T_MD[0] bit (TCF0, 02H...). For T1 applications, the pulse shape is shown in Figure-5 according to the T1.102 and the measuring diagram is shown in Figure-6. This also meets the requirement of G.703, 2001. The cable length is divided into five grades, and there are five pulse templates used for each of the cable length. The pulse template is selected by PULS[3:0] bits (TCF1, 03H...). When E1 mode is selected, in Single Rail mode, the Encoder can be configured to be a HDB3 encoder or an AMI encoder by setting T_MD[0] bit (TCF0, 02H...). In both T1/J1 mode and E1 mode, when Dual Rail mode is selected (bit T_MD[1] is ‘1’), the Encoder is by-passed. In the Dual Rail mode, a logic ‘1’ on the TDPn pin and a logic ‘0’ on the TDNn pin results in a negative pulse on the TTIPn/TRINGn; a logic ‘0’ on TDPn pin and a logic ‘1’ on TDNn pin results in a positive pulse on the TTIPn/TRINGn. If both TDPn and TDNn are logic ‘1’ or logic ‘0’, the TTIPn/TRINGn outputs a space (Refer to TDn/ TDPn, TDNn Pin Description). 1.2 1 0.8 Normalized Amplitude 3.2.3 RLOAD PULSE SHAPER The IDT82V2044E provides two ways of manipulating the pulse shape before sending it. One is to use preset pulse templates; the other is to use user-programmable arbitrary waveform template. 0.6 0.4 0.2 0 -0.2 -0.4 3.2.3.1 Preset Pulse Templates -0.6 0 For E1 applications, the pulse shape is shown in Figure-3 according to the G.703 and the measuring diagram is shown in Figure-4. In internal impedance matching mode, if the cable impedance is 75 Ω, the PULS[3:0] bits (TCF1, 03H...) should be set to ‘0000’; if the cable impedance is 120 250 500 750 1000 Time (ns) Figure-5 DSX-1 Waveform Template 14 1250 INDUSTRIAL TEMPERATURE RANGES QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT (4).Set the RW bit (TCF3, 05H...) to ‘0’ to implement writing data to RAM, or to ‘1’ to implement read data from RAM (5).Implement the Read from RAM/Write to RAM by setting the DONE bit (TCF3, 05H...) TTIPn Cable IDT82V2044E RLOAD VOUT Repeat the above steps until all the sample data are written to or read from the internal RAM. (6).Write the scaling data to SCAL[5:0] bits (TCF2, 04H...) to scale the amplitude of the waveform based on the selected standard pulse amplitude TRINGn Note: RLOAD = 100 Ω ± 5% Figure-6 T1 Pulse Template Test Circuit When more than one UI is used to compose the pulse template, the overlap of two consecutive pulses could make the pulse amplitude overflow (exceed the maximum limitation) if the pulse amplitude is not set properly. This overflow is captured by DAC_OV_IS bit (INTS1, 17H...), and, if enabled by the DAC_OV_IM bit (INTM1, 12H...), an interrupt will be generated. For J1 applications, the PULS[3:0] (TCF1, 03H...) should be set to ‘0111’. Table-10 lists these values. 3.2.3.2 User-Programmable Arbitrary Waveform When the PULS[3:0] bits are set to ‘11xx’, user-programmable arbitrary waveform generator mode can be used in the corresponding channel. This allows the transmitter performance to be tuned for a wide variety of line condition or special application. The following tables give all the sample data based on the preset pulse templates in detail for reference. For preset pulse templates, scaling up/ down against the pulse amplitude is not supported. 1.Table-2 Transmit Waveform Value For E1 75 Ω 2.Table-3 Transmit Waveform Value For E1 120 Ω 3.Table-4 Transmit Waveform Value For T1 0~133 ft 4.Table-5 Transmit Waveform Value For T1 133~266 ft 5.Table-6 Transmit Waveform Value For T1 266~399 ft 6.Table-7 Transmit Waveform Value For T1 399~533 ft 7.Table-8 Transmit Waveform Value For T1 533~655 ft 8.Table-9 Transmit Waveform Value For J1 0~655 ft Each pulse shape can extend up to 4 UIs (Unit Interval), addressed by UI[1:0] bits (TCF3, 05H...) and each UI is divided into 16 sub-phases, addressed by the SAMP[3:0] bits (TCF3, 05H...). The pulse amplitude of each phase is represented by a binary byte, within the range from +63 to 63, stored in WDAT[6:0] bits (TCF4, 06H...) in signed magnitude form. The most positive number +63 (D) represents the maximum positive amplitude of the transmit pulse while the most negative number -63 (D) represents the maximum negative amplitude of the transmit pulse. Therefore, up to 64 bytes are used. For each channel, a 64 bytes RAM is available. Table-2 Transmit Waveform Value For E1 75 Ω There are eight standard templates which are stored in a local ROM. User can select one of them as reference and make some changes to get the desired waveform. User can change the wave shape and the amplitude to get the desired pulse shape. In order to do this, firstly, users can choose a set of waveform value from the following eight tables, which is the most similar to the desired pulse shape. Table-2, Table-3, Table-4, Table-5, Table-6, Table-7, Table-8 and Table-9 list the sample data and scaling data of each of the eight templates. Then modify the corresponding sample data to get the desired transmit pulse shape. Secondly, through the value of SCAL[5:0] bits increased or decreased by 1, the pulse amplitude can be scaled up or down at the percentage ratio against the standard pulse amplitude if needed. For different pulse shapes, the value of SCAL[5:0] bits and the scaling percentage ratio are different. The following eight tables list these values. Do the followings step by step, the desired waveform can be programmed, based on the selected waveform template: (1).Select the UI by UI[1:0] bits (TCF3, 05H...) (2).Specify the sample address in the selected UI by SAMP [3:0] bits (TCF3, 05H...) (3).Write sample data to WDAT[6:0] bits (TCF4, 06H...). It contains the data to be stored in the RAM, addressed by the selected UI and the corresponding sample address. Sample UI 1 UI 2 UI 3 UI 4 1 0000000 0000000 0000000 0000000 2 0000000 0000000 0000000 0000000 3 0000000 0000000 0000000 0000000 4 0001100 0000000 0000000 0000000 5 0110000 0000000 0000000 0000000 6 0110000 0000000 0000000 0000000 7 0110000 0000000 0000000 0000000 8 0110000 0000000 0000000 0000000 9 0110000 0000000 0000000 0000000 10 0110000 0000000 0000000 0000000 11 0110000 0000000 0000000 0000000 12 0110000 0000000 0000000 0000000 13 0000000 0000000 0000000 0000000 14 0000000 0000000 0000000 0000000 15 0000000 0000000 0000000 0000000 16 0000000 0000000 0000000 0000000 SCAL[5:0] = 100001 (default), One step change of this value of SCAL[5:0] results in 3% scaling up/down against the pulse amplitude. 15 INDUSTRIAL TEMPERATURE RANGES QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT Table-3 Transmit Waveform Value For E1 120 Ω Table-5 Transmit Waveform Value For T1 133~266 ft Sample UI 1 UI 2 UI 3 UI 4 Sample UI 1 UI 2 UI 3 UI 4 1 0000000 0000000 0000000 0000000 1 0011011 1000011 0000000 0000000 2 0000000 0000000 0000000 0000000 2 0101110 1000010 0000000 0000000 3 0000000 0000000 0000000 0000000 3 0101100 1000001 0000000 0000000 4 0001111 0000000 0000000 0000000 4 0101010 0000000 0000000 0000000 5 0111100 0000000 0000000 0000000 5 0101001 0000000 0000000 0000000 6 0111100 0000000 0000000 0000000 6 0101000 0000000 0000000 0000000 7 0111100 0000000 0000000 0000000 7 0100111 0000000 0000000 0000000 8 0111100 0000000 0000000 0000000 8 0100110 0000000 0000000 0000000 9 0111100 0000000 0000000 0000000 9 0100101 0000000 0000000 0000000 10 0111100 0000000 0000000 0000000 10 1010000 0000000 0000000 0000000 11 0111100 0000000 0000000 0000000 11 1001111 0000000 0000000 0000000 12 0111100 0000000 0000000 0000000 12 1001101 0000000 0000000 0000000 13 0000000 0000000 0000000 0000000 13 1001010 0000000 0000000 0000000 14 0000000 0000000 0000000 0000000 14 1001000 0000000 0000000 0000000 15 0000000 0000000 0000000 0000000 15 1000110 0000000 0000000 0000000 16 0000000 0000000 0000000 0000000 16 1000100 0000000 0000000 0000000 SCAL[5:0] = 100001 (default), One step change of this value of SCAL[5:0] results in 3% scaling up/down against the pulse amplitude. See Table-4 Table-6 Transmit Waveform Value For T1 266~399 ft Table-4 Transmit Waveform Value For T1 0~133 ft Sample UI 1 UI 2 UI 3 UI 4 Sample UI 1 UI 2 UI 3 UI 4 1 0011111 1000011 0000000 0000000 1 0010111 1000010 0000000 0000000 2 0110100 1000010 0000000 0000000 2 0100111 1000001 0000000 0000000 3 0101111 1000001 0000000 0000000 3 0100111 0000000 0000000 0000000 4 0101100 0000000 0000000 0000000 4 0100110 0000000 0000000 0000000 5 0101011 0000000 0000000 0000000 5 0100101 0000000 0000000 0000000 6 0101010 0000000 0000000 0000000 6 0100101 0000000 0000000 0000000 7 0101001 0000000 0000000 0000000 7 0100101 0000000 0000000 0000000 8 0101000 0000000 0000000 0000000 8 0100100 0000000 0000000 0000000 9 0100101 0000000 0000000 0000000 9 0100011 0000000 0000000 0000000 10 1010111 0000000 0000000 0000000 10 1001010 0000000 0000000 0000000 11 1010011 0000000 0000000 0000000 11 1001010 0000000 0000000 0000000 12 1010000 0000000 0000000 0000000 12 1001001 0000000 0000000 0000000 13 1001011 0000000 0000000 0000000 13 1000111 0000000 0000000 0000000 14 1001000 0000000 0000000 0000000 14 1000101 0000000 0000000 0000000 15 1000110 0000000 0000000 0000000 15 1000100 0000000 0000000 0000000 16 1000100 0000000 0000000 0000000 16 1000011 0000000 0000000 0000000 See Table-4 SCAL[5:0] = 1101101 (default), One step change of this value of SCAL[5:0] results in 2% scaling up/down against the pulse amplitude. 1. In T1 mode, when arbitrary pulse for short haul application is configured, users should write ‘110110’ to SCAL[5:0] bits if no scaling is required. 16 INDUSTRIAL TEMPERATURE RANGES QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT Table-7 Transmit Waveform Value For T1 399~533 ft Table-9 Transmit Waveform Value For J1 0~655 ft Sample UI 1 UI 2 UI 3 UI 4 Sample UI 1 UI 2 UI 3 UI 4 1 0100000 1000011 0000000 0000000 1 0010111 1000010 0000000 0000000 2 0111011 1000010 0000000 0000000 2 0100111 1000001 0000000 0000000 3 0110101 1000001 0000000 0000000 3 0100111 0000000 0000000 0000000 4 0101111 0000000 0000000 0000000 4 0100110 0000000 0000000 0000000 5 0101110 0000000 0000000 0000000 5 0100101 0000000 0000000 0000000 6 0101101 0000000 0000000 0000000 6 0100101 0000000 0000000 0000000 7 0101100 0000000 0000000 0000000 7 0100101 0000000 0000000 0000000 8 0101010 0000000 0000000 0000000 8 0100100 0000000 0000000 0000000 9 0101000 0000000 0000000 0000000 9 0100011 0000000 0000000 0000000 10 1011000 0000000 0000000 0000000 10 1001010 0000000 0000000 0000000 11 1011000 0000000 0000000 0000000 11 1001010 0000000 0000000 0000000 12 1010011 0000000 0000000 0000000 12 1001001 0000000 0000000 0000000 13 1001100 0000000 0000000 0000000 13 1000111 0000000 0000000 0000000 14 1001000 0000000 0000000 0000000 14 1000101 0000000 0000000 0000000 15 1000110 0000000 0000000 0000000 15 1000100 0000000 0000000 0000000 16 1000100 0000000 0000000 0000000 16 1000011 0000000 0000000 0000000 See Table-4 SCAL[5:0] = 110110 (default), One step change of this value of SCAL[5:0] results in 2% scaling up/down against the pulse amplitude. Table-8 Transmit Waveform Value For T1 533~655 ft Sample UI 1 UI 2 UI 3 UI 4 1 0100000 1000011 0000000 0000000 2 0111111 1000010 0000000 0000000 3 0111000 1000001 0000000 0000000 4 0110011 0000000 0000000 0000000 5 0101111 0000000 0000000 0000000 6 0101110 0000000 0000000 0000000 7 0101101 0000000 0000000 0000000 8 0101100 0000000 0000000 0000000 9 0101001 0000000 0000000 0000000 10 1011111 0000000 0000000 0000000 11 1011110 0000000 0000000 0000000 12 1010111 0000000 0000000 0000000 13 1001111 0000000 0000000 0000000 14 1001001 0000000 0000000 0000000 15 1000111 0000000 0000000 0000000 16 1000100 0000000 0000000 0000000 See Table-4 17 INDUSTRIAL TEMPERATURE RANGES QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT 3.2.4 of the recommended impedance matching for transmitter. TRANSMIT PATH LINE INTERFACE The TTIPn/TRINGn can be turned into high impedance globally by pulling THZ pin to high or individually by setting the THZ bit (TCF1, 03H...) to ‘1’. In this state, the internal transmit circuits are still active. The transmit line interface consists of TTIPn pin and TRINGn pin. The impedance matching can be realized by the internal impedance matching circuit or the external impedance matching circuit. If T_TERM[2] is set to ‘0’, the internal impedance matching circuit will be selected. In this case, the T_TERM[1:0] bits (TERM, 1AH...) can be set to choose 75 Ω, 100 Ω, 110 Ω or 120 Ω internal impedance of TTIPn/TRINGn. If T_TERM[2] is set to ‘1’, the internal impedance matching circuit will be disabled. In this case, the external impedance matching circuit will be used to realize the impedance matching. For T1/J1 mode, the external impedance matching circuit for the transmitter is not supported. Figure-8 shows the appropriate external components to connect with the cable for one channel. Table-10 is the list Besides, in the following cases, TTIPn/TRINGn will also become high impedance: • Loss of MCLK: all TTIPn/TRINGn pins become high impedance;· • Loss of TCLKn: corresponding TTIPn/TRINGn become HZ (exceptions: Remote Loopback; Transmit internal pattern by MCLK); • Transmit path power down; • After software reset; pin reset and power on. Table-10 Impedance Matching for Transmitter Cable Configuration Internal Termination T_TERM[2:0] PULS[3:0] E1/75 Ω 000 0000 E1/120 Ω 001 0001 T1/0~133 ft 1XX 0011 010 0101 T1/533~655 ft 0110 011 - 0111 Note: The precision of the resistors should be better than ± 1% 3.2.5 PULS[3:0] 0001 0001 RT 9.4 Ω 0Ω 0100 T1/399~533 ft J1/0~655 ft T_TERM[2:0] 0010 T1/133~266 ft T1/266~399 ft External Termination RT TRANSMIT PATH POWER DOWN The transmit path can be powered down individually by setting the T_OFF bit (TCF0, 02H...) to ‘1’. In this case, the TTIPn/TRINGn pins are turned into high impedance. 18 - - INDUSTRIAL TEMPERATURE RANGES QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT 3.3 RECEIVE PATH is set to ‘0’, the internal impedance matching circuit will be selected. In this case, the R_TERM[1:0] bits (TERM, 1AH...) can be set to choose 75 Ω, 100 Ω, 110 Ω or 120 Ω internal impedance of RTIPn/RRINGn. If R_TERM[2] is set to ‘1’, the internal impedance matching circuit will be disabled. In this case, the external impedance matching circuit will be used to realize the impedance matching. The receive path consists of Receive Internal Termination, Monitor Gain, Amplitude/Wave Shape Detector, Digital Tuning Controller, Adaptive Equalizer, Data Slicer, CDR (Clock and Data Recovery), Optional Jitter Attenuator, Decoder and LOS/AIS Detector. Refer to Figure-7. 3.3.1 RECEIVE INTERNAL TERMINATION Figure-8 shows the appropriate external components to connect with the cable for one channel. Table-11 is the list of the recommended impedance matching for receiver. The impedance matching can be realized by the internal impedance matching circuit or the external impedance matching circuit. If R_TERM[2] LOS/AIS Detector RTIP RRING Receive Internal termination Adaptive Equalizer Monitor Gain Data Slicer Clock and Data Recovery LOS RCLK Jitter Attenuator Decoder RDP RDN Figure-7 Receive Path Function Block Diagram Table-11 Impedance Matching for Receiver Cable Configuration Internal Termination External Termination R_TERM[2:0] RR R_TERM[2:0] 120 Ω 1XX RR E1/75 Ω 000 E1/120 Ω 001 120 Ω T1 010 100 Ω J1 011 110 Ω VDDRn • RX Line RR B • T X Line 2:1 • D7 One of the Four Identical Channels •· VDDRn D6 •· • D5 VDDTn D4 RT •· D3 RTIPn RRINGn TTIPn RT Note: 1. Common decoupling capacitor 2. Cp 0-560 (pF) 3. D1 - D8, Motorola - MBR0540T1; D1 • GNDRn 3.3 V VDDTn Cp 3 68µF 1 0.1µF 2 VDDTn D2 3.3 V VDDRn IDT82V2044E A D8 1:1 • • 75 Ω 68µF 1 0.1µF •· TRINGn GNDTn International Rectifier - 11DQ04 or 10BQ060 Figure-8 Transmit/Receive Line Circuit 19 • INDUSTRIAL TEMPERATURE RANGES QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT 3.3.2 3.3.4 LINE MONITOR The Receive Sensitivity for both E1 and T1/J1 is -10 dB. With the Adaptive Equalizer enabled, the receive sensitivity will be -20 dB. In both T1/J1 and E1 short haul applications, the non-intrusive monitoring on channels located in other chips can be performed by tapping the monitored channel through a high impedance bridging circuit. Refer to Figure9 and Figure-10. 3.3.5 3.3.6 DSX cross connect point monitor gain=0dB RRING normal receive mode 3.3.7 RTIP DECODER In T1/J1 applications, the R_MD[1:0] bits (RCF0, 07H...) is used to select the AMI decoder or B8ZS decoder. In E1 applications, the R_MD[1:0] bits (RCF0, 07H...) are used to select the AMI decoder or HDB3 decoder. monitor gain =22/26/32dB RRING 3.3.8 monitor mode RECEIVE PATH SYSTEM INTERFACE The receive path system interface consists of RCLKn pin, RDn/RDPn pin and RDNn pin. In E1 mode, the RCLKn outputs a recovered 2.048 MHz clock. In T1/J1 mode, the RCLKn outputs a recovered 1.544 MHz clock. The received data is updated on the RDn/RDPn and RDNn pins on the active edge of RCLKn. The active edge of RCLKn can be selected by the RCLK_SEL bit (RCF0, 07H...). And the active level of the data on RDn/ RDPn and RDNn can also be selected by the RD_INV bit (RCF0, 07H...). Figure-9 Monitoring Receive Line in Another Chip DSX cross connect point TTIP TRING The received data can be output to the system side in two different ways: Single Rail or Dual Rail, as selected by R_MD bit [1] (RCF0, 07H...). In Single Rail mode, only RDn pin is used to output data and the RDNn/CVn pin is used to report the received errors. In Dual Rail Mode, both RDPn pin and RDNn pin are used for outputting data. normal transmit mode RTIP monitor gain monitor gain =22/26/32dB RRING In the receive Dual Rail mode, the CDR unit can be by-passed by setting R_MD[1:0] to ‘11’ (binary). In this situation, the output data from the Data Slicer will be output to the RDPn/RDNn pins directly, and the RCLKn outputs the exclusive OR (XOR) of the RDPn and RDNn. monitor mode Figure-10 Monitor Transmit Line in Another Chip 3.3.3 CDR (Clock & Data Recovery) The CDR is used to recover the clock from the received signals. The recovered clock tracks the jitter in the data output from the Data Slicer and keeps the phase relationship between data and clock during the absence of the incoming pulse. The CDR can also be by-passed in the Dual Rail mode. When CDR is by-passed, the data from the Data Slicer is output to the RDPn/RDNn pins directly. RTIP R DATA SLICER The Data Slicer is used to generate a standard amplitude mark or a space according to the amplitude of the input signals. The threshold can be 40%, 50%, 60% or 70%, as selected by the SLICE[1:0] bits (RCF2, 09H...). The output of the Data Slicer is forwarded to the CDR (Clock & Data Recovery) unit or to the RDPn/RDNn pins directly if the CDR is disabled. After a high resistance bridging circuit, the signal arriving at the RTIPn/ RRINGn is dramatically attenuated. To compensate this attenuation, the Monitor Gain can be used to boost the signal by 22 dB, 26 dB and 32 dB, selected by MG[1:0] bits (RCF2, 09H...). For normal operation, the Monitor Gain should be set to 0 dB. R RECEIVE SENSITIVITY ADAPTIVE EQUALIZER 3.3.9 The Adaptive Equalizer can be enabled to increase the receive sensitivity and to allow programming of the LOS level up to -24 dB. See section 3.5 LOS AND AIS DETECTION. It can be enabled or disabled by setting EQ_ON bit to ‘1’ or ‘0’ (RCF1, 08H...). RECEIVE PATH POWER DOWN The receive path can be powered down individually by setting R_OFF bit (RCF0, 07H...) to ‘1’. In this case, the RCLKn, RDn/RDPn, RDPn and LOSn will be logic low. 20 INDUSTRIAL TEMPERATURE RANGES QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT The monitored line signal (transmit or receive) goes through Channel 1's Clock and Data Recovery. The signal can be observed digitally at the RCLK1, RD1/RDP1 and RDN1. If Channel 1 is configured to Remote Loopback while in the Monitoring mode, the monitored data will be output on TTIP1/TRING1. 3.3.10 G.772 NON-INTRUSIVE MONITORING In applications using only three channels, channel 1 can be configured to monitor the data received or transmitted in any one of the remaining channels. The MON[3:0] bits (GCF1, 60H) determine which channel and which direction (transmit/receive) will be monitored. The monitoring is non-intrusive per ITU-T G.772. Figure-11 illustrates the concept. Channel N (N > 2) LOSn LOS/AIS Detector RCLKn RDn/RDPn CVn/RDNn B8ZS/ HDB3/AMI Decoder Jitter Attenuator TCLKn TDn/TDPn TDNn B8ZS/ HDB3/AMI Encoder Jitter Attenuator Clock and Data Recovery Data Slicer Adaptive Equalizer Line Driver Waveform Shaper Receiver Internal Termination RTIPn Transmitter Internal Termination TTIPn Channel 1 LOS1 RCLK1 RDn/RDP1 CVn/RDN1 LOS/AIS Detector B8ZS/ HDB3/AMI Decoder Jitter Attenuator Clock and Data Recovery Data Slicer Adaptive Equalizer RRINGn TRINGn G.772 Monitor Receiver Internal Termination RTIP1 Transmitter Internal Termination TTIP1 RRING1 Remote Loopback TCLK1 TDn/TDP1 TDN1 B8ZS/ HDB3/AMI Encoder Jitter Attenuator Line Driver Waveform Shaper Figure-11 G.772 Monitoring Diagram 21 TRING1 INDUSTRIAL TEMPERATURE RANGES QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT 3.4 JITTER ATTENUATOR In E1 applications, the Corner Frequency of the DPLL can be 0.9 Hz or 6.8 Hz, as selected by the JABW bit (JACF, 01H...). In T1/J1 applications, the Corner Frequency of the DPLL can be 1.25 Hz or 5.00 Hz, as selected by the JABW bit (JACF, 01H...). The lower the Corner Frequency is, the longer time is needed to achieve synchronization. There is one Jitter Attenuator in each channel of the LIU. The Jitter Attenuator can be deployed in the transmit path or the receive path, and can also be disabled. This is selected by the JACF[1:0] bits (JACF, 01H...). 3.4.1 JITTER ATTENUATION FUNCTION DESCRIPTION When the incoming data moves faster than the outgoing data, the FIFO will overflow. This overflow is captured by the JAOV_IS bit (INTS1, 17H...). If the incoming data moves slower than the outgoing data, the FIFO will underflow. This underflow is captured by the JAUD_IS bit (INTS1, 17H...). For some applications that are sensitive to data corruption, the JA limit mode can be enabled by setting JA_LIMIT bit (JACF, 01H...) to ‘1’. In the JA limit mode, the speed of the outgoing data will be adjusted automatically when the FIFO is close to its full or emptiness. The criteria of starting speed adjustment are shown in Table-12. The JA limit mode can reduce the possibility of FIFO overflow and underflow, but the quality of jitter attenuation is deteriorated. The Jitter Attenuator is composed of a FIFO and a DPLL, as shown in Figure-12. The FIFO is used as a pool to buffer the jittered input data, then the data is clocked out of the FIFO by a de-jittered clock. The depth of the FIFO can be 32 bits, 64 bits or 128 bits, as selected by the JADP[1:0] bits (JACF, 01H...). Consequently, the constant delay of the Jitter Attenuator will be 16 bits, 32 bits or 64 bits. Deeper FIFO can tolerate larger jitter, but at the expense of increasing data latency time. Jittered Data Jittered Clock RDn/RDPn FIFO 32/64/128 W 3.4.2 De-jittered Data The performance of the Jitter Attenuator in the IDT82V2044E meets the ITU-T I.431, G.703, G.736-739, G.823, G.824, ETSI 300011, ETSI TBR12/ 13, AT&T TR62411 specifications. Details of the Jitter Attenuator performance is shown in Table-64 Jitter Tolerance and Table-65 Jitter Attenuator Characteristics. RDNn R DPLL JITTER ATTENUATOR PERFORMANCE De-jittered Clock RCLKn Table-12 Criteria of Starting Speed Adjustment MCLK Figure-12 Jitter Attenuator 22 FIFO Depth Criteria for Adjusting Data Outgoing Speed 32 Bits 2 bits close to its full or emptiness 64 Bits 3 bits close to its full or emptiness 128 Bits 4 bits close to its full or emptiness INDUSTRIAL TEMPERATURE RANGES QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT 3.5 LOS AND AIS DETECTION 3.5.1 LOS DETECTION • LOS detect level threshold With the Adaptive Equalizer off, the amplitude threshold Q is fixed on 800 mVpp, while P=Q+200 mVpp (200 mVpp is the LOS level detect hysteresis). The Loss of Signal Detector monitors the amplitude of the incoming signal level and pulse density of the received signal on RTIPn and RRINGn. With the Adaptive Equalizer on, the value of Q can be selected by LOS[4:0] bit (RCF1, 08H...), while P=Q+4 dB (4 dB is the LOS level detect hysteresis). Refer to Table 33, “RCF1: Receiver Configuration Register 1,” on page 40 for LOS[4:0] bit values available. • LOS declare (LOS=1) A LOS is detected when the incoming signal has “no transitions”, i.e., when the signal level is less than Q dB below nominal for N consecutive pulse intervals. Here N is defined by LAC bit (MAINT0, 0AH...). LOS will be declared by pulling LOSn pin to high (LOS=1) and LOS interrupt will be generated if it is not masked. • Criteria for declare and clear of a LOS detect The detection supports the ANSI T1.231 and I.431 for T1/J1 mode and G.775 and ETSI 300233/I.431 for E1 mode. The criteria can be selected by LAC bit (MAINT0, 0AH...) and T1E1 bit (GCF0, 40H). • LOS clear (LOS=0) The LOS is cleared when the incoming signal has “transitions”, i.e., when the signal level is greater than P dB below nominal and has an average pulse density of at least 12.5% for M consecutive pulse intervals, starting with the receipt of a pulse. Here M is defined by LAC bit (MAINT0, 0AH...). LOS status is cleared by pulling LOSn pin to low. Table-13 and Table-14 summarize LOS declare and clear criteria for both with and without the Adaptive Equalizer enabled. • All Ones output during LOS On the system side, the RDPn/RDNn will reflect the input pulse “transition” at the RTIPn/RRINGn side and output recovery clock (but the quality of the output clock can not be guaranteed when the input level is lower than the maximum receive sensitivity) when AISE bit (MAINT0, 0AH...) is 0; or output All Ones as AIS when AISE bit (MAINT0, 0AH...) is 1. In this case RCLKn output is replaced by MCLK. LOS=1 On the line side, the TTIPn/TRINGn will output All Ones as AIS when ATAO bit (MAINT0, 0AH...) is 1. The All Ones pattern uses MCLK as the reference clock. signal levelP density=OK (observing windows= M) LOS indicator is always active for all kinds of loopback modes. (observing windows= N) LOS=0 Figure-13 LOS Declare and Clear Table-13 LOS Declare and Clear Criteria, Adaptive Equalizer Disabled Control bit T1E1 LOS declare threshold LOS clear threshold LAC 0=T1.231 Level < 800 mVpp N=175 bits Level > 1 Vpp M=128 bits 12.5% mark density 1 Vpp M=128 bits 12.5% mark density 1 Vpp M=32 bits 12.5% mark density 1 Vpp M=32 bits 12.5% mark density Q+ 4dB M=128 bits 12.5% mark density Q+ 4dB M=128 bits I.431 Level detect range is -18 to -30 dB. 12.5% mark density Q+ 4dB M=32 bits 12.5% mark density Q+ 4dB M=32 bits 12.5% mark density