WAN PLL
IDT82V3285
Version 1
December 9, 2008
6024 Silver Creek Valley Road, San Jose, CA 95138
Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775
Printed in U.S.A.
© 2008 Integrated Device Technology, Inc.
DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry
described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other
rights, of Integrated Device Technology, Inc.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its
safety or effectiveness.
Table of Contents
FEATURES .............................................................................................................................................................................. 9
HIGHLIGHTS.................................................................................................................................................................................................... 9
MAIN FEATURES ............................................................................................................................................................................................ 9
OTHER FEATURES ......................................................................................................................................................................................... 9
APPLICATIONS....................................................................................................................................................................... 9
DESCRIPTION....................................................................................................................................................................... 10
FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11
1 PIN ASSIGNMENT ........................................................................................................................................................... 12
2 PIN DESCRIPTION .......................................................................................................................................................... 13
3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 18
3.1
3.2
3.3
RESET ........................................................................................................................................................................................................... 18
MASTER CLOCK .......................................................................................................................................................................................... 18
INPUT CLOCKS & FRAME SYNC SIGNAL ................................................................................................................................................. 19
3.3.1 Input Clocks .................................................................................................................................................................................... 19
3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 19
3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 20
3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 21
3.5.1 Activity Monitoring ......................................................................................................................................................................... 21
3.5.2 Frequency Monitoring ................................................................................................................................................................... 22
3.6 T0 / T4 DPLL INPUT CLOCK SELECTION .................................................................................................................................................. 23
3.6.1 External Fast Selection (T0 only) .................................................................................................................................................. 23
3.6.2 Forced Selection ............................................................................................................................................................................ 24
3.6.3 Automatic Selection ....................................................................................................................................................................... 24
3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 25
3.7.1 T0 / T4 DPLL Locking Detection ................................................................................................................................................... 25
3.7.1.1 Fast Loss .......................................................................................................................................................................... 25
3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 25
3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 25
3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 25
3.7.2 Locking Status ............................................................................................................................................................................... 25
3.7.3 Phase Lock Alarm (T0 only) .......................................................................................................................................................... 26
3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 27
3.8.1 Input Clock Validity ........................................................................................................................................................................ 27
3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 27
3.8.2.1 Revertive Switch ............................................................................................................................................................... 27
3.8.2.2 Non-Revertive Switch (T0 only) ........................................................................................................................................ 28
3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 28
3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 29
3.9.1 T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 29
3.9.2 T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 31
3.10 T0 / T4 DPLL OPERATING MODE ............................................................................................................................................................... 32
3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 32
3.10.1.1 Free-Run Mode ................................................................................................................................................................ 32
3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 32
3.10.1.3 Locked Mode .................................................................................................................................................................... 32
3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 32
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December 9, 2008
IDT82V3285
WAN PLL
3.14
3.15
3.16
3.17
3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 32
3.10.1.5 Holdover Mode ................................................................................................................................................................. 32
3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 33
3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 33
3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 33
3.10.1.5.4 Manual ........................................................................................................................................................... 33
3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 33
3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 33
3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 33
3.10.2.1 Free-Run Mode ................................................................................................................................................................ 33
3.10.2.2 Locked Mode .................................................................................................................................................................... 33
3.10.2.3 Holdover Mode ................................................................................................................................................................. 33
T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 35
3.11.1 PFD Output Limit ............................................................................................................................................................................ 35
3.11.2 Frequency Offset Limit .................................................................................................................................................................. 35
3.11.3 PBO (T0 only) ................................................................................................................................................................................. 35
3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 35
3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 35
3.11.5.1 T0 Path ............................................................................................................................................................................. 35
3.11.5.2 T4 Path ............................................................................................................................................................................. 36
T0 / T4 APLL ................................................................................................................................................................................................. 37
OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 37
3.13.1 Output Clocks ................................................................................................................................................................................. 37
3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 39
MASTER / SLAVE CONFIGURATION ......................................................................................................................................................... 41
INTERRUPT SUMMARY ............................................................................................................................................................................... 42
T0 AND T4 SUMMARY ................................................................................................................................................................................. 42
POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 43
4.1
MASTER / SLAVE APPLICATION ............................................................................................................................................................... 44
5.1
5.2
5.3
5.4
5.5
EPROM MODE .............................................................................................................................................................................................. 46
MULTIPLEXED MODE .................................................................................................................................................................................. 47
INTEL MODE ................................................................................................................................................................................................. 49
MOTOROLA MODE ...................................................................................................................................................................................... 51
SERIAL MODE .............................................................................................................................................................................................. 53
7.1
7.2
REGISTER MAP ............................................................................................................................................................................................ 56
REGISTER DESCRIPTION ........................................................................................................................................................................... 61
7.2.1 Global Control Registers ............................................................................................................................................................... 61
7.2.2 Interrupt Registers ......................................................................................................................................................................... 70
7.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 74
7.2.4 Input Clock Quality Monitoring Configuration & Status Registers ........................................................................................... 85
7.2.5 T0 / T4 DPLL Input Clock Selection Registers ............................................................................................................................. 96
7.2.6 T0 / T4 DPLL State Machine Control Registers ......................................................................................................................... 101
7.2.7 T0 / T4 DPLL & APLL Configuration Registers .......................................................................................................................... 103
7.2.8 Output Configuration Registers .................................................................................................................................................. 117
7.2.9 PBO & Phase Offset Control Registers ...................................................................................................................................... 124
7.2.10 Synchronization Configuration Registers ................................................................................................................................. 126
3.11
3.12
3.13
4 TYPICAL APPLICATION ................................................................................................................................................. 44
5 MICROPROCESSOR INTERFACE .................................................................................................................................. 45
6 JTAG ................................................................................................................................................................................ 55
7 PROGRAMMING INFORMATION .................................................................................................................................... 56
8 THERMAL MANAGEMENT ........................................................................................................................................... 127
8.1
8.2
JUNCTION TEMPERATURE ...................................................................................................................................................................... 127
EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 127
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WAN PLL
8.3
8.4
HEATSINK EVALUATION .......................................................................................................................................................................... 127
TQFP EPAD THERMAL RELEASE PATH ................................................................................................................................................. 128
9.1
9.2
9.3
ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 129
RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 129
I/O SPECIFICATIONS ................................................................................................................................................................................. 130
9.3.1 CMOS Input / Output Port ............................................................................................................................................................ 130
9.3.2 PECL / LVDS Input / Output Port ................................................................................................................................................ 131
9.3.2.1 PECL Input / Output Port ................................................................................................................................................ 131
9.3.2.2 LVDS Input / Output Port ................................................................................................................................................ 133
JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 134
OUTPUT WANDER GENERATION ............................................................................................................................................................ 137
INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 138
OUTPUT CLOCK TIMING ........................................................................................................................................................................... 139
9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 129
9.4
9.5
9.6
9.7
PACKAGE DIMENSIONS.................................................................................................................................................... 144
ORDERING INFORMATION................................................................................................................................................ 147
Table of Contents
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December 9, 2008
List of Tables
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Table 47:
Table 48:
Pin Description ............................................................................................................................................................................................. 13
Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 18
Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 19
Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 20
Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 22
Input Clock Selection for T0 Path ................................................................................................................................................................ 23
Input Clock Selection for T4 Path ................................................................................................................................................................ 23
External Fast Selection ................................................................................................................................................................................ 23
Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 24
Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 25
Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 25
Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 26
Conditions of Qualified Input Clocks Available for T0 & T4 Selection ......................................................................................................... 27
Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 28
T0 DPLL Operating Mode Control ............................................................................................................................................................... 29
T4 DPLL Operating Mode Control ............................................................................................................................................................... 31
Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 31
Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 32
Frequency Offset Control in Holdover Mode ............................................................................................................................................... 33
Holdover Frequency Offset Read ................................................................................................................................................................ 33
Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 34
Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 36
Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 37
Outputs on OUT1 ~ OUT5 if Derived from T0/T4 DPLL Outputs ................................................................................................................ 37
Outputs on OUT1 ~ OUT5 if Derived from T0/T4 APLL .............................................................................................................................. 38
Synchronization Control ............................................................................................................................................................................... 39
Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 40
Device Master / Slave Control ..................................................................................................................................................................... 41
Related Bit / Register in Chapter 3.15 ......................................................................................................................................................... 42
Microprocessor Interface ............................................................................................................................................................................. 45
Access Timing Characteristics in EPROM Mode ......................................................................................................................................... 46
Read Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 47
Write Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 48
Read Timing Characteristics in Intel Mode .................................................................................................................................................. 49
Write Timing Characteristics in Intel Mode .................................................................................................................................................. 50
Read Timing Characteristics in Motorola Mode ........................................................................................................................................... 51
Write Timing Characteristics in Motorola Mode ........................................................................................................................................... 52
Read Timing Characteristics in Serial Mode ................................................................................................................................................ 53
Write Timing Characteristics in Serial Mode ................................................................................................................................................ 54
JTAG Timing Characteristics ....................................................................................................................................................................... 55
Register List and Map .................................................................................................................................................................................. 56
Power Consumption and Maximum Junction Temperature ....................................................................................................................... 127
Thermal Data ............................................................................................................................................................................................. 127
Absolute Maximum Rating ......................................................................................................................................................................... 129
Recommended Operation Conditions ........................................................................................................................................................ 129
CMOS Input Port Electrical Characteristics ............................................................................................................................................... 130
CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 130
CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 130
List of Tables
6
December 9, 2008
IDT82V3285
Table 49:
Table 50:
Table 51:
Table 52:
Table 53:
Table 54:
Table 55:
Table 56:
Table 57:
Table 58:
Table 59:
Table 60:
Table 61:
WAN PLL
CMOS Output Port Electrical Characteristics ............................................................................................................................................
PECL Input / Output Port Electrical Characteristics ...................................................................................................................................
LVDS Input / Output Port Electrical Characteristics ...................................................................................................................................
Output Clock Jitter Generation ..................................................................................................................................................................
Output Clock Phase Noise .........................................................................................................................................................................
Input Jitter Tolerance (155.52 MHz) ..........................................................................................................................................................
Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................
Input Jitter Tolerance (2.048 MHz) ............................................................................................................................................................
Input Jitter Tolerance (8 kHz) ....................................................................................................................................................................
T0 DPLL Jitter Transfer & Damping Factor ...............................................................................................................................................
T4 DPLL Jitter Transfer & Damping Factor ...............................................................................................................................................
Input/Output Clock Timing 3 ......................................................................................................................................................................
Output Clock Timing ..................................................................................................................................................................................
List of Tables
7
130
132
133
134
135
135
135
135
135
136
136
138
139
December 9, 2008
List of Figures
Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11
Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12
Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 20
Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 21
Figure 5. External Fast Selection ................................................................................................................................................................................ 23
Figure 6. Qualified Input Clocks for Automatic Selection ............................................................................................................................................ 24
Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 30
Figure 8. T4 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 31
Figure 9. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 39
Figure 10. 0.5 UI Early Frame Sync Input Signal Timing ............................................................................................................................................. 39
Figure 11. 0.5 UI Late Frame Sync Input Signal Timing .............................................................................................................................................. 40
Figure 12. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 40
Figure 13. Physical Connection Between Two Devices .............................................................................................................................................. 41
Figure 14. IDT82V3285 Power Decoupling Scheme ................................................................................................................................................... 43
Figure 15. Typical Application ...................................................................................................................................................................................... 44
Figure 16. EPROM Access Timing Diagram ............................................................................................................................................................... 46
Figure 17. Multiplexed Read Timing Diagram ............................................................................................................................................................. 47
Figure 18. Multiplexed Write Timing Diagram .............................................................................................................................................................. 48
Figure 19. Intel Read Timing Diagram ......................................................................................................................................................................... 49
Figure 20. Intel Write Timing Diagram ......................................................................................................................................................................... 50
Figure 21. Motorola Read Timing Diagram .................................................................................................................................................................. 51
Figure 22. Motorola Write Timing Diagram .................................................................................................................................................................. 52
Figure 23. Serial Read Timing Diagram (CLKE Asserted Low) ................................................................................................................................... 53
Figure 24. Serial Read Timing Diagram (CLKE Asserted High) .................................................................................................................................. 53
Figure 25. Serial Write Timing Diagram ....................................................................................................................................................................... 54
Figure 26. JTAG Interface Timing Diagram ................................................................................................................................................................. 55
Figure 27. Assembly for Expose Pad thermal Release Path (Side View) ................................................................................................................. 128
Figure 28. Recommended PECL Input Port Line Termination .................................................................................................................................. 131
Figure 29. Recommended PECL Output Port Line Termination ................................................................................................................................ 131
Figure 30. Recommended LVDS Input Port Line Termination .................................................................................................................................. 133
Figure 31. Recommended LVDS Output Port Line Termination ................................................................................................................................ 133
Figure 32. Output Wander Generation ...................................................................................................................................................................... 137
Figure 33. Input / Output Clock Timing ...................................................................................................................................................................... 138
Figure 34. Output Clock Timing ................................................................................................................................................................................. 139
Figure 35. 100-Pin EQG Package Dimensions (a) (in Millimeters) ............................................................................................................................ 144
Figure 36. 100-Pin EQG Package Dimensions (b) (in Millimeters) ............................................................................................................................ 145
Figure 37. EQG100 Recommended Land Pattern with Exposed Pad (in Millimeters) .............................................................................................. 146
List of Figures
8
December 9, 2008
WAN PLL
FEATURES
•
HIGHLIGHTS
•
•
The first single PLL chip:
• Features 0.5 mHz to 560 Hz bandwidth
• Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/
Option I) jitter generation requirements
• Provides node clocks for Cellular and WLL base-station (GSM
and 3G networks)
• Provides clocks for DSL access concentrators (DSLAM), especially for Japan TCM-ISDN network timing based ADSL equipments
•
•
•
•
•
•
•
MAIN FEATURES
•
•
•
•
•
•
•
•
•
•
•
Provides an integrated single-chip solution for Synchronous Equipment Timing Source, including Stratum 2, 3E, 3, SMC, 4E and 4
clocks
Employs DPLL and APLL to feature excellent jitter performance
and minimize the number of the external components
Integrates T0 DPLL and T4 DPLL; T4 DPLL locks independently or
locks to T0 DPLL
Supports Forced or Automatic operating mode switch controlled by
an internal state machine; the primary operating modes are FreeRun, Locked and Holdover
Supports programmable DPLL bandwidth (0.5 mHz to 560 Hz in 19
steps) and damping factor (1.2 to 20 in 5 steps)
Supports 1.1X10-5 ppm absolute holdover accuracy and 4.4X10-8
ppm instantaneous holdover accuracy
Supports PBO to minimize phase transients on T0 DPLL output to
be no more than 0.61 ns
Supports phase absorption when phase-time changes on T0
selected input clock are greater than a programmable limit over an
interval of less than 0.1 seconds
Supports programmable input-to-output phase offset adjustment
Limits the phase and frequency offset of the outputs
Supports manual and automatic selected input clock switch
•
Supports automatic hitless selected input clock switch on clock failure
Supports three types of input clock sources: recovered clock from
STM-N or OC-n, PDH network synchronization timing and external
synchronization reference timing
Provides a 2 kHz, 4 kHz or 8 kHz frame sync input signal, and a 2
kHz and an 8 kHz frame sync output signals
Provides 5 input clocks whose frequency cover from 2 kHz to
622.08 MHz
Provides 5 output clocks whose frequency cover from 1 Hz to
622.08 MHz
Provides output clocks for BITS, GPS, 3G, GSM, etc.
Supports PECL/LVDS and CMOS input/output technologies
Supports master clock calibration
Supports Master/Slave application (two chips used together) to
enable system protection against single chip failure
Meets Telcordia GR-1244-CORE, GR-253-CORE, GR-1377CORE, ITU-T G.812, ITU-T G.813 and ITU-T G.783 criteria
OTHER FEATURES
•
•
•
•
Multiple microprocessor interface modes: EPROM, Multiplexed,
Intel, Motorola and Serial
IEEE 1149.1 JTAG Boundary Scan
Single 3.3 V operation with 5 V tolerant CMOS I/Os
100-pin TQFP package, Green package options available
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
9
2008 Integrated Device Technology, Inc.
IDT82V3285
BITS / SSU
SMC / SEC (SONET / SDH)
DWDM cross-connect and transmission equipments
Central Office Timing Source and Distribution
Core and access IP switches / routers
Gigabit and Terabit IP switches / routers
IP and ATM core switches and access equipments
Cellular and WLL base-station node clocks
Broadband and multi-service access equipments
Any other telecom equipments that need synchronous equipment
system timing
December 9, 2008
DSC-6988/1
IDT82V3285
WAN PLL
DESCRIPTION
quency data acquired in Locked mode. Whatever the operating mode is,
the DPLL gives a stable performance without being affected by operating conditions or silicon process variations.
The IDT82V3285 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 2, 3E, 3, SMC, 4E and 4
clocks in SONET / SDH equipments, DWDM and Wireless base station,
such as GSM, 3G, DSL concentrator, Router and Access Network applications.
If the DPLL outputs are processed by T0/T4 APLL, the outputs of the
device will be in a better jitter/wander performance.
The device provides programmable DPLL bandwidths: 0.5 mHz to
560 Hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. Different
settings cover all SONET / SDH clock synchronization requirements.
The device supports three types of input clock sources: recovered
clock from STM-N or OC-n, PDH network synchronization timing and
external synchronization reference timing.
A high stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal
circuits in the device. It can be calibrated within ±741 ppm.
Based on ITU-T G.783 and Telcordia GR-253-CORE, the device consists of T0 and T4 paths. The T0 path is a high quality and highly configurable path to provide system clock for node timing synchronization
within a SONET / SDH network. The T4 path is simpler and less configurable for equipment synchronization. The T4 path locks independently
from the T0 path or locks to the T0 path.
All the read/write registers are accessed through a microprocessor
interface. The device supports five microprocessor interface modes:
EPROM, Multiplexed, Intel, Motorola and Serial.
In general, the device can be used in Master/Slave application. In
this application, two devices should be used together to enable system
protection against single chip failure. See Chapter 4 Typical Application
for details.
An input clock is automatically or manually selected for T0 and T4
each for DPLL locking. Both the T0 and T4 paths support three primary
operating modes: Free-Run, Locked and Holdover. In Free-Run mode,
the DPLL refers to the master clock. In Locked mode, the DPLL locks to
the selected input clock. In Holdover mode, the DPLL resorts to the fre-
Description
10
December 9, 2008
Functional Block Diagram
Priority
Priority
Selection
EX_SYNC1
Priority
Input Pre-Divider
Input Pre-Divider
Priority
Input Pre-Divider
Input Pre-Divider
Priority
Input Pre-Divider
IN5
IN1
IN2
IN3
IN4
Input
T0 Input
Selector
Monitors
T4 Input
Selector
11
Divider
T0 PFD
& LPF
MUX
T4 DPLL
OSCI
APLL
PBO
Phase Offset
T0 8 kHz
Divider
T4 PFD
& LPF
Microprocessor Interface
T0 DPLL
12E1/24T1/E3/T3
16E1/16T1
GSM/OBSAI/16E1/16T1
77.76 MHz
8 k Divider
T0 77.76 MHz
12E1/24T1/E3/T3
16E1/16T1
GSM/GPS/16E1/16T1
77.76 MHz
JTAG
T0
APLL
MUX
T4
APLL
MUX
T0
APLL
T4
APLL
Output
10
10
10
10
10
OUT5
MUX
OUT4
MUX
OUT3
MUX
OUT2
MUX
OUT1
MUX
Auto
Divider
Auto
Divider
Divider
Divider
Divider
Divider
Divider
MFRSYNC_2K
FRSYNC_8K
OUT5
OUT4
OUT3
OUT2
OUT1
IDT82V3285
WAN PLL
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
December 9, 2008
IDT82V3285
AD0/SDO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
83
82
80
78
77
76
79
VDDD6
DGND6
85
84
81
DGND7
VDDD7
86
87
90
NC
NC
AGND3
92
91
89
88
OUT3
OUT2
94
VDDA3
OUT1
IC5
NC
96
93
IC7
IC6
98
97
1
2
75
74
3
4
73
72
5
71
6
7
70
69
8
9
10
68
67
66
11
65
IDT82V3285
12
13
14
64
63
62
42
43
44
45
46
47
48
49
50
IN4_NEG
NC
EX_SYNC1
IN1
IN2
NC
DGND4
VDDD4
41
IN3_NEG
IN4_POS
40
39
VDD_DIFF2
IN3_POS
37
OUT5_NEG
GND_DIFF2
38
36
OUT5_POS
51
34
35
25
OUT4_POS
OUT4_NEG
24
54
53
52
33
22
23
32
55
GND_DIFF1
VDD_DIFF1
21
30
31
57
56
FRSYNC_8K
MFRSYNC_2K
19
20
28
29
60
59
58
NC
DGND8
16
17
18
27
61
26
15
VDDD8
NC
AGND
TRST
IC1
IC2
AGND1
VDDA1
TMS
INT_REQ
TCK
OSCI
DGND1
VDDD1
VDDD3
DGND3
DGND2
VDDD2
IC3
FF_SRCSW
VDDA2
AGND2
TDO
IC4
TDI
NC
NC
95
SONET/SDH
MS/SL
99
PIN ASSIGNMENT
100
1
WAN PLL
RDY
RST
ALE/SCLK
RD
WR
CS
A0/SDI
A1/CLKE
A2
A3
A4
A5
A6
DGND5
VDDD5
MPU_MODE0
MPU_MODE1
MPU_MODE2
NC
NC
NC
IN5
NC
NC
NC
Figure 2. Pin Assignment (Top View)
Pin Assignment
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IDT82V3285
2
WAN PLL
PIN DESCRIPTION
Table 1: Pin Description
Name
Pin No.
I/O
Description 1
Type
Global Control Signal
OSCI
10
I
CMOS
FF_SRCSW
18
I
pull-down
CMOS
MS/SL
99
I
pull-up
OSCI: Crystal Oscillator Master Clock
A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the
master clock for the device.
FF_SRCSW: External Fast Selection Enable
During reset, this pin determines the default value of the EXT_SW bit (b4, 0BH) 2. The
EXT_SW bit determines whether the External Fast Selection is enabled.
High: The default value of the EXT_SW bit (b4, 0BH) is ‘1’ (External Fast selection is
enabled);
Low: The default value of the EXT_SW bit (b4, 0BH) is ‘0’ (External Fast selection is disabled).
After reset, this pin selects an input clock pair for the T0 DPLL if the External Fast selection is
enabled:
High: Pair IN1 / IN3 is selected.
Low: Pair IN2/ IN4 is selected.
After reset, the input on this pin takes no effect if the External Fast selection is disabled.
CMOS
MS/SL: Master / Slave Selection
This pin, together with the MS_SL_CTRL bit (b0, 13H), controls whether the device is configured as the Master or as the Slave. Refer to Chapter 3.14 Master / Slave Configuration for
details.
The signal level on this pin is reflected by the MASTER_SLAVE bit (b1, 09H).
SONET/SDH
100
I
pull-down
CMOS
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, the value on this pin takes no effect.
RST
74
I
pull-up
CMOS
RST: Reset
A low pulse of at least 50 µs on this pin resets the device. After this pin is high, the device will
still be held in reset state for 500 ms (typical).
Frame Synchronization Input Signal
EX_SYNC1
45
I
pull-down
CMOS
EX_SYNC1: External Sync Input 1
A 2 kHz, 4 kHz or 8 kHz signal is input on this pin.
Input Clock
IN1
46
IN2
47
IN3_POS
40
IN3_NEG
41
IN4_POS
42
IN4_NEG
43
Pin Description
IN1: Input Clock 1
I
CMOS
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
pull-down
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN2: Input Clock 2
I
CMOS
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
pull-down
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN3_POS / IN3_NEG: Positive / Negative Input Clock 3
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
I
PECL/LVDS 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz
clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is
automatically detected.
IN4_POS / IN4_NEG: Positive / Negative Input Clock 4
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
I
PECL/LVDS 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz
clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is
automatically detected.
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IDT82V3285
WAN PLL
Table 1: Pin Description (Continued)
Name
IN5
Pin No.
54
I/O
I
pull-down
Type
Description 1
CMOS
IN5: Input Clock 5
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
In Slave operation, the frequency of the T0 selected input clock IN5 is recommended to be
6.48 MHz.
Output Frame Synchronization Signal
FRSYNC_8K
30
O
CMOS
MFRSYNC_2K
31
O
CMOS
FRSYNC_8K: 8 kHz Frame Sync Output
An 8 kHz signal is output on this pin.
MFRSYNC_2K: 2 kHz Multiframe Sync Output
A 2 kHz signal is output on this pin.
Output Clock
OUT1
90
O
OUT2
93
O
OUT3
94
O
OUT4_POS
34
OUT4_NEG
35
OUT5_POS
36
OUT5_NEG
37
O
O
OUT1: Output Clock 1
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
CMOS
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz or 155.52 MHz clock is output on this pin.
OUT2: Output Clock 2
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
CMOS
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz or 155.52 MHz clock is output on this pin.
OUT3: Output Clock 3
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
CMOS
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz or 155.52 MHz clock is output on this pin.
OUT4_POS / OUT4_NEG: Positive / Negative Output Clock 4
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
PECL/LVDS 5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially output on this pair
of pins.
OUT5_POS / OUT5_NEG: Positive / Negative Output Clock 5
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
PECL/LVDS 5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially output on this pair
of pins.
Microprocessor Interface
CS
70
I
pull-up
CMOS
INT_REQ
8
O
CMOS
Pin Description
CS: Chip Selection
A transition from high to low must occur on this pin for each read or write operation and this
pin should remain low until the operation is over.
INT_REQ: Interrupt Request
This pin is used as an interrupt request. The output characteristics are determined by the
HZ_EN bit (b1, 0CH) and the INT_POL bit (b0, 0CH).
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IDT82V3285
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Table 1: Pin Description (Continued)
Name
Pin No.
MPU_MODE0
60
MPU_MODE1
59
MPU_MODE2
58
A0 / SDI
69
A1 / CLKE
68
A2
67
A3
66
A4
65
A5
64
A6
63
AD0 / SDO
83
AD1
82
AD2
81
AD3
80
AD4
79
AD5
78
AD6
77
AD7
76
I/O
I
pull-down
I
pull-down
CMOS
MPU_MODE[2:0]: Microprocessor Interface Mode Selection
The device supports five microprocessor interface modes: EPROM, Multiplexed, Intel, Motorola and Serial.
During reset, these pins determine the default value of the MPU_SEL_CNFG[2:0] bits (b2~0,
7FH) as follows:
001 (EPROM mode);
010 (Multiplexed mode);
011 (Intel mode);
100 (Motorola mode);
101 (Serial mode);
110 - 111 (Reserved).
After reset, these pins are general purpose inputs. The microprocessor interface mode is
selected by the MPU_SEL_CNFG[2:0] bits (b2~0, 7FH).
The value of these pins is always reflected by the MPU_PIN_STS[2:0] bits (b2~0, 02H).
A[6:0]: Address Bus
In ERPOM, Intel and Motorola modes, these pins are the address bus of the microprocessor
interface.
SDI: Serial Data Input
In Serial mode, this pin is used as the serial data input. Address and data on this pin are serially clocked into the device on the rising edge of SCLK.
CMOS
CLKE: SCLK Active Edge Selection
In Serial mode, this pin selects the active edge of SCLK to update the SDO:
High - The falling edge;
Low - The rising edge.
In Multiplexed mode, A0/SDI, A1/CLKE and A[6:2] pins should be connected to ground.
In Serial mode, A[6:2] pins should be connected to ground.
AD[7:0]: Address / Data Bus
In EPROM, Intel and Motorola modes, these pins are the bi-directional data bus of the microprocessor interface.
In Multiplexed mode, these pins are the bi-directional address/data bus of the microprocessor interface.
I/O
pull-down
CMOS
SDO: Serial Data Output
In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked
out of the device on the active edge of SCLK.
In Serial mode, AD[7:1] pins should be connected to ground.
WR
71
I
pull-up
RD
72
I
pull-up
Pin Description
Description 1
Type
CMOS
WR: Write Operation
In Multiplexed and Intel modes, this pin is asserted low to initiate a write operation.
In Motorola mode, this pin is asserted low to initiate a write operation or s asserted high to initiate a read operation.
In EPROM and Serial modes, this pin should be connected to ground.
CMOS
RD: Read Operation
In Multiplexed and Intel modes, this pin is asserted low to initiate a read operation.
In EPROM, Motorola and Serial modes, this pin should be connected to ground.
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Table 1: Pin Description (Continued)
Name
Pin No.
I/O
Description 1
Type
ALE: Address Latch Enable
In Multiplexed mode, the address on AD[7:0] pins is sampled into the device on the falling
edge of ALE.
ALE / SCLK
RDY
73
75
I
pull-down
O
CMOS
CMOS
SCLK: Shift Clock
In Serial mode, a shift clock is input on this pin.
Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated
on the active edge of SCLK. The active edge is determined by the CLKE.
In EPROM, Intel and Motorola modes, this pin should be connected to ground.
RDY: Ready/Data Acknowledge
In Multiplexed and Intel modes, a high level on this pin indicates that a read/write cycle is
completed. A low level on this pin indicates that wait state must be inserted.
In Motorola mode, a low level on this pin indicates that valid information on the data bus is
ready for a read operation or acknowledges the acceptance of the written data during a write
operation.
In EPROM and Serial modes, this pin should be connected to ground.
JTAG (per IEEE 1149.1)
TRST
2
I
pull-down
CMOS
TMS
7
I
pull-up
CMOS
TCK
9
I
pull-down
CMOS
TDI
23
I
pull-up
CMOS
TDO
21
O
CMOS
TRST: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK.
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely
retain their state.
TDI: JTAG Test Data Input
The test data is input on this pin. It is clocked into the device on the rising edge of TCK.
TDO: JTAG Test Data Output
The test data is output on this pin. It is clocked out of the device on the falling edge of TCK.
TDO pin outputs a high impedance signal except during the process of data scanning.
This pin can indicate the interrupt of T0 selected input clock fail, as determined by the
LOS_FLAG_ON_TDO bit (b6, 0BH). Refer to Chapter 3.8.1 Input Clock Validity for details.
Power & Ground
VDDD1
12
VDDD2
16
VDDD3
13
VDDD4
50
VDDD5
61
VDDD6
85
VDDD7
86
Pin Description
VDDDn: 3.3 V Digital Power Supply
VDDDn connections should be connected using the recommended decoupling scheme
shown in Figure 14.
Power
-
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IDT82V3285
WAN PLL
Table 1: Pin Description (Continued)
Type
Description 1
Power
-
VDDAn: 3.3 V Analog Power Supply
VDDAn connections should be connected using the recommended decoupling scheme
shown in Figure 14.
Power
Power
Power
-
Ground
-
Name
Pin No.
I/O
VDDA1
6
VDDA2
19
VDDA3
VDDD8
VDD_DIFF1
VDD_DIFF2
DGND1
91
26
33
39
11
DGND2
15
DGND3
14
DGND4
49
DGND5
62
DGND6
84
DGND7
AGND1
87
5
AGND2
20
Ground
-
AGND3
GND_DIFF1
GND_DIFF2
DGND8
AGND
92
32
38
29
1
Ground
Ground
Ground
Ground
-
VDDD8: 3.3 V Digital Power Supply
VDD_DIFF1: 3.3 V Power Supply for OUT4
VDD_DIFF2: 3.3 V Power Supply for OUT5
DGNDn: Digital Ground
AGNDn: Analog Ground
GND_DIFF: Ground for OUT4
GND_DIFF: Ground for OUT5
DGND8: Digital Ground
AGND: Analog Ground
Others
IC1
3
IC2
4
IC3
17
IC4
22
IC5
96
IC6
97
IC7
98
24, 25, 27, 28, 44, 48,
51, 52, 53, 55, 56, 57,
88, 89, 95
NC
IC: Internally Connected
Internal Use. These pins should be left open for normal operation.
-
-
-
-
NC: Not Connected
Note:
1. All the unused input pins should be connected to ground; the output of all the unused output pins are don’t-care.
2. The contents in the brackets indicate the position of the register bit/bits.
3. N x 8 kHz: 1 < N < 19440.
4. N x E1: N = 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64.
5. N x T1: N = 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96.
6. N x 13.0 MHz: N = 1, 2, 4.
7. N x 3.84 MHz: N = 1, 2, 4, 8, 16, 10, 20, 40.
Pin Description
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IDT82V3285
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3
FUNCTIONAL DESCRIPTION
3.2
3.1
RESET
A nominal 12.8000 MHz clock, provided by a crystal oscillator, is
input on the OSCI pin. This clock is provided for the device as a master
clock. The master clock is used as a reference clock for all the internal
circuits. A better active edge of the master clock is selected by the
OSC_EDGE bit to improve jitter and wander performance.
The reset operation resets all registers and state machines to their
default value or status.
After power on, the device must be reset for normal operation.
MASTER CLOCK
In fact, an offset from the nominal frequency may input on the OSCI
pin. This offset can be compensated by setting the
NOMINAL_FREQ_VALUE[23:0] bits. The calibration range is within
±741 ppm.
For a complete reset, the RST pin must be asserted low for at least
50 µs. After the RST pin is pulled high, the device will still be in reset
state for 500 ms (typical). If the RST pin is held low continuously, the
device remains in reset state.
The performance of the master clock should meet GR-1244-CORE,
GR-253-CORE, ITU-T G.812 and G.813 criteria.
Table 2: Related Bit / Register in Chapter 3.2
Bit
Register
Address (Hex)
NOMINAL_FREQ_VALUE[23:0]
OSC_EDGE
NOMINAL_FREQ[23:16]_CNFG, NOMINAL_FREQ[15:8]_CNFG, NOMINAL_FREQ[7:0]_CNFG
DIFFERENTIAL_IN_OUT_OSCI_CNFG
06, 05, 04
0A
Functional Description
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IDT82V3285
3.3
WAN PLL
INPUT CLOCKS & FRAME SYNC SIGNAL
For SDH and SONET networks, the default frequency is different.
SONET / SDH frequency selection is controlled by the IN_SONET_SDH
bit. During reset, the default value of the IN_SONET_SDH bit is determined by the SONET/SDH pin: high for SONET and low for SDH. After
reset, the input signal on the SONET/SDH pin takes no effect.
Altogether 5 clocks and 1 frame sync signal are input to the device.
3.3.1
INPUT CLOCKS
The device provides 5 input clock ports.
3.3.2
According to the input port technology, the input ports support the following technologies:
• PECL/LVDS
• CMOS
A 2 kHz, 4 kHz or 8 kHz frame sync signal is input on the EX_SYNC1
pin. It is a CMOS input. The input frequency should match the setting in
the SYNC_FREQ[1:0] bits.
The frame sync input signal is used for frame sync output signal synchronization. Refer to Chapter 3.13.2 Frame SYNC Output Signals for
details.
According to the input clock source, the following clock sources are
supported:
• T1: Recovered clock from STM-N or OC-n
• T2: PDH network synchronization timing
• T3: External synchronization reference timing
Table 3: Related Bit / Register in Chapter 3.3
IN1, IN2 and IN5 support CMOS input signal only and the clock
sources can be from T1, T2 or T3.
IN3 and IN4 support PECL/LVDS input signal only and automatically
detect whether the signal is PECL or LVDS. The clock sources can be
from T1, T2 or T3.
Functional Description
FRAME SYNC INPUT SIGNALS
19
Bit
Register
Address (Hex)
IN_SONET_SDH
SYNC_FREQ[1:0]
INPUT_MODE_CNFG
09
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IDT82V3285
3.4
WAN PLL
INPUT CLOCK PRE-DIVIDER
Once the division factor is set for the input clock selected by the
PRE_DIV_CH_VALUE[3:0] bits, it is valid until a different division factor
is set for the same input clock. The division factor is calculated as follows:
Each input clock is assigned an internal Pre-Divider. The Pre-Divider
is used to divide the clock frequency down to the DPLL required frequency, which is no more than 38.88 MHz.
Division Factor = (the frequency of the clock input to the DivN
Divider ÷ the frequency of the DPLL required clock set by the
IN_FREQ[3:0] bits) - 1
For IN1 ~ IN5, the DPLL required frequency is set by the corresponding IN_FREQ[3:0] bits.
If the input clock is of 2 kHz, 4 kHz or 8 kHz, the Pre-Divider is
bypassed automatically and the corresponding IN_FREQ[3:0] bits
should be set to match the input frequency; the input clock can be
inverted, as determined by the IN_2K_4K_8K_INV bit.
The DivN Divider can only divide the input clock whose frequency is
lower than () 155.52 MHz. The input
clock can be divided by 4, 5 or can bypass the HF Divider, as determined by the IN3_DIV[1:0]/IN4_DIV[1:0] bits correspondingly.
The input clock on the IN4 pin is 622.08 MHz; the DPLL required
clock is 6.48 MHz by programming the IN_FREQ[3:0] bits of register IN4
to ‘0010’. Do the following step by step to divide the input clock:
1. Use the HF Divider to divide the clock down to 155.52 MHz:
622.08 ÷ 155.52 = 4, so set the IN4_DIV[1:0] bits to ‘01’;
2. Use the DivN Divider to divide the clock down to 6.48 MHz:
Set the PRE_DIV_CH_VALUE[3:0] bits to ‘0110’;
Set the DIRECT_DIV bit in Register IN4_CNFG to ‘1’ and the
LOCK_8K bit in Register IN4_CNFG to ‘0’;
155.52 ÷ 6.48 = 24; 24 - 1 = 23, so set the
PRE_DIVN_VALUE[14:0] bits to ‘10111’.
When the Lock 8k Divider is used, the input clock is divided down to
8 kHz automatically.
Either the DivN Divider or the Lock 8k Divider can be used or both
can be bypassed, as determined by the DIRECT_DIV bit and the
LOCK_8K bit.
When the DivN Divider is used for INn (1 ≤ n ≤ 5), the division factor
setting should observe the following order:
1. Select an input clock by the PRE_DIV_CH_VALUE[3:0] bits;
2. Write the lower eight bits of the division factor to the
PRE_DIVN_VALUE[7:0] bits;
3. Write the higher eight bits of the division factor to the
PRE_DIVN_VALUE[14:8] bits.
Pre-Divider
IN3_DIV[1:0] bits / IN4_DIV[1:0] bits
Input Clock INn
(1 ≤ n ≤ 5)
HF Divider
(for IN3 & IN4 only)
DIRECT_DIV bit
DivN Divider
LOCK_8K bit
Lock 8k Divider
DPLL required clock
Figure 3. Pre-Divider for An Input Clock
Table 4: Related Bit / Register in Chapter 3.4
Bit
IN3_DIV[1:0]
IN4_DIV[1:0]
IN_FREQ[3:0]
IN_2K_4K_8K_INV
DIRECT_DIV
LOCK_8K
PRE_DIV_CH_VALUE[3:0]
PRE_DIVN_VALUE[14:0]
Functional Description
Register
Address (Hex)
IN3_IN4_HF_DIV_CNFG
18
IN1_CNFG ~ IN5_CNFG
FR_MFR_SYNC_CNFG
16 ~ 17, 19 ~ 1A, 1F
74
IN1_CNFG ~ IN5_CNFG
16 ~ 17, 19 ~ 1A, 1F
PRE_DIV_CH_CNFG
PRE_DIVN[14:8]_CNFG, PRE_DIVN[7:0]_CNFG
23
25, 24
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December 9, 2008
IDT82V3285
3.5
WAN PLL
INPUT CLOCK QUALITY MONITORING
There are four configurations (0 - 3) for a leaky bucket accumulator.
The leaky bucket configuration for an input clock is selected by the corresponding BUCKET_SEL[1:0] bits. Each leaky bucket configuration
consists of four elements: upper threshold, lower threshold, bucket size
and decay rate.
The qualities of all the input clocks are always monitored in the following aspects:
• Activity
• Frequency
The bucket size is the capability of the accumulator. If the number of
the accumulated events reaches the bucket size, the accumulator will
stop increasing even if further events are detected. The upper threshold
is a point above which a no-activity alarm is raised. The lower threshold
is a point below which the no-activity alarm is cleared. The decay rate is
a certain period during which the accumulator decreases by 1 if no event
is detected.
Activity and frequency monitoring are conducted on all the input
clocks.
The qualified clocks are available for T0/T4 DPLL selection. The T0
and T4 selected input clocks have to be monitored further. Refer to
Chapter 3.7 Selected Input Clock Monitoring for details.
3.5.1
ACTIVITY MONITORING
The leaky bucket configuration is programmed by one of four groups
of register bits: the BUCKET_SIZE_n_DATA[7:0] bits, the UPPER_
THRESHOLD_n_DATA[7:0] bits, the LOWER_THRESHOLD_n_
DATA[7:0] bits and the DECAY_RATE_n_DATA[1:0] bits respectively; ‘n’
is 3.
Activity is monitored by using an internal leaky bucket accumulator,
as shown in Figure 4.
Each input clock is assigned an internal leaky bucket accumulator.
The input clock is monitored for each period of 128 ms and the internal
leaky bucket accumulator increases by 1 when an event is detected; it
decreases by 1 if no event is detected within the period set by the decay
rate. The event is that an input clock drifts outside (>) ±500 ppm with
respect to the master clock within a 128 ms period.
The no-activity alarm status of the input clock is indicated by the
INn_NO_ACTIVITY_ALARM bit (1 ≤ n ≤ 5).
The input clock with a no-activity alarm is disqualified for clock selection for T0/T4 DPLL.
clock signal with events
clock signal with no event
Input Clock
Decay
Rate
Bucket Size
Upper Threshold
Leaky Bucket Accumulator
Lower Threshold
0
No-activity Alarm Indication
Figure 4. Input Clock Activity Monitoring
Functional Description
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IDT82V3285
3.5.2
WAN PLL
The input clock with a frequency hard alarm is disqualified for clock
selection for T0/T4 DPLL.
FREQUENCY MONITORING
Frequency is monitored by comparing the input clock with a reference clock. The reference clock can be derived from the master clock or
the output of T0 DPLL, as determined by the FREQ_MON_CLK bit.
In addition, if the input clock is 2 kHz, 4 kHz or 8 kHz, its clock edges
with respect to the reference clock are monitored. If any edge drifts outside ±5%, the input clock is disqualified for clock selection for T0/T4
DPLL. The input clock is qualified if any edge drifts inside ±5%. This
function is supported only when the IN_NOISE_WINDOW bit is ‘1’.
A frequency hard alarm threshold is set for frequency monitoring. If
the FREQ_MON_HARD_EN bit is ‘1’, a frequency hard alarm is raised
when the frequency of the input clock with respect to the reference clock
is above the threshold; the alarm is cleared when the frequency is below
the threshold.
The frequency of each input clock with respect to the reference clock
can be read by doing the following step by step:
1. Select an input clock by setting the IN_FREQ_READ_CH[3:0]
bits;
2. Read the value in the IN_FREQ_VALUE[7:0] bits and calculate
as follows:
The frequency hard alarm threshold can be calculated as follows:
Frequency Hard Alarm Threshold (ppm) = (ALL_FREQ_HARD_
THRESHOLD[3:0] + 1) X FREQ_MON_FACTOR[3:0]
If the FREQ_MON_HARD_EN bit is ‘1’, the frequency hard alarm
status of the input clock is indicated by the INn_FREQ_HARD_ALARM
bit (1 ≤ n ≤ 5). When the FREQ_MON_HARD_EN bit is ‘0’, no frequency
hard alarm is raised even if the input clock is above the frequency hard
alarm threshold.
Input Clock Frequency (ppm) = IN_FREQ_VALUE[7:0] X
FREQ_MON_FACTOR[3:0]
Note that the value set by the FREQ_MON_FACTOR[3:0] bits
depends on the application.
Table 5: Related Bit / Register in Chapter 3.5
Bit
Register
Address (Hex)
BUCKET_SIZE_n_DATA[7:0] (n = 3)
UPPER_THRESHOLD_n_DATA[7:0] (n = 3)
LOWER_THRESHOLD_n_DATA[7:0] (n = 3)
DECAY_RATE_n_DATA[1:0] (n = 3)
BUCKET_SEL[1:0]
BUCKET_SIZE_3_CNFG
UPPER_THRESHOLD_3_CNFG
LOWER_THRESHOLD_3_CNFG
DECAY_RATE_3_CNFG
IN1_CNFG ~ IN5_CNFG
3F
3D
3E
40
16 ~ 17, 19 ~ 1A, 1F
IN1_IN2_STS, IN3_IN4_STS, IN5_STS
44~ 45, 48
MON_SW_PBO_CNFG
0B
ALL_FREQ_MON_THRESHOLD_CNFG
FREQ_MON_FACTOR_CNFG
PHASE_MON_PBO_CNFG
IN_FREQ_READ_CH_CNFG
IN_FREQ_READ_STS
2F
2E
78
41
42
INn_NO_ACTIVITY_ALARM ( 1 ≤ n ≤ 5)
INn_FREQ_HARD_ALARM (1 ≤ n ≤ 5)
FREQ_MON_CLK
FREQ_MON_HARD_EN
ALL_FREQ_HARD_THRESHOLD[3:0]
FREQ_MON_FACTOR[3:0]
IN_NOISE_WINDOW
IN_FREQ_READ_CH[3:0]
IN_FREQ_VALUE[7:0]
Functional Description
22
December 9, 2008
IDT82V3285
3.6
WAN PLL
T0 / T4 DPLL INPUT CLOCK SELECTION
Automatic selection is done based on the results of input clocks quality monitoring and the related registers configuration.
An input clock is selected for T0 DPLL and for T4 DPLL respectively.
The selected input clock is attempted to be locked in T0/T4 DPLL.
For T0 path, the EXT_SW bit and the T0_INPUT_SEL[3:0] bits determine the input clock selection, as shown in Table 6:
3.6.1
The External Fast selection is supported by T0 path only. In External
Fast selection, only IN1/IN3 and IN2/IN4 pairs are available for selection. Refer to Figure 5. The results of input clocks quality monitoring
(refer to Chapter 3.5 Input Clock Quality Monitoring) do not affect input
clock selection.
Table 6: Input Clock Selection for T0 Path
Control Bits
EXT_SW
T0_INPUT_SEL[3:0]
1
don’t-care
other than 0000
0000
0
EXTERNAL FAST SELECTION (T0 ONLY)
Input Clock Selection
External Fast selection
Forced selection
Automatic selection
The T0 input clock selection is determined by the FF_SRCSW pin
after reset (this pin determines the default value of the EXT_SW bit during reset, refer to Chapter 2 Pin Description), the
IN1_SEL_PRIORITY[3:0] bits and the IN2_SEL_PRIORITY[3:0] bits, as
shown in Figure 5 and Table 8:
For T4 path, the T4 DPLL may lock to a T0 DPLL output or lock independently from T0 path, as determined by the T4_LOCK_T0 bit. When
the T4 DPLL locks to the T0 DPLL output, the T4 selected input clock is
a 77.76 MHz or 8 kHz signal from the T0 DPLL 77.76 MHz path (refer to
Chapter 3.11.5.1 T0 Path), as determined by the T0_FOR_T4 bit. When
the T4 path locks independently from the T0 path, the T4 DPLL input
clock selection is determined by the T4_INPUT_SEL[3:0] bits. Refer to
Table 7:
IN1_SEL_PRIORITY[3:0] bits
FF_SRCSW pin
IN1
IN3
attempted to be
locked in T0 DPLL
Table 7: Input Clock Selection for T4 Path
Control Bits - T4_INPUT_SEL[3:0]
Input Clock Selection
IN2
other than 0000
0000
Forced selection
Automatic selection
IN4
External Fast selection is done between IN1/IN3 and IN2/IN4 pairs.
IN2_SEL_PRIORITY[3:0] bits
Forced selection is done by setting the related registers.
Figure 5. External Fast Selection
Table 8: External Fast Selection
Control Pin & Bits
FF_SRCSW (after reset)
IN1_SEL_PRIORITY[3:0]
IN2_SEL_PRIORITY[3:0]
high
0000
other than 0000
don’t-care
low
don’t-care
0000
other than 0000
Functional Description
23
Selected Input Clock
IN3
IN1
IN4
IN2
December 9, 2008
IDT82V3285
3.6.2
WAN PLL
depends on the results of input clock quality monitoring (refer to
Chapter 3.5 Input Clock Quality Monitoring). Locking allowance is configured by the corresponding INn_VALID bit(1 ≤ n ≤ 5). Refer to
Figure 6. In all the qualified input clocks, the one with the highest priority
is selected. The priority is set by the corresponding
INn_SEL_PRIORITY[3:0] bits (1 ≤ n ≤ 5). If more than one qualified
input clock INn is available and has the same priority, the input clock
with the smallest ‘n’ is selected.
FORCED SELECTION
In Forced selection, the selected input clock is set by the
T0_INPUT_SEL[3:0] / T4_INPUT_SEL[3:0] bits. The results of input
clocks quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring) do not affect the input clock selection.
3.6.3
AUTOMATIC SELECTION
In Automatic selection, the input clock selection is determined by its
validity, priority and locking allowance configuration. The validity
Validity
Priority
No
Locking Allowance
No
No
INn_SEL_PRIORITY[3:0]
'0000', ((1 ≤ n ≤ 5))
Input Clock Quality Monitoring
(Activity, Frequency)
INn = '1', (1 ≤ n ≤ 5)
INn_VALID = '0',
((1 ≤ n ≤ 5))
Yes
Yes
Yes
All qualified input clocks are available for Automatic selection
Figure 6. Qualified Input Clocks for Automatic Selection
Table 9: Related Bit / Register in Chapter 3.6
Bit
Register
Address (Hex)
EXT_SW
T0_INPUT_SEL[3:0]
T4_LOCK_T0
T0_FOR_T4
T4_INPUT_SEL[3:0]
MON_SW_PBO_CNFG
T0_INPUT_SEL_CNFG
0B
50
T4_INPUT_SEL_CNFG
51
IN1_IN2_SEL_PRIORITY_CNFG
IN3_IN4_SEL_PRIORITY_CNFG
IN5_SEL_PRIORITY_CNFG
REMOTE_INPUT_VALID1_CNFG,
REMOTE_INPUT_VALID2_CNFG
INPUT_VALID1_STS, INPUT_VALID2_STS
T4_T0_REG_SEL_CNFG
INn_SEL_PRIORITY[3:0] (1 ≤ n ≤ 5)
INn_VALID (1 ≤ n ≤ 5)
INn (1 ≤ n ≤ 5)
T4_T0_SEL
27 ~ 28, 2B
4C, 4D
4A, 4B
07
Note: * The setting in the 26 ~ 2C registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
Functional Description
24
December 9, 2008
IDT82V3285
3.7
WAN PLL
SELECTED INPUT CLOCK MONITORING
3.7.1.3
The T0/T4 DPLL compares the selected input clock with the feedback signal. If the phase-compared result exceeds the fine phase limit
programmed by the PH_LOS_FINE_LIMT[2:0] bits, a fine phase loss is
triggered. It is cleared once the phase-compared result is within the fine
phase limit.
The quality of the selected input clock is always monitored (refer to
Chapter 3.5 Input Clock Quality Monitoring) and the DPLL locking status
is always monitored.
3.7.1
T0 / T4 DPLL LOCKING DETECTION
The following events are always monitored:
• Fast Loss;
• Coarse Phase Loss;
• Fine Phase Loss;
• Hard Limit Exceeding.
3.7.1.1
The occurrence of the fine phase loss will result in T0/T4 DPLL being
unlocked if the FINE_PH_LOS_LIMT_EN bit is ‘1’.
3.7.1.4
A fast loss is triggered when the selected input clock misses 2 consecutive clock cycles. It is cleared once an active clock edge is detected.
For T0 path, the occurrence of the fast loss will result in T0 DPLL
being unlocked if the FAST_LOS_SW bit is ‘1’. For T4 path, the occurrence of the fast loss will result in T4 DPLL being unlocked regardless of
the FAST_LOS_SW bit.
Coarse Phase Loss
The DPLL soft limit is set by the DPLL_FREQ_SOFT_LIMT[6:0] bits
and can be calculated as follows:
The T0/T4 DPLL compares the selected input clock with the feedback signal. If the phase-compared result exceeds the coarse phase
limit, a coarse phase loss is triggered. It is cleared once the phase-compared result is within the coarse phase limit.
DPLL Soft Limit (ppm) = DPLL_FREQ_SOFT_LIMT[6:0] X 0.724
The DPLL hard limit is set by the DPLL_FREQ_HARD_LIMT[15:0]
bits and can be calculated as follows:
When the selected input clock is of 2 kHz, 4 kHz or 8 kHz, the coarse
phase limit depends on the MULTI_PH_8K_4K_2K_EN bit, the
WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to
Table 10. When the selected input clock is of other frequencies than 2
kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN
bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to Table 11.
DPLL Hard Limit (ppm) = DPLL_FREQ_HARD_LIMT[15:0] X 0.0014
3.7.2
0
Coarse Phase Limit
don’t-care
±1 UI
0
±1 UI
1
set by the PH_LOS_COARSE_LIMT[3:0] bits
1
If the FAST_LOS_SW bit, the COARSE_PH_LOS_LIMT_EN bit, the
FINE_PH_LOS_LIMT_EN bit or the FREQ_LIMT_PH_LOS bit is ‘0’, the
DPLL locking status will not be affected even if the corresponding event
is triggered. If all these bits are ‘0’, the DPLL will be in locked state in 2
seconds.
Table 11: Coarse Phase Limit Programming (the selected input
clock of other than 2 kHz, 4 kHz and 8 kHz)
WIDE_EN
Coarse Phase Limit
0
1
±1 UI
set by the PH_LOS_COARSE_LIMT[3:0] bits
The DPLL locking status is indicated by the T0_DPLL_LOCK /
T4_DPLL_LOCK bit.
The T4_STS 1 bit will be set when the locking status of the T4 DPLL
changes (from ‘locked’ to ‘unlocked’ or from ‘unlocked’ to ‘locked’). If the
T4_STS 2 bit is ‘1’, an interrupt will be generated.
The occurrence of the coarse phase loss will result in T0/T4 DPLL
being unlocked if the COARSE_PH_LOS_LIMT_EN bit is ‘1’.
Functional Description
LOCKING STATUS
The DPLL locking status depends on the locking monitoring results.
The DPLL is in locked state if none of the following events is triggered
during 2 seconds; otherwise, the DPLL is unlocked.
• Fast Loss (the FAST_LOS_SW bit is ‘1’);
• Coarse Phase Loss (the COARSE_PH_LOS_LIMT_EN bit is
‘1’);
• Fine Phase Loss (the FINE_PH_LOS_LIMT_EN bit is ‘1’);
• DPLL Hard Alarm (the FREQ_LIMT_PH_LOS bit is ‘1’).
Table 10: Coarse Phase Limit Programming (the selected input
clock of 2 kHz, 4 kHz or 8 kHz)
MULTI_PH_8K_4K
WIDE_EN
_2K_EN
Hard Limit Exceeding
Two limits are available for this monitoring. They are DPLL soft limit
and DPLL hard limit. When the frequency of the DPLL output with
respect to the master clock exceeds the DPLL soft / hard limit, a DPLL
soft / hard alarm will be raised; the alarm is cleared once the frequency
is within the corresponding limit. The occurrence of the DPLL soft alarm
does not affect the T0/T4 DPLL locking status. The DPLL soft alarm is
indicated by the corresponding T0_DPLL_SOFT_FREQ_ALARM /
T4_DPLL_SOFT_FREQ_ALARM bit. The occurrence of the DPLL hard
alarm will result in T0/T4 DPLL being unlocked if the
FREQ_LIMT_PH_LOS bit is ‘1’.
Fast Loss
3.7.1.2
Fine Phase Loss
25
December 9, 2008
IDT82V3285
3.7.3
WAN PLL
• Be cleared when a ‘1’ is written to the corresponding
INn_PH_LOCK_ALARM bit;
• Be cleared after the period (= TIME_OUT_VALUE[5:0] X
MULTI_FACTOR[1:0] in seconds) which starts from when the
alarm is raised.
PHASE LOCK ALARM (T0 ONLY)
A phase lock alarm will be raised when the selected input clock can
not be locked in T0 DPLL within a certain period. This period can be calculated as follows:
Period (sec.) = TIME_OUT_VALUE[5:0] X MULTI_FACTOR[1:0]
The selected input clock with a phase lock alarm is disqualified for T0
DPLL locking.
The phase lock alarm is indicated by the corresponding
INn_PH_LOCK_ALARM bit (1 ≤ n ≤ 5).
Note that no phase lock alarm is raised if the T4 selected input clock
can not be locked.
The phase lock alarm can be cleared by the following two ways, as
selected by the PH_ALARM_TIMEOUT bit:
Table 12: Related Bit / Register in Chapter 3.7
Bit
Register
Address (Hex)
PHASE_LOSS_FINE_LIMIT_CNFG
5B *
PHASE_LOSS_COARSE_LIMIT_CNFG
5A *
OPERATING_STS
52
DPLL_FREQ_SOFT_LIMIT_CNFG
65
DPLL_FREQ_HARD_LIMT[15:0]
DPLL_FREQ_HARD_LIMIT[15:8]_CNFG,
DPLL_FREQ_HARD_LIMIT[7:0]_CNFG
67, 66
T4_STS 1
INTERRUPTS3_STS
0F
INTERRUPTS3_ENABLE_CNFG
12
PHASE_ALARM_TIME_OUT_CNFG
08
IN1_IN2_STS, IN3_IN4_STS, IN5_STS
INPUT_MODE_CNFG
T4_T0_REG_SEL_CNFG
44 ~ 45, 48
09
07
FAST_LOS_SW
PH_LOS_FINE_LIMT[2:0]
FINE_PH_LOS_LIMT_EN
MULTI_PH_8K_4K_2K_EN
WIDE_EN
PH_LOS_COARSE_LIMT[3:0]
COARSE_PH_LOS_LIMT_EN
T0_DPLL_SOFT_FREQ_ALARM
T4_DPLL_SOFT_FREQ_ALARM
T0_DPLL_LOCK
T4_DPLL_LOCK
DPLL_FREQ_SOFT_LIMT[6:0]
FREQ_LIMT_PH_LOS
2
T4_STS
TIME_OUT_VALUE[5:0]
MULTI_FACTOR[1:0]
INn_PH_LOCK_ALARM (1 ≤ n ≤ 5)
PH_ALARM_TIMEOUT
T4_T0_SEL
Note: * The setting in the 5A and 5B registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
Functional Description
26
December 9, 2008
IDT82V3285
3.8
WAN PLL
SELECTED INPUT CLOCK SWITCH
For T0 path, Revertive and Non-Revertive switches are supported,
as selected by the REVERTIVE_MODE bit.
If the input clock is selected by External Fast selection or by Forced
selection, it can be switched by setting the related registers (refer to
Chapter 3.6.1 External Fast Selection (T0 only) & Chapter 3.6.2 Forced
Selection) any time. In this case, whether the input clock is qualified for
DPLL locking does not affect the clock switch. If the T4 selected input
clock is a T0 DPLL output, it can only be switched by setting the
T0_FOR_T4 bit.
For T4 path, only Revertive switch is supported.
The difference between Revertive and Non-Revertive switches is
that whether the selected input clock is switched when another qualified
input clock with a higher priority than the current selected input clock is
available for selection. In Non-Revertive switch, input clock switch is
minimized.
When the input clock is selected by Automatic selection, the input
clock switch depends on its validity, priority and locking allowance configuration. If the current selected input clock is disqualified, a new qualified input clock may be switched to.
3.8.1
Conditions of the qualified input clocks available for T0 selection are
different from that for T4 selection, as shown in Table 13:
Table 13: Conditions of Qualified Input Clocks Available for T0 & T4
Selection
INPUT CLOCK VALIDITY
Conditions of Qualified Input Clocks Available for T0 & T4 Selection
For all the input clocks, the validity depends on the results of input
clock quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring). When all of the following conditions are satisfied, the input clock
is valid; otherwise, it is invalid.
• No no-activity alarm (the INn_NO_ACTIVITY_ALARM bit is ‘0’);
• No frequency hard alarm (the INn_FREQ_HARD_ALARM bit is
‘0’);
• If the IN_NOISE_WINDOW bit is ‘1’, all the edges of the input
clock of 2 kHz, 4 kHz or 8 kHz drift inside ±5%; if the
IN_NOISE_WINDOW bit is ‘0’, this condition is ignored.
• Valid, i.e., the INn 1 bit is ‘1’;
• Priority enabled, i.e., the corresponding INn_SEL_PRIORITY[3:0] bits
T0 are not ‘0000’;
• Locking to the input clock is allowed, i.e., the corresponding INn_VALID
bit is ‘0’.
• Valid (all the validity conditions listed in Chapter 3.8.1 Input Clock Validity are satisfied);
• Priority enabled, i.e., the corresponding INn_SEL_PRIORITY[3:0] bits
T4
are not ‘0000’;
• Locking to the input clock is allowed, i.e., the corresponding INn_VALID
bit is ‘0’.
The validity qualification of the T0 selected input clock is different
from that of the T4 selected input clock. The validity qualification of the
T4 selected input clock is the same as the above. The T0 selected input
clock is valid when all of the above and the following conditions are satisfied; otherwise, it is invalid.
• No phase lock alarm, i.e., the INn_PH_LOCK_ALARM bit is ‘0’;
• If the ULTR_FAST_SW bit is ‘1’, the T0 selected input clock
misses less than (T
ns
Note:
* Timing with RDY. If RDY is not used, tpw1 is 3.5T + 10.
Microprocessor Interface
47
December 9, 2008
IDT82V3285
WAN PLL
tpw3
tT
ALE
th1
tsu1
CS
RD
th2
tpw1
tsu2
WR
th4
tsu3
AD[7:0]
data
address
td2
RDY
tpw2
th3
td5
High-Z
High-Z
td6
Figure 18. Multiplexed Write Timing Diagram
Table 33: Write Timing Characteristics in Multiplexed Mode
Symbol
Parameter
Min
Typ
Max
Unit
T
One cycle time of the master clock
12.86
ns
tin
Delay of input pad
5
ns
tout
Delay of output pad
5
ns
tsu1
Valid address to ALE falling edge setup time
2
ns
tsu2
Valid CS to valid WR setup time
0
ns
tsu3
Valid data to WR rising edge setup time
3
td2
Valid CS to valid RDY delay time
13
ns
td5
WR rising edge to RDY low delay time
13
ns
td6
CS rising edge to RDY release delay time
13
ns
tpw1
Valid WR pulse width low
1.5T + 10
ns
tpw2
Valid RDY pulse width low
1.5T + 10
ns
tpw3
Valid ALE pulse width high
2
ns
th1
Valid address after ALE falling edge hold time
3
ns
th2
Valid CS after WR rising edge hold time
0
ns
th3
Valid WR after RDY rising edge hold time
0
ns
th4
ns
Valid data after WR rising edge hold time
9
ns
tT
Time between ALE falling edge and WR falling edge
0
ns
tTI
Time between consecutive Write-Read or Write-Write accesses
(WR rising edge to ALE rising edge)
>7T
ns
Microprocessor Interface
48
December 9, 2008
IDT82V3285
5.3
WAN PLL
INTEL MODE
CS
WR
tpw1
tsu2
th2
RD
th1
tsu1
A[6:0]
address
td4
td1
High-Z
td2
RDY
High-Z
data
AD[7:0]
tpw2
th3
td5
High-Z
High-Z
td6
Figure 19. Intel Read Timing Diagram
Table 34: Read Timing Characteristics in Intel Mode
Symbol
Parameter
Min
Typ
Max
Unit
T
One cycle time of the master clock
12.86
ns
tin
Delay of input pad
5
ns
tout
Delay of output pad
5
ns
tsu1
Valid address to valid CS setup time
0
ns
tsu2
Valid CS to valid RD setup time
0
ns
td1
Valid RD to valid data delay time
3.5T + 10
ns
td2
Valid CS to valid RDY delay time
13
ns
td4
RD rising edge to AD[7:0] high impedance delay time
10
ns
td5
RD rising edge to RDY low delay time
13
ns
td6
CS rising edge to RDY release delay time
13
ns
tpw1
Valid RD pulse width low
4.5T + 10 *
ns
tpw2
Valid RDY pulse width low
4.5T + 10
ns
th1
Valid address after RD rising edge hold time
0
ns
th2
Valid CS after RD rising edge hold time
0
ns
th3
Valid RD after RDY rising edge hold time
0
ns
tTI
Time between consecutive Read-Read or Read-Write accesses
(RD rising edge to RD falling edge, or RD rising edge to WR falling edge)
>T
ns
Note:
* Timing with RDY. If RDY is not used, tpw1 is 3.5T + 10.
Microprocessor Interface
49
December 9, 2008
IDT82V3285
WAN PLL
CS
tsu2
tpw1
th2
WR
RD
tsu1
th1
A[6:0]
address
tsu3
AD[7:0]
data
td2
RDY
th4
tpw2
th3
td5
High-Z
High-Z
td6
Figure 20. Intel Write Timing Diagram
Table 35: Write Timing Characteristics in Intel Mode
Symbol
Parameter
Min
Typ
Max
Unit
T
One cycle time of the master clock
12.86
ns
tin
Delay of input pad
5
ns
tout
Delay of output pad
5
ns
tsu1
Valid address to valid CS setup time
0
ns
tsu2
Valid CS to valid WR setup time
0
ns
tsu3
Valid data before WR rising edge setup time
3
ns
td2
Valid CS to valid RDY delay time
13
ns
td5
WR rising edge to RDY low delay time
13
ns
td6
CS rising edge to RDY release delay time
13
ns
tpw1
Valid WR pulse width low
1.5T + 10
ns
tpw2
Valid RDY pulse width low
1.5T + 10
ns
th1
Valid address after WR rising edge hold time
0
ns
th2
Valid CS after WR rising edge hold time
0
ns
th3
Valid WR after RDY rising edge hold time
0
ns
th4
Valid data after WR rising edge hold time
9
ns
tTI
Time between consecutive Write-Read or Write-Write accesses
(WR rising edge to WR falling edge, or WR rising edge to RD falling edge)
>7T
ns
Microprocessor Interface
50
December 9, 2008
IDT82V3285
5.4
WAN PLL
MOTOROLA MODE
tpw1
CS
th2
tsu2
WR
th1
tsu1
address
A[6:0]
td3
td1
AD[7:0]
High-Z
data
td2
RDY
tpw2
th3
High-Z
tr1
td4
High-Z
High-Z
Figure 21. Motorola Read Timing Diagram
Table 36: Read Timing Characteristics in Motorola Mode
Symbol
Parameter
Min
Typ
T
One cycle time of the master clock
12.86
tin
Delay of input pad
5
Max
Unit
ns
tout
Delay of output pad
tsu1
Valid address to valid CS setup time
0
ns
tsu2
Valid WR to valid CS setup time
0
ns
td1
Valid CS to valid data delay time
td2
Valid CS to valid RDY delay time
13
ns
td3
CS rising edge to AD[7:0] high impedance delay time
10
ns
td4
CS rising edge to RDY release delay time
13
ns
tpw1
Valid CS pulse width low
4.5T + 10 *
ns
tpw2
Valid RDY pulse width high
4.5T + 10
ns
th1
Valid address after CS rising edge hold time
0
ns
th2
Valid WR after CS rising edge hold time
0
ns
th3
Valid CS after RDY falling edge hold time
0
tr1
RDY release time
tTI
Time between consecutive Read-Read or Read-Write accesses
(CS rising edge to CS falling edge)
5
ns
3.5T + 10
ns
3
>T
ns
ns
ns
Note:
* Timing with RDY. If RDY is not used, tpw1 is 3.5T +10.
Microprocessor Interface
51
December 9, 2008
IDT82V3285
WAN PLL
tpw1
CS
th2
tsu2
WR
tsu1
th1
A[6:0]
address
th4
tsu3
AD[7:0]
data
td2
RDY
th3
tpw2
tr1
td4
High-Z
High-Z
Figure 22. Motorola Write Timing Diagram
Table 37: Write Timing Characteristics in Motorola Mode
Symbol
Parameter
T
One cycle time of the master clock
Min
Typ
12.86
Max
Unit
ns
tin
Delay of input pad
5
ns
tout
Delay of output pad
5
ns
tsu1
Valid address to valid CS setup time
0
ns
tsu2
Valid WR to valid CS setup time
0
ns
tsu3
Valid data before CS rising edge setup time
3
ns
td2
Valid CS to valid RDY delay time
13
ns
td4
CS rising edge to RDY release delay time
13
ns
tpw1
Valid CS pulse width low
1.5T + 10
ns
tpw2
Valid RDY pulse width high
1.5T + 10
ns
th1
Valid address after valid CS rising edge hold time
0
ns
th2
Valid WR after valid CS rising edge hold time
0
ns
th3
Valid CS after RDY falling edge hold time
0
ns
th4
Valid data after valid CS rising edge hold time
9
tr1
RDY release time
tTI
Time between consecutive Write-Write or Write-Read accesses
(CS rising edge to CS falling edge)
Microprocessor Interface
ns
3
52
> 7T
ns
ns
December 9, 2008
IDT82V3285
5.5
WAN PLL
SERIAL MODE
ing edge of SCLK. When CLKE is asserted high, data on SDO will be
clocked out on the falling edge of SCLK.
In a read operation, the active edge of SCLK is selected by CLKE.
When CLKE is asserted low, data on SDO will be clocked out on the ris-
In a write operation, data on SDI will be clocked in on the rising edge
of SCLK.
CS
SCLK
tsu1
th1
tpw1
R/W
SDI
th2
tpw2
tsu2
A0
A1
A2
A3
A4
A5
A6
td1
High-Z
SDO
td2
D0
D1
D2
D3
D4
D5
D6
D7
Figure 23. Serial Read Timing Diagram (CLKE Asserted Low)
CS
th2
SCLK
SDI
R/W
A0
A1
A2
A3
A4
A5
A6
td1
High-Z
td2
D0
SDO
D1
D2
D3
D4
D5
D6
D7
Figure 24. Serial Read Timing Diagram (CLKE Asserted High)
Table 38: Read Timing Characteristics in Serial Mode
Symbol
Parameter
Min
Typ
Max
Unit
T
One cycle time of the master clock
12.86
ns
tin
Delay of input pad
5
ns
tout
Delay of output pad
5
ns
tsu1
Valid SDI to valid SCLK setup time
4
tsu2
Valid CS to valid SCLK setup time
14
td1
Valid SCLK to valid data delay time
10
ns
td2
CS rising edge to SDO high impedance delay time
10
ns
tpw1
SCLK pulse width low
3.5T + 5
ns
tpw2
SCLK pulse width high
3.5T + 5
ns
th1
Valid SDI after valid SCLK hold time
6
ns
th2
Valid CS after valid SCLK hold time (CLKE = 0/1)
5
ns
tTI
Time between consecutive Read-Read or Read-Write accesses
(CS rising edge to CS falling edge)
10
ns
Microprocessor Interface
53
ns
ns
December 9, 2008
IDT82V3285
WAN PLL
CS
tsu2
SCLK
th1
tpw1
tsu1
SDI
th2
tpw2
R/W
A0
A1
A2
A3
A4
A5
A6
D0
D1
D2
D3
D4
D5
D6
D7
High-Z
SDO
Figure 25. Serial Write Timing Diagram
Table 39: Write Timing Characteristics in Serial Mode
Symbol
Parameter
Min
Typ
Max
Unit
T
One cycle time of the master clock
12.86
ns
tin
Delay of input pad
5
ns
tout
Delay of output pad
5
ns
tsu1
Valid SDI to valid SCLK setup time
4
ns
tsu2
Valid CS to valid SCLK setup time
14
ns
tpw1
SCLK pulse width low
3.5T
ns
tpw2
SCLK pulse width high
3.5T
ns
th1
Valid SDI after valid SCLK hold time
6
ns
th2
Valid CS after valid SCLK hold time
5
ns
tTI
Time between consecutive Write-Write or Write-Read accesses
(CS rising edge to CS falling edge)
10
ns
Microprocessor Interface
54
December 9, 2008
IDT82V3285
6
WAN PLL
JTAG
This device is compliant with the IEEE 1149.1 Boundary Scan standard except the following:
• The output boundary scan cells do not capture data from the
core and the device does not support EXTEST instruction;
• The TRST pin is set low by default and JTAG is disabled in order
to be consistent with other manufacturers.
The JTAG interface timing diagram is shown in Figure 26.
tTCK
TCK
tS
tH
TMS
TDI
tD
TDO
Figure 26. JTAG Interface Timing Diagram
Table 40: JTAG Timing Characteristics
Symbol
JTAG
Parameter
Min
tTCK
Typ
Max
TCK period
100
ns
tS
TMS / TDI to TCK setup time
25
ns
tH
TCK to TMS / TDI Hold Time
25
ns
tD
TCK to TDO delay time
50
55
Unit
ns
December 9, 2008
IDT82V3285
7
WAN PLL
PROGRAMMING INFORMATION
The access of the Multi-word Registers is different from that of the
Single-word Registers. Take the registers (04H, 05H and 06H) for an
example, the write operation for the Multi-word Registers follows a fixed
sequence. The register (04H) is configured first and the register (06H) is
configured last. The three registers are configured continuously and
should not be interrupted by any operation. The crystal calibration configuration will take effect after all the three registers are configured. During read operation, the register (04H) is read first and the register (06H)
is read last. The crystal calibration reading should be continuous and not
be interrupted by any operation.
After reset, all the registers are set to their default values. The registers are read or written via the microprocessor interface.
Before any write operation, the value in register
PROTECTION_CNFG is recommended to be confirmed to make sure
whether the write operation is enabled. The device provides 3 register
protection modes:
• Protected mode: no other registers can be written except register
PROTECTION_CNFG itself;
• Fully Unprotected mode: all the writable registers can be written;
• Single Unprotected mode: one more register can be written
besides register PROTECTION_CNFG. After write operation
(not including writing a ‘1’ to clear a bit to ‘0’), the device automatically switches to Protected mode.
Certain bit locations within the device register map are designated as
Reserved. To ensure proper and predictable operation, bits designated
as Reserved should not be written by the users. In addition, their value
should be masked out from any testing or error detection methods that
are implemented.
Writing ‘0’ to the registers will take no effect if the registers are
cleared by writing ‘1’.
7.1
T0 and T4 paths share some registers, whose addresses are 27H,
28H, 2BH, 4EH, 4FH, 5AH, 5BH, 62H ~ 64H, 68H and 69H. The names
of shared registers are marked with a *. Before register read/write operation, register T4_T0_REG_SEL_CNFG is recommended to be confirmed to make sure whether the register operation is available for T0 or
T4 path.
REGISTER MAP
Table 41 is the map of all the registers, sorted in an ascending order
of their addresses.
Table 41: Register List and Map
Address
(Hex)
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reference
Page
Global Control Registers
00
01
02
04
05
06
07
08
09
0A
ID[7:0] - Device ID 1
ID[15:8] - Device ID 2
MPU_PIN_STS - MPU_MODE[2:0]
Pins Status
NOMINAL_FREQ[7:0]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 1
NOMINAL_FREQ[15:8]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 2
NOMINAL_FREQ[23:16]_CNFG
Crystal Oscillator Frequency Offset
Calibration Configuration 3
T4_T0_REG_SEL_CNFG - T0 / T4
Registers Selection Configuration
PHASE_ALARM_TIME_OUT_CNFG Phase Lock Alarm Time-Out Configuration
ID[7:0]
ID[15:8]
-
-
-
-
-
-
-
MPU_PIN_STS[2:0]
P 62
NOMINAL_FREQ_VALUE[7:0]
P 62
NOMINAL_FREQ_VALUE[15:8]
P 62
NOMINAL_FREQ_VALUE[23:16]
P 63
-
T4_T0_SE
L
MULTI_FACTOR[1:0]
-
-
-
-
TIME_OUT_VALUE[5:0]
AUTO_EX
PH_ALAR
INPUT_MODE_CNFG - Input Mode
EXT_SYN
T_SYNC_
M_TIMEO
Configuration
C_EN
EN
UT
DIFFERENTIAL_IN_OUT_OSCI_CNF
G - Differential Input / Output Port &
Master Clock Configuration
Programming Information
P 61
P 62
56
SYNC_FREQ[1:0]
-
-
P 63
P 64
IN_SONET MASTER_ REVERTIV
_SDH
SLAVE
E_MODE
P 65
OSC_EDG OUT5_PE OUT4_PE
E
CL_LVDS CL_LVDS
P 66
December 9, 2008
IDT82V3285
WAN PLL
Table 41: Register List and Map (Continued)
Address
(Hex)
0B
13
7E
7F
0C
0D
0E
0F
10
11
12
16
17
18
19
1A
1F
23
24
25
27
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MON_SW_PBO_CNFG - Frequency
LOS_FLA
FREQ_MO
FREQ_MO
ULTR_FAS
PBO_FRE
Monitor, Input Clock Selection & PBO
G_TO_TD
EXT_SW
PBO_EN
N_HARD_
N_CLK
T_SW
Z
Control
O
EN
MS_SL_CTRL_CNFG - Master Slave
MS_SL_C
Control
TRL
PROTECTION_CNFG - Register ProPROTECTION_DATA[7:0]
tection Mode Configuration
MPU_SEL_CNFG - Microprocessor
MPU_SEL_CNFG[2:0]
Interface Mode Configuration
Interrupt Registers
INTERRUPT_CNFG - Interrupt ConfigHZ_EN
INT_POL
uration
INTERRUPTS1_STS - Interrupt Status
IN[4:1]
1
T0_OPER T0_MAIN_
INTERRUPTS2_STS - Interrupt Status
IN5
ATING_MO REF_FAIL
2
DE
ED
INTERRUPTS3_STS - Interrupt Status EX_SYNC
INPUT_TO
T4_STS
3
_ALARM
_T4
INTERRUPTS1_ENABLE_CNFG
IN[4:1]
Interrupt Control 1
T0_OPER T0_MAIN_
INTERRUPTS2_ENABLE_CNFG
ATING_MO REF_FAIL
IN5
Interrupt Control 2
DE
ED
INTERRUPTS3_ENABLE_CNFG
- EX_SYNC
INPUT_TO
T4_STS
Interrupt Control 3
_ALARM
_T4
Input Clock Frequency & Priority Configuration Registers
IN1_CNFG - Input Clock 1 Configura- DIRECT_D
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
tion
IV
IN2_CNFG - Input Clock 2 Configura- DIRECT_D
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
tion
IV
IN3_IN4_HF_DIV_CNFG - Input Clock
3 & 4 High Frequency Divider ConfiguIN4_DIV[1:0]
IN3_DIV[1:0]
ration
IN3_CNFG - Input Clock 3 Configura- DIRECT_D
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
tion
IV
IN4_CNFG - Input Clock 4 Configura- DIRECT_D
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
tion
IV
IN5_CNFG - Input Clock 5 Configura- DIRECT_D
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
tion
IV
PRE_DIV_CH_CNFG - DivN Divider
PRE_DIV_CH_VALUE[3:0]
Channel Selection
PRE_DIVN[7:0]_CNFG - DivN Divider
PRE_DIVN_VALUE[7:0]
Division Factor Configuration 1
PRE_DIVN[14:8]_CNFG
DivN
PRE_DIVN_VALUE[14:8]
Divider Division Factor Configuration 2
IN1_IN2_SEL_PRIORITY_CNFG
Input Clock 1 & 2 Priority Configuration
IN2_SEL_PRIORITY[3:0]
IN1_SEL_PRIORITY[3:0]
*
Programming Information
57
Reference
Page
P 67
P 68
P 68
P 69
P 70
P 70
P 71
P 72
P 72
P 73
P 73
P 74
P 75
P 76
P 77
P 78
P 79
P 80
P 80
P 81
P 82
December 9, 2008
IDT82V3285
WAN PLL
Table 41: Register List and Map (Continued)
Address
(Hex)
28
2B
2E
2F
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IN3_IN4_SEL_PRIORITY_CNFG
Input Clock 3 & 4 Priority Configuration
IN4_SEL_PRIORITY[3:0]
IN3_SEL_PRIORITY[3:0]
*
IN5_SEL_PRIORITY_CNFG - Input
IN5_SEL_PRIORITY[3:0]
Clock 5 Priority Configuration *
Input Clock Quality Monitoring Configuration & Status Registers
FREQ_MON_FACTOR_CNFG - FacFREQ_MON_FACTOR[3:0]
tor of Frequency Monitor Configuration
ALL_FREQ_MON_THRESHOLD_CN
FG - Frequency Monitor Threshold for
ALL_FREQ_HARD_THRESHOLD[3:0]
All Input Clocks Configuration
UPPER_THRESHOLD_0_CNFG
Upper Threshold for Leaky Bucket
UPPER_THRESHOLD_0_DATA[7:0]
Configuration 0
LOWER_THRESHOLD_0_CNFG
Lower Threshold for Leaky Bucket
LOWER_THRESHOLD_0_DATA[7:0]
Configuration 0
BUCKET_SIZE_0_CNFG - Bucket
BUCKET_SIZE_0_DATA[7:0]
Size for Leaky Bucket Configuration 0
DECAY_RATE_0_CNFG - Decay Rate
DECAY_RATE_0_DATA
for Leaky Bucket Configuration 0
[1:0]
UPPER_THRESHOLD_1_CNFG
Upper Threshold for Leaky Bucket
UPPER_THRESHOLD_1_DATA[7:0]
Configuration 1
LOWER_THRESHOLD_1_CNFG
Lower Threshold for Leaky Bucket
LOWER_THRESHOLD_1_DATA[7:0]
Configuration 1
BUCKET_SIZE_1_CNFG - Bucket
BUCKET_SIZE_1_DATA[7:0]
Size for Leaky Bucket Configuration 1
DECAY_RATE_1_CNFG - Decay Rate
DECAY_RATE_1_DATA
for Leaky Bucket Configuration 1
[1:0]
UPPER_THRESHOLD_2_CNFG
Upper Threshold for Leaky Bucket
UPPER_THRESHOLD_2_DATA[7:0]
Configuration 2
LOWER_THRESHOLD_2_CNFG
Lower Threshold for Leaky Bucket
LOWER_THRESHOLD_2_DATA[7:0]
Configuration 2
BUCKET_SIZE_2_CNFG - Bucket
BUCKET_SIZE_2_DATA[7:0]
Size for Leaky Bucket Configuration 2
DECAY_RATE_2_CNFG - Decay Rate
DECAY_RATE_2_DATA
for Leaky Bucket Configuration 2
[1:0]
UPPER_THRESHOLD_3_CNFG
Upper Threshold for Leaky Bucket
UPPER_THRESHOLD_3_DATA[7:0]
Configuration 3
LOWER_THRESHOLD_3_CNFG
Lower Threshold for Leaky Bucket
LOWER_THRESHOLD_3_DATA[7:0]
Configuration 3
BUCKET_SIZE_3_CNFG - Bucket
BUCKET_SIZE_3_DATA[7:0]
Size for Leaky Bucket Configuration 3
DECAY_RATE_3_CNFG - Decay Rate
DECAY_RATE_3_DATA
for Leaky Bucket Configuration 3
[1:0]
Programming Information
58
Reference
Page
P 83
P 84
P 85
P 85
P 86
P 86
P 86
P 87
P 87
P 87
P 88
P 88
P 88
P 89
P 89
P 89
P 90
P 90
P 90
P 91
December 9, 2008
IDT82V3285
WAN PLL
Table 41: Register List and Map (Continued)
Address
(Hex)
41
42
Register Name
IN_FREQ_READ_CH_CNFG - Input
Clock Frequency Read Channel
Selection
IN_FREQ_READ_STS - Input Clock
Frequency Read Value
Bit 7
Bit 6
Bit 5
Bit 4
-
-
-
-
IN1_IN2_STS - Input Clock 1 & 2 Status
-
45
IN3_IN4_STS - Input Clock 3 & 4 Status
-
48
IN5_STS - Input Clock 5 Status
-
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
Bit 2
Bit 1
Bit 0
IN_FREQ_READ_CH[3:0]
IN2_FREQ
_HARD_A
LARM
IN4_FREQ
_HARD_A
LARM
IN2_NO_A
CTIVITY_A
LARM
IN4_NO_A
CTIVITY_A
LARM
IN2_PH_L
OCK_ALA
RM
IN4_PH_L
OCK_ALA
RM
-
-
-
-
-
-
P 92
IN1_FREQ
_HARD_A
LARM
IN3_FREQ
_HARD_A
LARM
IN5_FREQ
_HARD_A
LARM
IN1_NO_A
CTIVITY_A
LARM
IN3_NO_A
CTIVITY_A
LARM
IN5_NO_A
CTIVITY_A
LARM
IN1_PH_L
OCK_ALA
RM
IN3_PH_L
OCK_ALA
RM
IN5_PH_L
OCK_ALA
RM
T0 / T4 DPLL Input Clock Selection Registers
INPUT_VALID1_STS - Input Clocks
IN[4:1]
Validity 1
INPUT_VALID2_STS - Input Clocks
IN5
Validity 2
REMOTE_INPUT_VALID1_CNFG -D
IN4_VALID IN3_VALID IN2_VALID IN1_VALID
Input Clocks Validity Configuration 1
REMOTE_INPUT_VALID2_CNFG IN5_VALID
Input Clocks Validity Configuration 2
PRIORITY_TABLE1_STS - Priority
HIGHEST_PRIORITY_VALIDATED[3:0]
CURRENTLY_SELECTED_INPUT[3:0]
Status 1 *
PRIORITY_TABLE2_STS - Priority
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0
THIRD_HIGHEST_PRIORITY_VALIDATED[3:0]
Status 2 *
]
T0_INPUT_SEL_CNFG - T0 Selected
T0_INPUT_SEL[3:0]
Input Clock Configuration
T4_LOCK_ T0_FOR_T T4_TEST_
T4_INPUT_SEL_CNFG - T4 Selected
T4_INPUT_SEL[3:0]
T0
4
T0_PH
Input Clock Configuration
T0 / T4 DPLL State Machine Control Registers
EX_SYNC
T0_DPLL_ T4_DPLL_
OPERATING_STS - DPLL Operating
T4_DPLL_
T0_DPLL_
_ALARM_
SOFT_FRE SOFT_FRE
T0_DPLL_OPERATING_MODE[2:0]
Status
LOCK
LOCK
MON
Q_ALARM Q_ALRAM
T0_OPERATING_MODE_CNFG - T0
T0_OPERATING_MODE[2:0]
DPLL Operating Mode Configuration
T4_OPERATING_MODE_CNFG - T4
T4_OPERATING_MODE[2:0]
DPLL Operating Mode Configuration
T0 / T4 DPLL & APLL Configuration Registers
T0_DPLL_APLL_PATH_CNFG - T0
T0_GSM_OBSAI_16E1 T0_12E1_24T1_E3_T3
T0_APLL_PATH[3:0]
DPLL & APLL Path Configuration
_16T1_SEL[1:0]
_SEL[1:0]
T0_DPLL_START_BW_DAMPING_C
NFG - T0 DPLL Start Bandwidth & T0_DPLL_START_DAMPING[2:0]
T0_DPLL_START_BW[4:0]
Damping Factor Configuration
T0_DPLL_ACQ_BW_DAMPING_CNF
G - T0 DPLL Acquisition Bandwidth & T0_DPLL_ACQ_DAMPING[2:0]
T0_DPLL_ACQ_BW[4:0]
Damping Factor Configuration
Programming Information
59
Reference
Page
P 91
IN_FREQ_VALUE[7:0]
44
4A
Bit 3
P 93
P 94
P 95
P 96
P 96
P 96
P 97
P 97
P 98
P 99
P 100
P 101
P 102
P 102
P 103
P 104
P 105
December 9, 2008
IDT82V3285
WAN PLL
Table 41: Register List and Map (Continued)
Address
(Hex)
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
Register Name
T0_DPLL_LOCKED_BW_DAMPING_
CNFG - T0 DPLL Locked Bandwidth &
Damping Factor Configuration
T0_BW_OVERSHOOT_CNFG - T0
DPLL Bandwidth Overshoot Configuration
PHASE_LOSS_COARSE_LIMIT_CNF
G - Phase Loss Coarse Detector Limit
Configuration *
PHASE_LOSS_FINE_LIMIT_CNFG Phase Loss Fine Detector Limit Configuration *
T0_HOLDOVER_MODE_CNFG - T0
DPLL Holdover Mode Configuration
T0_HOLDOVER_FREQ[7:0]_CNFG T0 DPLL Holdover Frequency Configuration 1
T0_HOLDOVER_FREQ[15:8]_CNFG
- T0 DPLL Holdover Frequency Configuration 2
T0_HOLDOVER_FREQ[23:16]_CNFG
- T0 DPLL Holdover Frequency Configuration 3
T4_DPLL_APLL_PATH_CNFG - T4
DPLL & APLL Path Configuration
T4_DPLL_LOCKED_BW_DAMPING_
CNFG - T4 DPLL Locked Bandwidth &
Damping Factor Configuration
CURRENT_DPLL_FREQ[7:0]_STS DPLL Current Frequency Status 1 *
CURRENT_DPLL_FREQ[15:8]_STS DPLL Current Frequency Status 2 *
CURRENT_DPLL_FREQ[23:16]_STS
- DPLL Current Frequency Status 3 *
DPLL_FREQ_SOFT_LIMIT_CNFG DPLL Soft Limit Configuration
DPLL_FREQ_HARD_LIMIT[7:0]_CNF
G - DPLL Hard Limit Configuration 1
DPLL_FREQ_HARD_LIMIT[15:8]_CN
FG - DPLL Hard Limit Configuration 2
CURRENT_DPLL_PHASE[7:0]_STS DPLL Current Phase Status 1 *
CURRENT_DPLL_PHASE[15:8]_STS
- DPLL Current Phase Status 2 *
T0_T4_APLL_BW_CNFG - T0 / T4
APLL Bandwidth Configuration
Bit 7
Bit 6
Bit 5
Bit 4
T0_DPLL_LOCKED_DAMPING[2:0]
AUTO_BW
_SEL
-
-
Bit 3
Bit 2
Bit 1
Bit 0
T0_DPLL_LOCKED_BW[4:0]
-
T0_LIMT
-
-
P 106
-
COARSE_
MULTI_PH
MULTI_PH
PH_LOS_L WIDE_EN
_8K_4K_2
PH_LOS_COARSE_LIMT[3:0]
_APP
IMT_EN
K_EN
FINE_PH_
FAST_LOS
LOS_LIMT
PH_LOS_FINE_LIMT[2:0]
_SW
_EN
MAN_HOL AUTO_AV
READ_AV TEMP_HOLDOVER_M
FAST_AVG
DOVER
G
G
ODE[1:0]
P 108
P 109
P 110
P 110
T0_HOLDOVER_FREQ[15:8]
P 111
T0_HOLDOVER_FREQ[23:16]
P 111
T4_DPLL_LOCKED_DAMPING[2:0]
-
T4_GSM_GPS_16E1_1 T4_12E1_24T1_E3_T3
6T1_SEL[1:0]
_SEL[1:0]
P 112
T4_DPLL_LOCKED_B
W[1:0]
P 113
-
-
CURRENT_DPLL_FREQ[7:0]
P 113
CURRENT_DPLL_FREQ[15:8]
P 113
CURRENT_DPLL_FREQ[23:16]
P 114
FREQ_LIM
T_PH_LOS
DPLL_FREQ_SOFT_LIMT[6:0]
-
P 107
T0_HOLDOVER_FREQ[7:0]
T4_APLL_PATH[3:0]
-
Reference
Page
P 114
DPLL_FREQ_HARD_LIMT[7:0]
P 114
DPLL_FREQ_HARD_LIMT[15:8]
P 115
CURRENT_PH_DATA[7:0]
P 115
CURRENT_PH_DATA[15:8]
P 115
T0_APLL_BW[1:0]
-
-
T4_APLL_BW[1:0]
P 116
Output Configuration Registers
6D
OUT1_FREQ_CNFG - Output Clock 1
Frequency Configuration
Programming Information
OUT1_PATH_SEL[3:0]
60
OUT1_DIVIDER[3:0]
P 117
December 9, 2008
IDT82V3285
WAN PLL
Table 41: Register List and Map (Continued)
Address
(Hex)
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Reference
Page
Bit 0
OUT2_FREQ_CNFG - Output Clock 2
OUT2_PATH_SEL[3:0]
OUT2_DIVIDER[3:0]
Frequency Configuration
OUT3_FREQ_CNFG - Output Clock 3
OUT3_PATH_SEL[3:0]
OUT3_DIVIDER[3:0]
Frequency Configuration
OUT4_FREQ_CNFG - Output Clock 4
OUT4_PATH_SEL[3:0]
OUT4_DIVIDER[3:0]
Frequency Configuration
OUT5_FREQ_CNFG - Output Clock 5
OUT5_PATH_SEL[3:0]
OUT5_DIVIDER[3:0]
Frequency Configuration
OUTPUT_INV2 - Output Clock 4 & 5
OUT5_INV OUT4_INV
Invert Configuration
OUTPUT_INV1 - Output Clock 1 ~ 3
OUT3_INV OUT2_INV OUT1_INV
Invert Configuration
FR_MFR_SYNC_CNFG - Frame Sync
2K_8K_PU
IN_2K_4K_
& Multiframe Sync Output Configura8K_EN
2K_EN
L_POSITI 8K_INV
8K_PUL
2K_INV
2K_PUL
8K_INV
tion
ON
PBO & Phase Offset Control Registers
PHASE_MON_PBO_CNFG - Phase
IN_NOISE
PH_MON_ PH_MON_
Transient Monitor & PBO ConfiguraPH_TR_MON_LIMT[3:0]
_WINDOW
EN
PBO_EN
tion
PHASE_OFFSET[7:0]_CNFG - Phase
PH_OFFSET[7:0]
Offset Configuration 1
PHASE_OFFSET[9:8]_CNFG - Phase PH_OFFS
PH_OFFSET[9:8]
Offset Configuration 2
ET_EN
Synchronization Configuration Registers
SYNC_MONITOR_CNFG - Sync MonSYNC_MON_LIMT[2:0]
itor Configuration
SYNC_PHASE_CNFG - Sync Phase
SYNC_PH1[1:0]
Configuration
6E
6F
70
71
72
73
74
78
7A
7B
7C
7D
7.2
REGISTER DESCRIPTION
7.2.1
GLOBAL CONTROL REGISTERS
P 118
P 119
P 120
P 121
P 121
P 122
P 123
P 124
P 124
P 125
P 126
P 126
ID[7:0] - Device ID 1
Address: 00H
Type: Read
Default Value: 10001000
7
6
5
4
3
2
1
0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Bit
Name
7-0
ID[7:0]
Programming Information
Description
Refer to the description of the ID[15:8] bits (b7~0, 01H).
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ID[15:8] - Device ID 2
Address: 01H
Type: Read
Default Value: 00010001
7
6
5
4
3
2
1
0
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
Bit
Name
Description
7-0
ID[15:8]
The value in the ID[15:0] bits are pre-set, representing the identification number for the IDT82V3285.
MPU_PIN_STS - MPU_MODE[2:0] Pins Status
Address: 02H
Type: Read
Default Value: XXXXXXXX
7
6
5
4
3
2
1
0
-
-
-
-
-
MPU_PIN_STS2
MPU_PIN_STS1
MPU_PIN_STS0
Bit
Name
7-3
-
Description
Reserved.
These bits indicate the value of the MPU_MODE[2:0] pins.
MPU_PIN_STS[2:0]
The default value of these bits is determined by the MPU_MODE[2:0] pins during reset.
2-0
NOMINAL_FREQ[7:0]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 1
Address: 04H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
NOMINAL_FRE
Q_VALUE7
NOMINAL_FRE
Q_VALUE6
NOMINAL_FRE
Q_VALUE5
NOMINAL_FRE
Q_VALUE4
NOMINAL_FRE
Q_VALUE3
NOMINAL_FRE
Q_VALUE2
NOMINAL_FRE
Q_VALUE1
NOMINAL_FRE
Q_VALUE0
Bit
7-0
Name
Description
NOMINAL_FREQ_VALUE[7:0] Refer to the description of the NOMINAL_FREQ_VALUE[23:16] bits (b7~0, 06H).
NOMINAL_FREQ[15:8]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 2
Address: 05H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
NOMINAL_FRE
Q_VALUE15
NOMINAL_FRE
Q_VALUE14
NOMINAL_FRE
Q_VALUE13
NOMINAL_FRE
Q_VALUE12
NOMINAL_FRE
Q_VALUE11
NOMINAL_FRE
Q_VALUE10
NOMINAL_FRE
Q_VALUE9
NOMINAL_FRE
Q_VALUE8
Bit
7-0
Name
Description
NOMINAL_FREQ_VALUE[15:8] Refer to the description of the NOMINAL_FREQ_VALUE[23:16] bits (b7~0, 06H).
Programming Information
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WAN PLL
NOMINAL_FREQ[23:16]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 3
Address: 06H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
NOMINAL_FRE
Q_VALUE23
NOMINAL_FRE
Q_VALUE22
NOMINAL_FRE
Q_VALUE21
NOMINAL_FRE
Q_VALUE20
NOMINAL_FRE
Q_VALUE19
NOMINAL_FRE
Q_VALUE18
NOMINAL_FRE
Q_VALUE17
NOMINAL_FRE
Q_VALUE16
Bit
7-0
Name
Description
The NOMINAL_FREQ_VALUE[23:0] bits represent a 2’s complement signed integer. If the value is multiplied by
0.0000884, the calibration value for the master clock in ppm will be gotten.
For example, the frequency offset on OSCI is +3 ppm. Though -3 ppm should be compensated, the calibration value is
NOMINAL_FREQ_VALUE[23:16] calculated as +3 ppm:
3 ÷ 0.0000884 = 33937 (Dec.) = 8490 (Hex);
So ‘008490’ should be written into these bits.
The calibration range is within ±741 ppm.
T4_T0_REG_SEL_CNFG - T0 / T4 Registers Selection Configuration
Address: 07H
Type: Read / Write
Default Value: XXX0XXXX
7
6
5
4
3
2
1
0
-
-
-
T4_T0_SEL
-
-
-
-
Bit
Name
Description
7-5
-
4
T4_T0_SEL
3-0
-
Reserved.
A part of the registers are shared by T0 and T4 paths. These registers are addressed 27H, 28H, 2BH, 4EH, 4FH, 5AH, 5BH, 62H
~ 64H, 68H and 69H. This bit determines whether the register configuration is available for T0 or T4 path.
0: T0 path (default).
1: T4 path.
Reserved.
Programming Information
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WAN PLL
PHASE_ALARM_TIME_OUT_CNFG - Phase Lock Alarm Time-Out Configuration
Address: 08H
Type: Read / Write
Default Value: 00110010
7
6
5
4
3
2
1
0
MULTI_FACTO
R1
MULTI_FACTO
R0
TIME_OUT_VA
LUE5
TIME_OUT_VA
LUE4
TIME_OUT_VA
LUE3
TIME_OUT_VA
LUE2
TIME_OUT_VA
LUE1
TIME_OUT_VAL
UE0
Bit
7-6
5-0
Name
Description
These bits determine a factor which has a relationship with a period in seconds. A phase lock alarm will be raised if the T0
selected input clock is not locked in T0 DPLL within this period. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the
phase lock alarm will be cleared after this period (starting from when the alarm is raised). Refer to the description of the
TIME_OUT_VALUE[5:0] bits (b5~0, 08H).
MULTI_FACTOR[1:0]
00: 2 (default)
01: 4
10: 8
11: 16
These bits represent an unsigned integer. If the value in these bits is multiplied by the value in the MULTI_FACTOR[1:0]
bits (b7~6, 08H), a period in seconds will be gotten.
TIME_OUT_VALUE[5:0] A phase lock alarm will be raised if the T0 selected input clock is not locked in T0 DPLL within this period. If the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the phase lock alarm will be cleared after this period (starting from when the
alarm is raised).
Programming Information
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IDT82V3285
WAN PLL
INPUT_MODE_CNFG - Input Mode Configuration
Address: 09H
Type: Read / Write
Default Value: 10100XX0
7
6
5
4
3
2
1
0
AUTO_EXT_SY
NC_EN
EXT_SYNC_EN
PH_ALARM_TI
MEOUT
SYNC_FREQ1
SYNC_FREQ0
IN_SONET_SD
H
MASTER_SLAV
E
REVERTIVE_M
ODE
Bit
7
6
5
4-3
2
1
0
Name
Description
AUTO_EXT_SYNC_EN Refer to the description of the EXT_SYNC_EN bit (b6, 09H).
This bit, together with the AUTO_EXT_SYNC_EN bit (b7, 09H), determines whether EX_SYNC1 is enabled to synchronize
the frame sync output signals.
EXT_SYNC_EN
AUTO_EXT_SYNC_EN
EXT_SYNC_EN
Synchronization
don’t-care
0
1
0
1
1
Disabled (default)
Enabled
Enabled if the T0 selected input clock is IN5; otherwise, disabled.
This bit determines how to clear the phase lock alarm.
0: The phase lock alarm will be cleared when a ‘1’ is written to the corresponding INn_PH_LOCK_ALARM bit (b4/0, 44H &
PH_ALARM_TIMEOUT 45H & 48H).
1: The phase lock alarm will be cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0]
(b7~6, 08H) in seconds) which starts from when the alarm is raised. (default)
These bits set the frequency of the frame sync signal input on the EX_SYNC1 pin.
00: 8 kHz (default)
SYNC_FREQ[1:0] 01: 8 kHz.
10: 4 kHz.
11: 2 kHz.
This bit selects the SDH or SONET network type.
0: SDH. The DPLL required clock is 2.048 MHz when the IN_FREQ[3:0] bits (b3~0, 16H & 17H & 19H) are ‘0001’; the T0/T4
DPLL output from the 16E1/16T1 path is 16E1.
IN_SONET_SDH
1: SONET. The DPLL required clock is 1.544 MHz when the IN_FREQ[3:0] bits (b3~0, 16H & 17H & 19H) are ‘0001’; the T0/
T4 DPLL output from the 16E1/16T1 path is 16T1.
The default value of this bit is determined by the SONET/SDH pin during reset.
This bit is read only. It indicates the value of the MS/SL pin.
MASTER_SLAVE
Its default value is determined by the MS/SL pin during reset.
This bit selects Revertive or Non-Revertive switch for T0 path.
REVERTIVE_MODE 0: Non-Revertive switch. (default)
1: Revertive switch.
Programming Information
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IDT82V3285
WAN PLL
DIFFERENTIAL_IN_OUT_OSCI_CNFG - Differential Input / Output Port & Master Clock Configuration
Address: 0AH
Type: Read / Write
Default Value: XXXXX001
7
6
5
4
3
2
1
0
-
-
-
-
-
OSC_EDGE
OUT5_PECL_LVDS
OUT4_PECL_LVDS
Bit
Name
7-3
-
2
1
0
Description
Reserved.
This bit selects a better active edge of the master clock.
OSC_EDGE
0: The rising edge. (default)
1: The falling edge.
This bit selects a port technology for OUT5.
OUT5_PECL_LVDS 0: LVDS. (default)
1: PECL.
This bit selects a port technology for OUT4.
OUT4_PECL_LVDS 0: LVDS.
1: PECL. (default)
Programming Information
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IDT82V3285
WAN PLL
MON_SW_PBO_CNFG - Frequency Monitor, Input Clock Selection & PBO Control
Address: 0BH
Type: Read / Write
Default Value: 100X01X1
7
6
5
4
3
2
1
0
FREQ_MON_C
LK
LOS_FLAG_TO
_TDO
ULTR_FAST_SW
EXT_SW
PBO_FREZ
PBO_EN
-
FREQ_MON_H
ARD_EN
Bit
7
6
5
4
3
2
1
0
Name
Description
The bit selects a reference clock for input clock frequency monitoring.
0: The output of T0 DPLL.
1: The master clock. (default)
The bit determines whether the interrupt of T0 selected input clock fail - is reported by the TDO pin.
0: Not reported. TDO pin is used as JTAG test data output which complies with IEEE 1149.1. (default)
LOS_FLAG_TO_TDO
1: Reported. TDO pin mimics the state of the T0_MAIN_REF_FAILED bit (b6, 0EH) and does not strictly comply with IEEE
1149.1.
This bit determines whether the T0 selected input clock is valid when missing 2 consecutive clock cycles or more.
ULTR_FAST_SW
0: Valid. (default)
1: Invalid.
This bit determines the T0 input clock selection.
0: Forced selection or Automatic selection, as controlled by the T0_INPUT_SEL[3:0] bits (b3~0, 50H).
EXT_SW
1: External Fast selection.
The default value of this bit is determined by the FF_SRCSW pin during reset.
This bit is valid only when the PBO is enabled by the PBO_EN bit (b2, 0BH). It determines whether PBO is frozen at the current phase offset when a PBO event is triggered.
PBO_FREZ
0: Not frozen. (default)
1: Frozen. Further PBO events are ignored and the current phase offset is maintained.
This bit determines whether PBO is enabled when the T0 selected input clock switch or the T0 DPLL exiting from Holdover
mode or Free-Run mode occurs.
PBO_EN
0: Disabled.
1: Enabled. (default)
Reserved.
This bit determines whether the frequency hard alarm is enabled when the frequency of the input clock with respect to the
reference clock is above the frequency hard alarm threshold. The reference clock can be the output of T0 DPLL or the masFREQ_MON_HARD_EN ter clock, as determined by the FREQ_MON_CLK bit (b7, 0BH).
0: Disabled.
1: Enabled. (default)
FREQ_MON_CLK
Programming Information
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WAN PLL
MS_SL_CTRL_CNFG - Master Slave Control
Address: 13H
Type: Read / Write
Default Value: XXXXXXX0
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
MS_SL_CTRL
Bit
Name
7-1
-
Description
Reserved.
This bit, together with the MS/SL pin, controls whether the device is configured as the Master or as the Slave.
Master/Slave Control
MS/SL pin
0
MS_SL_CTRL
Result
MS_SL_CTRL Bit
0
1
0
1
High
Low
Master
Slave
Slave
Master
The default value of this bit is ‘0’.
PROTECTION_CNFG - Register Protection Mode Configuration
Address: 7EH
Type: Read / Write
Default Value: 10000101
7
6
5
4
3
2
1
0
PROTECTION_
DATA7
PROTECTION_
DATA6
PROTECTION_
DATA5
PROTECTION_
DATA4
PROTECTION_
DATA3
PROTECTION_
DATA2
PROTECTION_
DATA1
PROTECTION_
DATA0
Bit
7-0
Name
Description
These bits select a register write protection mode.
00000000 - 10000100, 10000111 - 11111111: Protected mode. No other registers can be written except this register.
PROTECTION_DATA[7:0] 10000101: Fully Unprotected mode. All the writable registers can be written. (default)
10000110: Single Unprotected mode. One more register can be written besides this register. After write operation (not
including writing a ‘1’ to clear the bit to ‘0’), the device automatically switches to Protected mode.
Programming Information
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WAN PLL
MPU_SEL_CNFG - Microprocessor Interface Mode Configuration
Address: 7FH
Type: Read / Write
Default Value: XXXXXXXX
7
6
5
4
3
2
1
0
-
-
-
-
-
MPU_SEL_CNFG2
MPU_SEL_CNFG1
MPU_SEL_CNFG0
Bit
Name
7-3
-
2-0
Description
Reserved.
These bits select a microprocessor interface mode:
000: Reserved.
001: ERPOM mode.
010: Multiplexed mode.
MPU_SEL_CNFG[2:0] 011: Intel mode.
100: Motorola mode.
101: Serial mode.
110, 111: Reserved.
The default value of these bits are determined by the MPU_MODE[2:0] pins during reset.
Programming Information
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December 9, 2008
IDT82V3285
7.2.2
WAN PLL
INTERRUPT REGISTERS
INTERRUPT_CNFG - Interrupt Configuration
Address: 0CH
Type: Read / Write
Default Value: XXXXXX10
7
6
5
4
3
2
1
0
-
-
-
-
-
-
HZ_EN
INT_POL
Bit
Name
Description
7-2
-
1
HZ_EN
0
INT_POL
Reserved.
This bit determines the output characteristics of the INT_REQ pin.
0: The output on the INT_REQ pin is high/low when the interrupt is active; the output is the opposite when the interrupt is inactive.
1: The output on the INT_REQ pin is high/low when the interrupt is active; the output is in high impedance state when the interrupt
is inactive. (default)
This bit determines the active level on the INT_REQ pin for an active interrupt indication.
0: Active low. (default)
1: Active high.
INTERRUPTS1_STS - Interrupt Status 1
Address: 0DH
Type: Read / Write
Default Value: 11111111
7
6
5
4
3
2
1
0
-
-
IN4
IN3
IN2
IN1
-
-
Bit
Name
Description
7-6
-
5-2
INn
1-0
-
Reserved.
This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for the corresponding INn; i.e., whether
there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding INn bit (b5~2, 4AH). Here n is any one of 4 to 1.
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
Reserved.
Programming Information
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WAN PLL
INTERRUPTS2_STS - Interrupt Status 2
Address: 0EH
Type: Read / Write
Default Value: 00111111
7
6
5
4
3
2
1
0
T0_OPERATING
_MODE
T0_MAIN_REF_F
AILED
-
-
-
IN5
-
-
Bit
7
6
5-3
2
1-0
Name
Description
This bit indicates the operating mode switch for T0 DPLL; i.e., whether the value in the
T0_DPLL_OPERATING_MODE[2:0] bits (b2~0, 52H) changes.
T0_OPERATING_MODE 0: Has not switched. (default)
1: Has switched.
This bit is cleared by writing a ‘1’.
This bit indicates whether the T0 selected input clock has failed. The T0 selected input clock fails when its validity
changes from ‘valid’ to ‘invalid’; i.e., when there is a transition from ‘1’ to ‘0’ on the corresponding INn bit (4AH, 4BH).
T0_MAIN_REF_FAILED 0: Has not failed. (default)
1: Has failed.
This bit is cleared by writing a ‘1’.
Reserved.
This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for IN5 for T0 path, i.e., whether
there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on IN5 bit (b2, 4BH).
IN5
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
Reserved.
Programming Information
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IDT82V3285
WAN PLL
INTERRUPTS3_STS - Interrupt Status 3
Address: 0FH
Type: Read / Write
Default Value: 11X10000
7
6
5
4
3
2
1
0
EX_SYNC_ALARM
T4_STS
-
INPUT_TO_T4
-
-
-
-
Bit
Name
Description
This bit indicates whether an external sync alarm is raised; i.e., whether there is a transition from ‘0’ to ‘1’ on the
EX_SYNC_ALARM_MON bit (b7, 52H).
EX_SYNC_ALARM 0: Not raised.
1: Raised. (default)
This bit is cleared by writing a ‘1’.
This bit indicates the T4 DPLL locking status changes (from ‘locked’ to ‘unlocked’ or from ‘unlocked’ to ‘locked’); i.e., whether
there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the T4_DPLL_LOCK bit (b6, 52H).
T4_STS
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
Reserved.
This bit indicates whether all the input clocks for T4 path change to be unqualified; i.e., whether the
HIGHEST_PRIORITY_VALIDATED[3:0] bits (b7~4, 4EH) are set to ‘0000’ when these bits are available for T4 path.
INPUT_TO_T4 0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
Reserved.
7
6
5
4
3-0
INTERRUPTS1_ENABLE_CNFG - Interrupt Control 1
Address: 10H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
-
-
IN4
IN3
IN2
IN1
-
-
Bit
Name
Description
7-6
-
5-2
INn
0 -1
-
Reserved.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (from
‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding INn bit (b5~2, 0DH) is ‘1’. Here n is any one of 4 to 1.
0: Disabled. (default)
1: Enabled.
Reserved
Programming Information
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WAN PLL
INTERRUPTS2_ENABLE_CNFG - Interrupt Control 2
Address: 11H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
T0_OPERATING
_MODE
T0_MAIN_REF_F
AILED
-
-
-
IN5
-
-
Bit
Name
Description
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 DPLL operating mode
switches, i.e., when the T0_OPERATING_MODE bit (b7, 0EH) is ‘1’.
T0_OPERATING_MODE
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 selected input clock
has failed; i.e., when the T0_MAIN_REF_FAILED bit (b6, 0EH) is ‘1’.
T0_MAIN_REF_FAILED
0: Disabled. (default)
1: Enabled.
Reserved.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity
changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when IN5 bit (b2, 0EH) is ‘1’.
IN5
0: Disabled. (default)
1: Enabled.
Reserved.
7
6
5-3
2
1-0
INTERRUPTS3_ENABLE_CNFG - Interrupt Control 3
Address: 12H
Type: Read / Write
Default Value: 00X00000
7
6
5
4
3
2
1
0
EX_SYNC_ALARM
T4_STS
-
INPUT_TO_T4
-
-
-
-
Bit
7
6
5
4
3-0
Name
Description
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when an external sync alarm has
occurred, i.e., when the EX_SYNC_ALARM bit (b7, 0FH) is ‘1’.
EX_SYNC_ALARM
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T4 DPLL locking status
changes (from ‘locked’ to ‘unlocked’ or from ‘unlocked’ to ‘locked’), i.e., when the T4_STS bit (b6, 0FH) is ‘1’.
T4_STS
0: Disabled. (default)
1: Enabled.
Reserved.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when all the input clocks for T4 path
become unqualified, i.e., when the INPUT_TO_T4 bit (b4, 0FH) is ‘1’.
INPUT_TO_T4
0: Disabled. (default)
1: Enabled.
Reserved.
Programming Information
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December 9, 2008
IDT82V3285
7.2.3
WAN PLL
INPUT CLOCK FREQUENCY & PRIORITY CONFIGURATION REGISTERS
IN1_CNFG - Input Clock 1 Configuration
Address: 16H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
DIRECT_DIV
LOCK_8K
BUCKET_SEL1
BUCKET_SEL0
IN_FREQ3
IN_FREQ2
IN_FREQ1
IN_FREQ0
Bit
Name
Description
7
DIRECT_DIV
Refer to the description of the LOCK_8K bit (b6, 16H).
This bit, together with the DIRECT_DIV bit (b7, 16H), determines whether the DivN Divider or the Lock 8k Divider is used for
IN1:
6
5-4
3-0
LOCK_8K
DIRECT_DIV bit
LOCK_8K bit
Used Divider
0
0
1
1
0
1
0
1
Both bypassed (default)
Lock 8k Divider
DivN Divider
Reserved
These bits select one of the four groups of leaky bucket configuration registers for IN1:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN1:
0000: 8 kHz. (default)
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.44 MHz.
0100: 25.92 MHz.
IN_FREQ[3:0]
0101: 38.88 MHz.
0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
For IN1, the required frequency should not be set higher than that of the input clock.
Programming Information
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December 9, 2008
IDT82V3285
WAN PLL
IN2_CNFG - Input Clock 2 Configuration
Address: 17H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
DIRECT_DIV
LOCK_8K
BUCKET_SEL1
BUCKET_SEL0
IN_FREQ3
IN_FREQ2
IN_FREQ1
IN_FREQ0
Bit
Name
Description
7
DIRECT_DIV
Refer to the description of the LOCK_8K bit (b6, 17H).
This bit, together with the DIRECT_DIV bit (b7, 17H), determines whether the DivN Divider or the Lock 8k Divider is used for
IN2:
6
5-4
3-0
LOCK_8K
DIRECT_DIV bit
LOCK_8K bit
Used Divider
0
0
1
1
0
1
0
1
Both bypassed (default)
Lock 8k Divider
DivN Divider
Reserved
These bits select one of the four groups of leaky bucket configuration registers for IN2:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN2
0000: 8 kHz. (default)
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.44 MHz.
0100: 25.92 MHz.
IN_FREQ[3:0]
0101: 38.88 MHz.
0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
For the IN2, the required frequency should not be set higher than that of the input clock.
Programming Information
75
December 9, 2008
IDT82V3285
WAN PLL
IN3_IN4_HF_DIV_CNFG - Input Clock 3 & 4 High Frequency Divider Configuration
Address: 18H
Type: Read / Write
Default Value: 00XXXX00
7
6
5
4
3
2
1
0
IN4_DIV1
IN4_DIV0
-
-
-
-
IN3_DIV1
IN3_DIV0
Bit
Name
7-6
IN4_DIV[1:0]
5-2
-
1-0
IN3_DIV[1:0]
Programming Information
Description
These bits determine whether the HF Divider is used and what the division factor is for IN4 frequency division:
00: Bypassed. (default)
01: Divided by 4.
10: Divided by 5.
11: Reserved.
Reserved.
These bits determine whether the HF Divider is used and what the division factor is for IN3 frequency division:
00: Bypassed. (default)
01: Divided by 4.
10: Divided by 5.
11: Reserved.
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December 9, 2008
IDT82V3285
WAN PLL
IN3_CNFG - Input Clock 3 Configuration
Address: 19H
Type: Read / Write
Default Value: 00000011
7
6
5
4
3
2
1
0
DIRECT_DIV
LOCK_8K
BUCKET_SEL1
BUCKET_SEL0
IN_FREQ3
IN_FREQ2
IN_FREQ1
IN_FREQ0
Bit
Name
Description
7
DIRECT_DIV
Refer to the description of the LOCK_8K bit (b6, 19H).
This bit, together with the DIRECT_DIV bit (b7, 19H), determines whether the DivN Divider or the Lock 8k Divider is used for
IN3:
6
5-4
3-0
LOCK_8K
DIRECT_DIV bit
LOCK_8K bit
Used Divider
0
0
1
1
0
1
0
1
Both bypassed (default)
Lock 8k Divider
DivN Divider
Reserved
These bits select one of the four groups of leaky bucket configuration registers for IN3:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN3:
0000: 8 kHz.
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.44 MHz. (default)
0100: 25.92 MHz.
IN_FREQ[3:0]
0101: 38.88 MHz.
0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
The required frequency should not be set higher than that of the input clock.
Programming Information
77
December 9, 2008
IDT82V3285
WAN PLL
IN4_CNFG - Input Clock 4 Configuration
Address: 1AH
Type: Read / Write
Default Value: 00000011
7
6
5
4
3
2
1
0
DIRECT_DIV
LOCK_8K
BUCKET_SEL1
BUCKET_SEL0
IN_FREQ3
IN_FREQ2
IN_FREQ1
IN_FREQ0
Bit
Name
Description
7
DIRECT_DIV
Refer to the description of the LOCK_8K bit (b6, 1AH).
This bit, together with the DIRECT_DIV bit (b7, 1AH), determines whether the DivN Divider or the Lock 8k Divider is used for
IN4:
6
5-4
3-0
LOCK_8K
DIRECT_DIV bit
LOCK_8K bit
Used Divider
0
0
1
1
0
1
0
1
Both bypassed (default)
Lock 8k Divider
DivN Divider
Reserved
These bits select one of the four groups of leaky bucket configuration registers for IN4
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN4:
0000: 8 kHz.
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.44 MHz. (default)
0100: 25.92 MHz.
IN_FREQ[3:0]
0101: 38.88 MHz.
0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
For IN4, the required frequency should not be set higher than that of the input clock.
Programming Information
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December 9, 2008
IDT82V3285
WAN PLL
IN5_CNFG - Input Clock 5 Configuration
Address: 1FH
Type: Read / Write
Default Value: 0000XXXX
7
6
5
4
3
2
1
0
DIRECT_DIV
LOCK_8K
BUCKET_SEL1
BUCKET_SEL0
IN_FREQ3
IN_FREQ2
IN_FREQ1
IN_FREQ0
Bit
Name
Description
7
DIRECT_DIV
Refer to the description of the LOCK_8K bit (b6, 1FH).
This bit, together with the DIRECT_DIV bit (b7, 1FH), determines whether the DivN Divider or the Lock 8k Divider is used for
IN5:
6
5-4
3-0
LOCK_8K
DIRECT_DIV bit
LOCK_8K bit
Used Divider
0
0
1
1
0
1
0
1
Both bypassed (default)
Lock 8k Divider
DivN Divider
Reserved
These bits select one of the four groups of leaky bucket configuration registers for IN5:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN5:
0000: 8 kHz.
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.44 MHz.
0100: 25.92 MHz.
0101: 38.88 MHz.
IN_FREQ[3:0] 0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
For IN5, the required frequency should not be set higher than that of the input clock.
The default value of these bits depends on the device application as follows:
In Master / Slave application, when the device is configured as the Master, the default value is ‘0001’; when the device is configured as the Slave, the default value is ‘0010’.
Programming Information
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December 9, 2008
IDT82V3285
WAN PLL
PRE_DIV_CH_CNFG - DivN Divider Channel Selection
Address: 23H
Type: Read / Write
Default Value: XXXX0000
7
6
5
4
3
2
1
0
-
-
-
-
PRE_DIV_CH_VALUE3
PRE_DIV_CH_VALUE2
PRE_DIV_CH_VALUE1
PRE_DIV_CH_VALUE0
Bit
Name
7-4
-
Description
Reserved.
This register is an indirect address register for Register 24H and 25H.
These bits select an input clock. The value set in the PRE_DIVN_VALUE[14:0] bits (25H, 24H) is available for the
selected input clock.
0000: Reserved. (default)
0001, 0010: Reserved.
0011: IN1.
PRE_DIV_CH_VALUE[3:0]
0100: IN2.
0101: IN3
0110: IN4
0111, 1000, 1001, 1010: Reserved
1011: IN5
1100, 1101, 1110, 1111: Reserved.
3-0
PRE_DIVN[7:0]_CNFG - DivN Divider Division Factor Configuration 1
Address: 24H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
PRE_DIVN_VA
LUE7
PRE_DIVN_VA
LUE6
PRE_DIVN_VA
LUE5
PRE_DIVN_VA
LUE4
PRE_DIVN_VA
LUE3
PRE_DIVN_VA
LUE2
PRE_DIVN_VA
LUE1
PRE_DIVN_VA
LUE0
Bit
7-0
Name
Description
PRE_DIVN_VALUE[7:0] Refer to the description of the PRE_DIVN_VALUE[14:8] bits (b6~0, 25H).
Programming Information
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December 9, 2008
IDT82V3285
WAN PLL
PRE_DIVN[14:8]_CNFG - DivN Divider Division Factor Configuration 2
Address: 25H
Type: Read / Write
Default Value: X0000000
7
6
5
4
3
2
1
0
-
PRE_DIVN_VAL
UE14
PRE_DIVN_VAL
UE13
PRE_DIVN_VAL
UE12
PRE_DIVN_VAL
UE11
PRE_DIVN_VAL
UE10
PRE_DIVN_VAL
UE9
PRE_DIVN_VAL
UE8
Bit
Name
Description
7
-
6-0
PRE_DIVN_VALUE[14:8]
Reserved.
The division factor for an input clock is the value in the PRE_DIVN_VALUE[14:0] bits plus 1. The input clock is selected
by the PRE_DIV_CH_VALUE[3:0] bits (b3~0, 23H).
A value from ‘0’ to ‘4BEF’ (Hex) can be written into, corresponding to a division factor from 1 to 19440. The others are
reserved. So the DivN Divider only supports an input clock whose frequency is lower than (