8304AG-02LF

Low Skew, 1-to-4, LVCMOS/LVTTL Fanout Buffer ICS8304-02 DATA SHEET PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 General Description Features The ICS8304-02 is a low skew, high performance, 1-to-4 Fanout Buffer with individual output enables. The ICS8304-02 is characterized at full 3.3V and 2.5V for input (VDD), and mixed 3.3V and 2.5V for output operating supply modes (VDDO). Guaranteed output and part-to-part skew characteristics make the ICS8304-02 ideal for those clock distribution applications demanding well defined performance and repeatability. • • • • • • • Four LVCMOS / LVTTL outputs, 15 output impedance • • • • Individual output enable control LVCMOS / LVTTL clock input Maximum output frequency: 250MHz Output skew: 30ps (typical) Part-to-part skew: 400ps (maximum) Small 16 lead TSSOP package saves board space Power supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V 0°C to 70°C ambient operating temperature Available in lead-free (RoHS 6) packaging For functional replacement part use 8305 Block Diagram CLK OE0 Pin Assignment OE0 OE1 VDDO Pulldown Q0 Q1 Pullup Q0 OE1 16 15 OE3 nc 3 4 5 6 14 13 12 11 10 9 GND Q3 Q2 VDDO OE2 nc 7 8 ICS8304-02 Pullup Q1 OE2 GND CLK V DD 1 2 Pullup 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View Q2 OE3 Pullup Q3 ICS8304AG-02 REVISION A FEBRUARY 4, 2013 1 ©2013 Integrated Device Technology, Inc. ICS8304-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER Pin Descriptions and Pin Characteristics Table 1. Pin Descriptions Number Name Type Description 1, 2, 10, 16 OE0, OE1, OE2, OE3 Input 3, 11 VDDO Power Output supply pins. 4, 5, 12, 13 Q0, Q1, Q2, Q3 Output Single-ended clock outputs. 15 output impedance. LVCMOS/LVTTL interface levels. 6, 14 GND Power 7 CLK Input 8 VDD Power 9, 15 nc Unused Output enable pins. Active HIGH. If pin is LOW, output is high impedance. LVCMOS/LVTTL interface levels. See Table 3. Pullup Power supply ground. Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Power supply pin. No connect. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k Power Dissipation Capacitance (per output) VDD, VDDO = 3.465V or 2.625V 5 pF CPD VDD = 3.465V, VDDO = 2.625V 3 pF Output Impedance VDDO = 3.465V 15 ROUT  VDDO = 2.625V 17  Function Table Table 3. OEx Function Table Inputs Outputs OE3, OE2, OE1, OE0 Q3, Q2, Q1, Q0 0 Hi-Z 1 Active (default) NOTE: Asynchronous output enables. ICS8304AG-02 REVISION A FEBRUARY 4, 2013 2 ©2013 Integrated Device Technology, Inc. ICS8304-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO+ 0.5V Package Thermal Impedance, JA 100.3C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter VDD Power Supply Voltage VDDO Output Supply Voltage IDD IDDO Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 3.135 3.3 3.465 V 2.375 2.5 2.625 V Power Supply Current 16 20 mA Output Supply Current 6 10 mA Table 4B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter VDD Minimum Typical Maximum Units Power Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 14 17 mA IDDO Output Supply Current 5 10 mA ICS8304AG-02 REVISION A FEBRUARY 4, 2013 Test Conditions 3 ©2013 Integrated Device Technology, Inc. ICS8304-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER Table 4C. LVCMOS/LVTTL DC Characteristics, TA = 0°C to 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum VDD = 3.465V Typical Maximum Units 2 VDD + 0.3 V VDD = 2.625V 1.7 VDD + 0.3 V VDD = 3.465V -0.3 0.8 V VDD = 2.625V -0.3 0.7 V CLK VDD = VIN = 3.465V or 2.625V 150 µA OE3, OE2, OE1, OE0 VDD = VIN = 3.465V or 2.625V 5 µA CLK VDD = 3.465V or 2.625V, VIN = 0V -5 µA OE3, OE2, OE1, OE0 VDD = 3.465V or 2.625V, VIN = 0V -150 µA VDDO = 3.3V ± 5%; IOH = -12mA 2.6 V VDDO = 2.5V ± 5%; IOH = -12mA 1.8 V VOH Output High Voltage VOL Output Low Voltage IOZL Output Hi-Z Current Low IOZH Output Hi-Z Current High VDDO = 3.3V ± 5%; IOL = 12mA 0.5 V VDDO = 2.5V ± 5%; IOL = 12mA 0.5 V -5 µA 5 µA Maximum Units 250 MHz 4.0 ns AC Electrical Characteristics Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Parameter Symbol Test Conditions fOUT Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 tsk(o) Output Skew; NOTE 2, 5 tsk(pp) Part-to-Part Skew; NOTE 3, 5 tR / tF Output Rise/Fall Time odc Output Duty Cycle tEN Output Enable Time; NOTE 4 tDIS Output Disable Time; NOTE 4 CLK Minimum 2.0 Measured on the Rising Edge Typical 2.5 30 60 ps 400 ps 20% to 80% 400 600 1000 ps Output Frequency < 150MHz 45 50 55 % Output Frequency 150MHz 40 47 60 % 3 5 ns 4 6 ns NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. ICS8304AG-02 REVISION A FEBRUARY 4, 2013 4 ©2013 Integrated Device Technology, Inc. ICS8304-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER Table 5B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C Parameter Symbol Test Conditions fOUT Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 tsk(o) Output Skew; NOTE 2, 5 tsk(pp) Part-to-Part Skew; NOTE 3, 5 tR / tF Output Rise/Fall Time CLK Minimum 2.0 Measured on the Rising Edge Typical Maximum Units 250 MHz 2.7 4.0 ns 30 60 ps 425 ps 20% to 80% 400 750 1200 ps Output Frequency < 150MHz 45 50 55 % Output Frequency 150MHz 40 47 60 % odc Output Duty Cycle tEN Output Enable Time; NOTE 4 3 5 ns tDIS Output Disable Time; NOTE 4 4 6 ns NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. Table 5C. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 70°C Parameter Symbol Test Conditions fOUT Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 tsk(o) Output Skew; NOTE 2, 5 tsk(pp) Part-to-Part Skew; NOTE 3, 5 tR / tF Output Rise/Fall Time odc Output Duty Cycle tEN Output Enable Time; NOTE 4 tDIS Output Disable Time; NOTE 4 CLK Minimum 2.0 Measured on the Rising Edge Typical 2.8 30 Maximum Units 250 MHz 4.0 ns 60 ps 425 ps 20% to 80% 400 750 1200 ps Output Frequency < 150MHz 45 50 55 % Output Frequency 150MHz 40 47 60 % 3 5 ns 4 6 ns NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. ICS8304AG-02 REVISION A FEBRUARY 4, 2013 5 ©2013 Integrated Device Technology, Inc. ICS8304-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER Parameter Measurement Information 1.65V±5% 1.25V±5% SCOPE VDD, SCOPE VDD, VDDO VDDO Qx Qx GND GND -1.65V±5% -1.25V±5% 2.5V Core/2.5V LVCMOS Output Load Test Circuit 3.3V Core/3.3V LVCMOS Output Load Test Circuit 2.05V±5% 1.25V±5% V DDO SCOPE VDD VDDO Qx 2 Qx V DDO GND Qy 2 tsk(o) -1.25V±5% Output Skew 3.3V Core/2.5V LVCMOS Output Load Test Circuit Part 1 VDD 2 V DDO Qx CLK 2 Part 2 VDDO 2 V DDO Qy Q[0:3] 2 tsk(pp) t PD Propagation Delay Part-to-Part Skew ICS8304AG-02 REVISION A FEBRUARY 4, 2013 6 ©2013 Integrated Device Technology, Inc. ICS8304-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER Parameter Measurement Information, continued VDD OE (High-level enabling) V DDO VDD/2 VDD/2 0V 2 Q[0:3] t PW t PERIOD tEN odc = t PW x 100% VDD/2 t PERIOD Q[0:3] VOH VDD/2 Output Qx Output Duty Cycle/Pulse Width/Period 80% tDIS Output Enable/Disable Time 80% 20% 20% tR tF Output Rise/Fall Time ICS8304AG-02 REVISION A FEBRUARY 4, 2013 7 ©2013 Integrated Device Technology, Inc. ICS8304-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER Applications Information Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVCMOS Outputs All control pins have internal pullup resistors; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVCMOS outputs can be left floating. There should be no trace attached. ICS8304AG-02 REVISION A FEBRUARY 4, 2013 8 ©2013 Integrated Device Technology, Inc. ICS8304-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS8304-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8304-02 is the sum of the core power plus the power dissipated due to loading. The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power (core)MAX = VDD_MAX * (IDD + IDDO) = 3.465V *(20mA + 17mA) = 128.21mW • Output Impedance ROUT Current due to Loading 50 to VDD/2 Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 15)] = 26.7mA • Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 15 * (26.7mA)2 = 10.7mW per output • Total Power (ROUT) = 10.7mW * 4 = 42.8mW Dynamic Power Dissipation at 250MHz Power (250MHz) = CPD * Frequency * (VDD)2 = 5pF * 250MHz * (3.465V)2 = 15mW per output Total Power (250MHz) = 15mW * 4 = 60mW Total Power Dissipation • Total Power = Power (core)MAX + Power (ROUT) + Power (250MHz) = 128.21mW + 42.8mW + 60mW = 231.01mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 100.3°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0231W *100.3°C/W = 93.17°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS8304AG-02 REVISION A FEBRUARY 4, 2013 0 1 2.5 100.3°C/W 96.0°C/W 93.9°C/W 9 ©2013 Integrated Device Technology, Inc. ICS8304-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER Reliability Information Table 7. JA vs. Air Flow Table for a 16 Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 100.3°C/W 96.0°C/W 93.9°C/W Transistor Count The transistor count for ICS8304-02: 2690 Package Outline and Package Dimensions Package Outline - G Suffix for 16 Lead TSSOP Table 8. Package Dimensions for 16 Lead TSSOP Symbol N A A1 A2 b c D E E1 e L  aaa All Dimensions in Millimeters Minimum Maximum 16 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.10 6.40 Basic 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS8304AG-02 REVISION A FEBRUARY 4, 2013 10 ©2013 Integrated Device Technology, Inc. ICS8304-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER Ordering Information Table 9. Ordering Information Part/Order Number 8304AG-02LF 8304AG-02LFT Marking 8304A02L 8304A02L ICS8304AG-02 REVISION A FEBRUARY 4, 2013 Package “Lead-Free” 16 Lead TSSOP “Lead-Free” 16 Lead TSSOP 11 Shipping Packaging Tube Tape & Reel Temperature 0C to 70C 0C to 70C ©2013 Integrated Device Technology, Inc. ICS8304-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER Revision History ] Revision Date May 6, 2016 Description of Change ▪ Product Discontinuation Notice - Last time buy expires May 6, 2017. ▪ PDN CQ-16-01 ICS8304AG-02 REVISION A FEBRUARY 4, 2013 12 ©2013 Integrated Device Technology, Inc. ICS8304-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. 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