Low Skew, 1-to-4 Multiplexed Differential/
LVCMOS-to-LVCMOS Fanout Buffer
ICS8305I-02
DATA SHEET
General Description
Features
The ICS8305I-02 is a low skew, 1-to-4, Differential/
LVCMOS-to-LVCMOS/LVTTL Fanout Buffer. The ICS8305I-02 has
selectable clock inputs that accept either differential or single-ended
input levels. The clock enable is internally synchronized to eliminate
runt pulses on the outputs during asynchronous assertion/
deassertion of the clock enable pin. Outputs are forced LOW when
the clock is disabled. A separate output enable pin controls whether
the outputs are in the active or high impedance state.
•
Four LVCMOS/LVTTL outputs, (two banks of two LVCMOS
outputs)
•
•
Selectable differential CLK, nCLK pair or LVCMOS_CLK input
•
LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
•
•
•
Maximum output frequency: 250MHz
•
•
-40°C to 85°C ambient operating temperature
Guaranteed output and part-to-part skew characteristics make the
ICS8305I-02 ideal for those applications demanding well defined
performance and repeatability.
Block Diagram
OEA
Pullup
CLK_EN
Pullup
CLK
nCLK
Pulldown
Pullup
CLK_SEL
Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
3.3V/1.5V
Lead-free (RoHS 6) packaging
OEA
OEB
VDD
CLK_EN
CLK
nCLK
CLK_SEL
LVCMOS_CLK
D
LE
Pulldown
Output skew: 100ps (maximum)
Pin Assignment
Q
LVCMOS_CLK
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL
00
QA0
11
Pullup
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
QA0
VDDO_A
QA1
GND
QB0
VDDO_B
QB1
GND
ICS8305I-02
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
QA1
QB0
QB1
OEB
Pullup
ICS8305AGI-02 REVISION A FEBRUARY 27, 2013
1
©2013 Integrated Device Technology, Inc.
ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Table 1. Pin Descriptions
Number
Name
Type
Description
1
OEA
Input
Pullup
Output enable for Bank A outputs. When LOW, QAx outputs are in HIGH
impedance state. When HIGH, QAx outputs are active. LVCMOS / LVTTL
interface levels.
2
OEB
Input
Pullup
Output enable for Bank B outputs. When LOW, QBx outputs are in HIGH
impedance state. When HIGH, QBx outputs are active. LVCMOS / LVTTL
interface levels.
3
VDD
Power
4
CLK_EN
Input
Pullup
5
CLK
Input
Pulldown
6
nCLK
Input
Pullup
Inverting differential clock input.
7
CLK_SEL
Input
Pullup
Clock select input. When HIGH, selects CLK, nCLK inputs.
When LOW, selects LVCMOS_CLK input. LVCMOS / LVTTL interface levels.
8
LVCMOS_CLK
Input
Pulldown
9, 13
GND
Power
Power supply ground.
10, 12
QB1, QB0
Output
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.
11
VDDO_B
Power
Output supply pin for Bank B outputs.
14, 16
QA1, QA0
Output
Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels.
15
VDDO_A
Power
Output supply pin for Bank A outputs.
Positive supply pins.
Synchronizing clock enable. When LOW, the output clocks are disabled. When
HIGH, output clocks are enabled. LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
Single-ended clock input. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
CPD
Power Dissipation Capacitance
(per output)
13
pF
VDDO_A = VDDO_B = 3.3V
9
VDDO_A = VDDO_B = 2.5V
11
VDDO_A = VDDO_B = 1.8V
15
VDDO_A = VDDO_B = 1.5V
20
ROUT
Output Impedance
ICS8305AGI-02 REVISION A FEBRUARY 27, 2013
Test Conditions
2
Minimum
Typical
Maximum
Units
©2013 Integrated Device Technology, Inc.
ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Function Tables
Table 3. Clock Input Function Table
Inputs
Outputs
OEA, OEB
CLK_EN
CLK_SEL
Selected Source
QAx, QBx
1
0
0
LVCMOS_CLK
Disabled; LOW
1
0
1
CLK, nCLK
Disabled; LOW
1
1
0
LVCMOS_CLK
Enabled
1 (default)
1 (default)
1 (default)
CLK, nCLK
Enabled
0
X
X
High-Impedance
NOTE: After CLK_EN switches, the clock outputs are disabled or enabled following a rising and
falling input clock edge as shown in Figure 1.
Enabled
Disabled
nCLK
CLK,
LVCMOS_CLK
CLK_EN
QA[0:1],
QB[0:1]
Figure 1. CLK_EN Timing Diagram
ICS8305AGI-02 REVISION A FEBRUARY 27, 2013
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©2013 Integrated Device Technology, Inc.
ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, JA
100.3C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, VDDO_A = VDDO_B = 3.3V±5% or 2.5V±5% or 1.8V±0.15V or
1.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Positive Supply Voltage
VDDO_A,
VDDO_B
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
3.135
3.3
3.465
V
2.375
2.5
2.625
V
1.65
1.8
1.95
V
1.425
1.5
1.575
V
21
mA
5
mA
Output Supply Voltage
IDD
Power Supply Current
IDDO_A +
IDDO_B
Output Supply Current
ICS8305AGI-02 REVISION A FEBRUARY 27, 2013
No Load
4
©2013 Integrated Device Technology, Inc.
ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Table 4B. LVCMOS DC Characteristics, VDD = 3.3V±5%, VDDO_A = VDDO_B = 3.3V±5% or 2.5V±5% or 1.8V±0.15V or
1.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input
High
Current
OEA, OEB,
CLK_SEL, CLK_EN
LVCMOS_CLK
Input
Low
Current
OEA, OEB,
CLK_SEL, CLK_EN
VDD = 3.465V, VIN = 0V
-150
µA
LVCMOS_CLK
VDD = 3.465V, VIN = 0V
-5
µA
VDDO_X = 3.3V ± 5%
2.6
V
VDDO_X = 2.5V ± 5%
1.8
V
VDDO_X = 1.8V ± 0.15V
1.5
V
VDDO_X = 1.5V ± 5%
VDDO_X – 0.3
V
IIL
VOH
VOL
Test Conditions
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
IOZL
Output High-Impedance Low
IOZH
Output High-Impedance High
Minimum
Typical
Maximum
Units
2
VDD + 0.3
V
-0.3
0.8
V
VDD = VIN = 3.465V
5
µA
VDD = VIN = 3.465V
150
µA
VDDO_X = 3.3V ± 5%
0.5
V
VDDO_X = 2.5V ± 5%
0.4
V
VDDO_X = 1.8V ± 0.15V
0.35
V
VDDO_X = 1.5V ± 5%
0.30
V
-5
µA
5
µA
NOTE: VDDO_X denotes VDDO_A and VDDO_B.
NOTE 1: Outputs terminated with 50 to VDDO_X/2. See Parameter Measurement Information section, Output Load Test Circuit diagrams.
Table 4C. DC Characteristics, VDD = 3.3V±5%, VDDO_A = VDDO_B = 3.3V±5% or 2.5V±5% or 1.8V±0.15V or 1.5V±5%,
TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
IIH
Input
High Current
IIL
Input
Low Current
VPP
Peak-to-Peak Input Voltage; NOTE 1
VCMR
Input Common Mode Voltage;
NOTE 1, 2
Minimum
Typical
Maximum
Units
CLK,
VDD = VIN = 3.465V
150
µA
nCLK
VDD = VIN = 3.465V
5
µA
CLK
VDD = 3.465V, VIN = 0V
-5
µA
nCLK
VDD = 3.465V, VIN = 0V
-150
µA
0.15
1.3
V
GND + 0.5
VDD – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as VIH.
ICS8305AGI-02 REVISION A FEBRUARY 27, 2013
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©2013 Integrated Device Technology, Inc.
ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDO_A = VDDO_B = 3.3V±5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
fOUT
Output Frequency
tPD
Propagation Delay; NOTE 1
tsk(o)
Output Skew; NOTE 2, 4
tsk(pp)
Maximum
Units
250
MHz
3.2
ns
100
ps
Part-to-Part Skew; NOTE 3, 4
900
ps
tsk(b)
Bank Skew; NOTE 4, 5
35
ps
tjit
Buffer Additive Phase
Jitter, RMS; refer to
Additive Phase Jitter
Section, NOTE 6
tR / t F
Output Rise/Fall Time; NOTE 7
CLK, nCLK
Minimum
Typical
1.9
Measured on the Rising Edge
156.25MHz, Integration Range:
12kHz - 20MHz
0.25
ps
20% to 80%
100
700
ps
CLK, nCLK
ƒOUT 156.25MHz
45
55
%
LVCMOS_CLK
ƒOUT 156.25MHz
40
60
%
odc
Output Duty Cycle;
NOTE 8
tEN
Output Enable Time: NOTE 7
5
ns
tDIS
Output Disable Time: NOTE 7
5
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at ƒ 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input clock (LVCMOS_CLK) or from the differential input crossing point (CLK, nCLK) to VDDO_X/2 of
the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO_X/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages, with equal load conditions. Using the
same type of inputs on each device, the outputs are measured at VDDO_X/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 6: Driving only one input clock.
NOTE 7: These parameters are guaranteed by characterization. Not tested in production.
NOTE 8: Input duty cycle must be 50%.
ICS8305AGI-02 REVISION A FEBRUARY 27, 2013
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©2013 Integrated Device Technology, Inc.
ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Table 5B. AC Characteristics, VDD = 3.3V±5%, VDDO_A = VDDO_B = 2.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency
Test Conditions
tPD
Propagation Delay; NOTE 1
tsk(o)
Output Skew; NOTE 2, 4
tsk(pp)
Minimum
Typical
Units
250
MHz
3.2
ns
100
ps
Part-to-Part Skew; NOTE 3, 4
900
ps
tsk(b)
Bank Skew; NOTE 4, 5
35
ps
tjit
Buffer Additive Phase
Jitter, RMS; refer to
Additive Phase Jitter
Section, NOTE 6
tR / t F
Output Rise/Fall Time; NOTE 7
CLK, nCLK
1.9
Maximum
Measured on the Rising Edge
156.25MHz, Integration Range:
12kHz - 20MHz
0.25
ps
20% to 80%
100
700
ps
CLK, nCLK
ƒOUT 156.25MHz
45
55
%
LVCMOS_CLK
ƒOUT 156.25MHz
40
60
%
odc
Output Duty Cycle;
NOTE 8
tEN
Output Enable Time: NOTE 7
5
ns
tDIS
Output Disable Time: NOTE 7
5
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at ƒ 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input clock (LVCMOS_CLK) or from the differential input crossing point (CLK, nCLK) to VDDO_X/2 of
the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO_X/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages, with equal load conditions. Using the
same type of inputs on each device, the outputs are measured at VDDO_X/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 6: Driving only one input clock.
NOTE 7: These parameters are guaranteed by characterization. Not tested in production.
NOTE 8: Input duty cycle must be 50%.
ICS8305AGI-02 REVISION A FEBRUARY 27, 2013
7
©2013 Integrated Device Technology, Inc.
ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Table 5C. AC Characteristics, VDD = 3.3V±5%, VDDO_A = VDDO_B = 1.8V±0.15V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
3.9
ns
100
ps
fOUT
Output Frequency
tPD
Propagation Delay; NOTE 1
tsk(o)
Output Skew; NOTE 2, 4
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
1.2
ns
tsk(b)
Bank Skew; NOTE 4, 5
50
ps
tjit
Buffer Additive Phase
Jitter, RMS; refer to
Additive Phase Jitter
Section, NOTE 6
tR / t F
Output Rise/Fall Time; NOTE 7
CLK, nCLK
2.2
Measured on the Rising Edge
156.25MHz, Integration Range:
12kHz - 20MHz
0.28
ps
20% to 80%
100
800
ps
CLK, nCLK
ƒOUT 156.25MHz
45
55
%
LVCMOS_CLK
ƒOUT 156.25MHz
40
60
%
odc
Output Duty Cycle;
NOTE 8
tEN
Output Enable Time: NOTE 7
5
ns
tDIS
Output Disable Time: NOTE 7
5
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at ƒ 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input clock (LVCMOS_CLK) or from the differential input crossing point (CLK, nCLK) to VDDO_X/2 of
the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO_X/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages, with equal load conditions. Using the
same type of inputs on each device, the outputs are measured at VDDO_X/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 6: Driving only one input clock.
NOTE 7: These parameters are guaranteed by characterization. Not tested in production.
NOTE 8: Input duty cycle must be 50%.
ICS8305AGI-02 REVISION A FEBRUARY 27, 2013
8
©2013 Integrated Device Technology, Inc.
ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Table 5D. AC Characteristics, VDD = 3.3V±5%, VDDO_A = VDDO_B = 1.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
4.3
ns
100
ps
fOUT
Output Frequency
tPD
Propagation Delay; NOTE 1
tsk(o)
Output Skew; NOTE 2, 4
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
1.6
ns
tsk(b)
Bank Skew; NOTE 4, 5
50
ps
tjit
Buffer Additive Phase
Jitter, RMS; refer to
Additive Phase Jitter
Section, NOTE 6
tR / t F
Output Rise/Fall Time; NOTE 7
CLK, nCLK
2.5
Measured on the Rising Edge
156.25MHz, Integration Range:
12kHz - 20MHz
0.35
ps
20% to 80%
100
800
ps
CLK, nCLK
ƒOUT 156.25MHz
45
55
%
LVCMOS_CLK
ƒOUT 156.25MHz
40
60
%
odc
Output Duty Cycle;
NOTE 8
tEN
Output Enable Time: NOTE 7
5
ns
tDIS
Output Disable Time: NOTE 7
5
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at ƒ 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input clock (LVCMOS_CLK) or from the differential input crossing point (CLK, nCLK) to VDDO_X/2 of
the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO_X/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages, with equal load conditions. Using the
same type of inputs on each device, the outputs are measured at VDDO_X/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 6: Driving only one input clock.
NOTE 7: These parameters are guaranteed by characterization. Not tested in production.
NOTE 8: Input duty cycle must be 50%.
ICS8305AGI-02 REVISION A FEBRUARY 27, 2013
9
©2013 Integrated Device Technology, Inc.
ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
SSB Phase Noise dBc/Hz
Additive Phase Jitter @ 156.25MHz
12kHz to 20MHz = 0.25ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
ICS8305AGI-02 REVISION A FEBRUARY 27, 2013
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Measured using a Rohde & Schwarz SMA100 as the input source.
10
©2013 Integrated Device Technology, Inc.
ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Parameter Measurement Information
2.05V±5%
1.65V±5%
1.25V±5%
SCOPE
VDD,
VDDO_A,
VDDO_B
SCOPE
VDD
VDDO_A,
VDDO_B
GND
Qx
Qx
GND
-1.65V±5%
-1.25V±5%
3.3V Core/3.3V LVCMOS Output Load Test Circuit
3.3V Core/2.5V LVCMOS Output Load Test Circuit
2.4V±0.09V
2.55V±5%
0.75V±5%
0.9V±0.075V
SCOPE
VDD
VDDO_A,
VDDO_B
GND
SCOPE
VDD
VDDO_A,
VDDO_B
GND
Qx
Qx
-0.75V±5%
-0.9V±0.075V
3.3V Core/1.8V LVCMOS Output Load Test Circuit
3.3V Core/1.5V LVCMOS Output Load Test Circuit
VDD
V
DDO_X
Qx
nCLK
V
PP
Cross Points
2
V
CMR
V
DDO_X
CLK
Qy
2
tsk(o)
GND
Differential Input Level
ICS8305AGI-02 REVISION A FEBRUARY 27, 2013
Output Skew
11
©2013 Integrated Device Technology, Inc.
ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Parameter Measurement Information, continued
Part 1
V
QX0
DDO_X
Qx
VDDO_X
2
2
VDDO_X
2
Part 2
QX1
V
DDO_X
Qy
2
tsk(pp)
tsk(b)
Where X denotes outputs in the same Bank
Part-to-Part Skew
Bank Skew
V
DDO_X
QA[0:1],
QB[0:1]
80%
80%
2
t PW
t
PERIOD
20%
20%
QA[0:1],
QB[0:1]
tR
tF
odc =
t PW
x 100%
t PERIOD
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
nCLK
CLK
VDD
LVCMOS_CLK
2
VDDO_X
QA[0:1],
QB[0:1]
2
tpLH
Propagation Delay
ICS8305AGI-02 REVISION A FEBRUARY 27, 2013
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©2013 Integrated Device Technology, Inc.
ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VDD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1in the center of the input voltage swing. For
example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2
value should be adjusted to set V1 at 1.25V. The values below are for
when both the single ended swing and VDD are at the same voltage.
This configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
impedance. For most 50 applications, R3 and R4 can be 100. The
values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS8305AGI-02 REVISION A FEBRUARY 27, 2013
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©2013 Integrated Device Technology, Inc.
ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVCMOS Outputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
All unused LVCMOS output can be left floating. There should be no
trace attached.
LVCMOS_CLK Input
For applications not requiring the use of the single-ended clock input,
it can be left floating. Though not required, but for additional
protection, a 1k resistor can be tied from the LVCMOS_CLK input
to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
ICS8305AGI-02 REVISION A FEBRUARY 27, 2013
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©2013 Integrated Device Technology, Inc.
ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Differential Clock Input Interface
with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 3A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. The differential signals must meet the VPP and
VCMR input requirements. Figures 3A to 3E show interface examples
for the CLK/nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
Differential
Input
LVHSTL
IDT
LVHSTL Driver
R1
50Ω
Differential
Input
LVPECL
nCLK
R2
50Ω
R1
50Ω
R2
50Ω
R2
50Ω
Figure 3B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 3A. CLK/nCLK Input Driven by an IDT Open
Emitter LVHSTL Driver
3.3V
3.3V
3.3V
3.3V
3.3V
Zo = 50Ω
CLK
CLK
R1
100Ω
nCLK
Zo = 50Ω
Differential
Input
LVPECL
LVDS
nCLK
Receiver
Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
Figure 3C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
3.3V
*R3
CLK
nCLK
HCSL
*R4
Differential
Input
Figure 3E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
ICS8305AGI-02 REVISION A FEBRUARY 27, 2013
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©2013 Integrated Device Technology, Inc.
ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8305I-02.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8305I-02 is the sum of the core power plus the power dissipation due to loading.
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * IDD_MAX= 3.465V *21mA = 72.765mW
LVCMOS Driver Power Dissipation
•
Output Impedance ROUT Power Dissipation due to Loading 50 to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 9)] = 35.36mA
•
Power Dissipation on the ROUT per LVCMOS output
Power (LVCMOS) = ROUT * (IOUT)2 = 9 * (35.36mA)2 = 11.25mW per output
Total Power Dissipation on the ROUT
Total Power (ROUT) = 11.25mW * 4 = 45mW
Dynamic Power Dissipation at 250MHz
Power (250MHz) = CPD * Frequency * (VDD)2 * Number of outputs = 13pF * 250MHz * (3.465V)2 * 4 = 156.53mW
Total Power
= Power (core)MAX + Total Power (ROUT) + Power (250MHz)
= 72.765mW + 45mW + 156.53mW
= 274.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 100.3°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.274W *100.3°C/W = 112.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
ICS8305AGI-02 REVISION A FEBRUARY 27, 2013
0
1
2.5
100.3°C/W
96.0°C/W
93.9°C/W
16
©2013 Integrated Device Technology, Inc.
ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Reliability Information
Table 7. JA vs. Air Flow Table for a 16 Lead TSSOP
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
100.3°C/W
96.0°C/W
93.9°C/W
Transistor Count
The transistor count for ICS8305I-02: 538
Package Outline and Package Dimensions
Package Outline - G Suffix for 16 Lead TSSOP
Table 8. Package Dimensions for 16 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
16
A
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
5.10
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS8305AGI-02 REVISION A FEBRUARY 27, 2013
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©2013 Integrated Device Technology, Inc.
ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Ordering Information
Table 9. Ordering Information
Part/Order Number
8305AGI-02LF
8305AGI-02LFT
Marking
305AI02L
305AI02L
ICS8305AGI-02 REVISION A FEBRUARY 27, 2013
Package
“Lead-Free” 16 Lead TSSOP
“Lead-Free” 16 Lead TSSOP
18
Shipping Packaging
Tube
Tape & Reel
Temperature
-40C to 85C
-40C to 85C
©2013 Integrated Device Technology, Inc.
ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
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