83905AK-01LFT

Low Skew, 1:6 Crystal-to-LVCMOS Fanout Buffer 83905-01 DATA SHEET General Description Features The 83905-01 is a low skew, 1-to-6 LVCMOS Fanout Buffer. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 6 to 12 by utilizing the ability of the outputs to drive two series terminated lines. • • • • • • The 83905-01 is characterized at full 1.8V, 1.5V, and 1.2V, mixed 1.8V/1.5V, 1.8V/1.2V and 1.5V/1.2V output operating supply mode. Guaranteed output skew characteristics along with the 1.2V output capabilities makes the 83905-01 ideal for high performance, single ended applications that also require a limited output voltage. ENABLE2 XTAL_OUT XTAL_IN ENABLE1 nc 19 18 17 16 GND 1 15 BCLK5 GND 2 14 VDDO BCLK0 3 13 BCLK4 VDDO 4 12 GND BCLK1 5 11 GND 83905-01 BCLK2 9 VDD 8 Crystal Oscillator Interface Crystal input frequency range: 10MHz to 40MHz Output skew: 95ps (maximum) RMS phase jitter @ 25MHz, (100Hz – 1MHz): 0.17ps (typical) • • Synchronous output enables • • 0°C to 70°C ambient operating temperature Power supply modes: Full 1.8V, 1.5V, 1.2V Mixed 1.8V core/1.5V output operating supply Mixed 1.8V core/1.2V output operating supply Mixed 1.5V core/1.2V output operating supply Available in lead-free (RoHS 6) package Block Diagram 10 BCLK0 BCLK3 7 GND GND 6 Outputs able to drive 12 series terminated lines Noise Power Offset 100Hz................. -115 dBc/Hz 1kHz ................... -138 dBc/Hz 10kHz ................. -154 dBc/Hz 100kHz ............... -160 dBc/Hz Pin Assignments 20 Six LVCMOS outputs BCLK1 XTAL_IN 20-pin, 4mm x 4mm VFQFN Package BCLK2 XTAL_OUT XTAL_OUT 1 16 XTAL_IN ENABLE2 GND 2 15 3 14 ENABLE1 BCLK5 BCLK0 VDDO BCLK1 GND BCLK2 4 13 5 12 6 11 7 10 8 9 BCLK3 VDDO BCLK4 GND BCLK3 VDD BCLK4 ENABLE 1 SYNCHRONIZE BCLK5 ENABLE 2 SYNCHRONIZE 83905-01 16-pin, 4.4mm x 5.0mm TSSOP Package 83905-01 REVISION 1 05/01/15 1 ©2015 Integrated Device Technology, Inc. 83905-01 DATA SHEET Pin Descriptions and Characteristics Table 1. Pin Descriptions Name Type Description XTAL_OUT Output Crystal oscillator interface. XTAL_IN Input Crystal oscillator interface. ENABLE1, ENABLE2 Input Clock enable. LVCMOS/LVTTL interface levels. See Table 3. BCLK0, BCLK1, BCLK2, BCLK3, BCLK4, BCLK5 Output Clock outputs. LVCMOS interface levels. GND Power Power supply ground. VDD Power Power supply pin. VDDO Power Output supply pin. nc Unused No connect. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance (per output) ROUT Test Conditions ENABLE[2:1] Output Impedance Minimum Typical Maximum Units 4 pF VDDO = 2.0V 12 pF VDDO = 1.6V 12 pF VDDO = 1.26V 12 pF VDDO = 1.8V ± 0.2V 17  VDDO = 1.5V ± 0.1V 18  VDDO = 1.2V ± 5% 24  Function Table Table 3. Clock Enable Function Table Control Inputs Outputs ENABLE 1 ENABLE2 BCLK[0:4] BCLK5 0 0 LOW LOW 0 1 LOW Toggling 1 0 Toggling LOW 1 1 Toggling Toggling BCLK5 BCLK[0:4] ENABLE2 ENABLE1 Figure 1. Enable Timing Diagram LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 2 REVISION 1 05/01/15 83905-01 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Input, VI Crystal Oscillator Input 0V to VDD Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, TJ 125C Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDO = 1.8V ±0.2V, TA = 0°C to 70°C Symbol Parameter Minimum Typical Maximum Units VDD Power Supply Voltage Test Conditions 1.6 1.8 2.0 V VDDO Output Supply Voltage 1.6 1.8 2.0 V 4 10 mA 1 mA IDD; NOTE 1 Power Supply Current ENABLE [1:2] = 00 IDDO; NOTE 1 Output Supply Current ENABLE [1:2] = 00 NOTE 1: Measured with outputs unterminated, and XTAL_IN and XTAL_OUT floated. Table 4B. Power Supply DC Characteristics, VDD = VDDO = 1.5V ±0.1V, TA = 0°C to 70°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Power Supply Voltage 1.4 1.5 1.6 V VDDO Output Supply Voltage 1.4 1.5 1.6 V IDD; NOTE 1 Power Supply Current ENABLE [1:2] = 00 3 7 mA IDDO; NOTE 1 Output Supply Current ENABLE [1:2] = 00 1 mA NOTE 1: Measured with outputs unterminated, and XTAL_IN and XTAL_OUT floated. Table 4C. Power Supply DC Characteristics, VDD = VDDO = 1.2V ±5%, TA = 0°C to 70°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Power Supply Voltage 1.14 1.2 1.26 V VDDO Output Supply Voltage 1.14 1.2 1.26 V IDD; NOTE 1 Power Supply Current ENABLE [1:2] = 00 2 6 mA IDDO; NOTE 1 Output Supply Current ENABLE [1:2] = 00 1 mA NOTE 1: Measured with outputs unterminated, and XTAL_IN and XTAL_OUT floated. REVISION 1 05/01/15 3 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 83905-01 DATA SHEET Table 4D. Power Supply DC Characteristics, VDD = 1.8V ±0.2V, VDDO = 1.5V ±0.1V, TA = 0°C to 70°C Symbol Parameter Minimum Typical Maximum Units VDD Power Supply Voltage Test Conditions 1.6 1.8 2.0 V VDDO Output Supply Voltage 1.4 1.5 1.6 V IDD; NOTE 1 Power Supply Current ENABLE [1:2] = 00 4 10 mA IDDO; NOTE 1 Output Supply Current ENABLE [1:2] = 00 1 mA NOTE 1: Measured with outputs unterminated, and XTAL_IN and XTAL_OUT floated. Table 4E. Power Supply DC Characteristics, VDD = 1.8V ±0.2V, VDDO = 1.2V ±5%, TA = 0°C to 70°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Power Supply Voltage 1.6 1.8 2.0 V VDDO Output Supply Voltage 1.14 1.2 1.26 V IDD; NOTE 1 Power Supply Current ENABLE [1:2] = 00 4 10 mA IDDO; NOTE 1 Output Supply Current ENABLE [1:2] = 00 1 mA NOTE 1: Measured with outputs unterminated, and XTAL_IN and XTAL_OUT floated. Table 4F. Power Supply DC Characteristics, VDD = 1.5V ±0.1V, VDDO = 1.2V ±5%, TA = 0°C to 70°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Power Supply Voltage 1.4 1.5 1.6 V VDDO Output Supply Voltage 1.14 1.2 1.26 V IDD; NOTE 1 Power Supply Current ENABLE [1:2] = 00 3 7 mA IDDO; NOTE 1 Output Supply Current ENABLE [1:2] = 00 1 mA Maximum Units NOTE 1: Measured with outputs unterminated, and XTAL_IN and XTAL_OUT floated. Table 4G. LVCMOS/LVTTL DC Characteristics, TA = 0°C to 70°C Symbol VIH VIL VOH VOL Parameter Input High Voltage Input Low Voltage Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Test Conditions Minimum Typical VDD = 1.8V ± 0.2V 1.2 VDD + 0.3 V VDD = 1.5V ± 0.1V 1.0 VDD + 0.3 V VDD = 1.2V ± 5% 0.8 VDD + 0.3 V VDD = 1.8V ± 0.2V -0.3 0.4 V VDD = 1.5V ± 0.1V -0.3 0.3 V VDD = 1.2V ± 5% -0.3 0.2 V VDDO = 1.8V ± 0.2V 0.7 V VDDO = 1.5V ± 0.1V 0.7 V VDDO = 1.2V ± 5% 0.7 V VDDO = 1.8V ± 0.2V 0.4 V VDDO = 1.5V ± 0.1V 0.4 V VDDO = 1.2V ± 5% 0.4 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams. LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 4 REVISION 1 05/01/15 83905-01 DATA SHEET Table 5. Crystal Characteristics Parameter Test Conditions Minimum Maximum Units 40 MHz Equivalent Series Resistance (ESR) 50  Shunt Capacitance 7 pF 12 18 pF Typical Mode of Oscillation Typical Fundamental Frequency 10 Load Capacitance AC Electrical Characteristics Table 6A. AC Characteristics, VDD = VDDO = 1.8V ±0.2V, TA = 0°C to 70°C Symbol Parameter Maximum Units Using External Crystal Test Conditions 10 40 MHz Using External Clock Source NOTE 1 1 100 MHz 90 ps fMAX Output Frequency tsk(o) Output Skew; NOTE 2, 3 tjit RMS Phase Jitter (Random); NOTE 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle tEN Output Enable Time; NOTE 5 tDIS Output Disable Time; NOTE 5 Minimum 25MHz, Integration Range: 100Hz – 1MHz 20% to 80% 0.17 300 ps 600 ps 58 % ENABLE1 4 cycles ENABLE2 4 cycles ENABLE1 4 cycles ENABLE2 4 cycles 42 50 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ  40MHz using a crystal input unless noted otherwise. Outputs terminated with 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by an external source. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: See phase noise plot. NOTE 5: These parameters are guaranteed by design. Not tested in production. REVISION 1 05/01/15 5 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 83905-01 DATA SHEET Table 6B. AC Characteristics, VDD = VDDO = 1.5V ±0.1V, TA = 0°C to 70°C Symbol Parameter Test Conditions fMAX Output Frequency tsk(o) Output Skew; NOTE 2, 3 tjit RMS Phase Jitter (Random) tR / tF Output Rise/Fall Time odc Output Duty Cycle tEN Output Enable Time; NOTE 4 tDIS Output Disable Time; NOTE 4 Minimum Typical Maximum Units Using External Crystal 10 40 MHz Using External Clock Source; NOTE 1 1 100 MHz 90 ps 25MHz, Integration Range: 100Hz – 1MHz 20% to 80% 0.3 300 ps 650 ps 56 % ENABLE1 4 cycles ENABLE2 4 cycles ENABLE1 4 cycles ENABLE2 4 cycles 44 50 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ  40MHz using a crystal input unless noted otherwise. Outputs terminated with 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by an external source. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by design. Not tested in production. Table 6C. AC Characteristics, VDD = VDDO = 1.2V ±5%, TA = 0°C to 70°C Symbol Parameter Test Conditions fMAX Output Frequency tsk(o) Output Skew; NOTE 2, 3 tjit RMS Phase Jitter (Random) Typical Maximum Units Using External Crystal 10 40 MHz Using External Clock Source; NOTE 1 1 100 MHz 90 ps tR / tF Output Rise/Fall Time odc Output Duty Cycle tEN Output Enable Time; NOTE 4 Output Disable Time; NOTE 4 tDIS Minimum 25MHz, Integration Range: 100Hz – 1MHz 20% to 80% 0.7 350 ps 800 ps 56 % ENABLE1 4 cycles ENABLE2 4 cycles ENABLE1 4 cycles ENABLE2 4 cycles 44 50 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ  40MHz using a crystal input unless noted otherwise. Outputs terminated with 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by an external source. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by design. Not tested in production. LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 6 REVISION 1 05/01/15 83905-01 DATA SHEET Table 6D. AC Characteristics, VDD = 1.8V ±0.2V, VDDO = 1.5V ±0.1V, TA = 0°C to 70°C Symbol Parameter Test Conditions fMAX Output Frequency tsk(o) Output Skew; NOTE 2, 3 tjit RMS Phase Jitter (Random) tR / tF Output Rise/Fall Time odc Output Duty Cycle tEN Output Enable Time; NOTE 4 tDIS Output Disable Time; NOTE 4 Minimum Typical Maximum Units Using External Crystal 10 40 MHz Using External Clock Source; NOTE 1 1 100 MHz 90 ps 25MHz, Integration Range: 100Hz – 1MHz 20% to 80% 0.18 300 ps 650 ps 60 % ENABLE1 4 cycles ENABLE2 4 cycles ENABLE1 4 cycles ENABLE2 4 cycles 40 50 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ  40MHz using a crystal input unless noted otherwise. Outputs terminated with 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by an external source. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by design. Not tested in production. Table 6E. AC Characteristics, VDD = 1.8V ±0.2V, VDDO = 1.2V ±5%, TA = 0°C to 70°C Symbol Parameter Test Conditions fMAX Output Frequency tsk(o) Output Skew; NOTE 2, 3 tjit RMS Phase Jitter (Random) Typical Maximum Units Using External Crystal 10 40 MHz Using External Clock Source; NOTE 1 1 100 MHz 95 ps tR / tF Output Rise/Fall Time odc Output Duty Cycle tEN Output Enable Time; NOTE 4 Output Disable Time; NOTE 4 tDIS Minimum 25MHz, Integration Range: 100Hz – 1MHz 20% to 80% 0.2 350 ps 800 ps 58 % ENABLE1 4 cycles ENABLE2 4 cycles ENABLE1 4 cycles ENABLE2 4 cycles 42 50 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ  40MHz using a crystal input unless noted otherwise. Outputs terminated with 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by an external source. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by design. Not tested in production. REVISION 1 05/01/15 7 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 83905-01 DATA SHEET Table 6F. AC Characteristics, VDD = 1.5V ±0.1V, VDDO = 1.2V ±5%, TA = 0°C to 70°C Symbol Parameter Test Conditions fMAX Output Frequency tsk(o) Output Skew; NOTE 2, 3 tjit RMS Phase Jitter (Random) tR / tF Output Rise/Fall Time odc Output Duty Cycle tEN Output Enable Time; NOTE 4 tDIS Output Disable Time; NOTE 4 Minimum Typical Maximum Units Using External Crystal 10 40 MHz Using External Clock Source; NOTE 1 1 100 MHz 90 ps 25MHz, Integration Range: 100Hz – 1MHz 20% to 80% 0.34 350 ps 800 ps 58 % ENABLE1 4 cycles ENABLE2 4 cycles ENABLE1 4 cycles ENABLE2 4 cycles 42 50 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ  40MHz using a crystal input unless noted otherwise. Outputs terminated with 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by an external source. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by design. Not tested in production. LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 8 REVISION 1 05/01/15 83905-01 DATA SHEET Noise Power (dBc/Hz) Typical Phase Noise at 25MHz (1.8V Core, 1.8V Output) Offset Frequency (Hz) REVISION 1 05/01/15 9 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 83905-01 DATA SHEET Parameter Measurement Information 0.75V±0.05V 0.9V±0.1V SCOPE VDD, VDDO SCOPE VDD, VDDO Qx Qx GND GND -0.75V±0.05V -0.9V±0.1V 1.5V Core/1.5V LVCMOS Output Load Test Circuit 1.8V Core/1.8V LVCMOS Output Load Test Circuit 1.05V±0.15V 0.6V±5% 0.75V±0.05V SCOPE VDD, VDDO SCOPE VDD VDDO Qx Qx GND GND -0.75V±0.05V -0.6V±5% 1.8V Core/1.5V LVCMOS Output Load Test Circuit 1.2V Core/1.2V LVCMOS Output Load Test Circuit 1.2V±0.2V 0.9V±0.07V 0.6V±5% 0.6V±5% SCOPE VDD VDDO SCOPE VDD VDDO Qx GND GND -0.6V±5% -0.6V±5% 1.5V Core/1.2V LVCMOS Output Load Test Circuit 1.8V Core/1.2V LVCMOS Output Load Test Circuit LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER Qx 10 REVISION 1 05/01/15 83905-01 DATA SHEET Parameter Measurement Information, continued VDDO 2 BCLKx VDDO 2 BCLKy tsk(b) RMS Phase Jitter Output Skew V DDO 80% 80% 2 BCLK[0:5] t PW t 20% 20% BCLK[0:5] tR tF odc = PERIOD t PW x 100% t PERIOD Output Duty Cycle/Pulse Width/Period Output Rise/Fall Time VDD OEx (High-level enabling) VDD/2 VDD/2 0V tEN Output BCLKx (See Note) tDIS VOH VDDO/2 VOL Output Enable/Disable REVISION 1 05/01/15 11 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 83905-01 DATA SHEET Application Information Recommendations for Unused Output Pins Outputs: LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. Crystal Input Interface The 83905-01 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 15pF X1 18pF Parallel Crystal XTAL_OUT C2 15pF Figure 2. Crystal Input Interface LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 12 REVISION 1 05/01/15 83905-01 DATA SHEET Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 3A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This VCC can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 3B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. XTAL_OUT R1 100 Ro Rs C1 Zo = 50 ohms XTAL_IN R2 100 Zo = Ro + Rs .1uf LVCMOS Driver Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface XTAL_OUT C2 Zo = 50 ohms XTAL_IN .1uf Zo = 50 ohms LVPECL Driver R1 50 R2 50 R3 50 Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface REVISION 1 05/01/15 13 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 83905-01 DATA SHEET Schematic Example Figure 4 shows an example of the 83905-01 application schematic. In this example, the device is operated at VDD = VDDO = 1.8V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by an 18pF load resonant quartz crystal. The tuning capacitors C1 and C2 are fairly accurate, but   minor adjustments might be required. For the LVCMOS output drivers, two termination examples are shown in this schematic. For additional termination examples, see LVCMOS Termination Application Note. VD DO = 1.8V VDD = 1. 8V R2 31 Z o = 50 Ohm CL = 18 pf C2 15pf C1 15pF LVCMO S U1 EN ABLE 2 VDD O 1 2 3 4 5 6 7 8 XTAL_OUT EN ABLE 2 GND BC LK0 VD DO BC LK1 GND BC LK2 XTAL_IN EN ABLE 1 BCLK5 VD DO BCLK4 G ND BCLK3 VDD 16 15 14 13 12 11 10 9 ENABLE 1 VDD R3 100 Z o = 50 Ohm R4 100 LVCMO S VDD C3 10uF VDD O C4 .1uF C5 . 1uF Optional Termination C6 .1uF Unused outputs can be left floating. There should be no trace attached to unused outputs. Device characterized and specification limits set with all outputs terminated. Figure 4. 83905-01 Schematic Layout LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 14 REVISION 1 05/01/15 83905-01 DATA SHEET Power Considerations This section provides information on power dissipation and junction temperature for the 83905-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 83905-01 is the sum of the core power plus the analog power plus the power dissipated due to the load. The following is the power dissipation for VDD = 1.8V + 0.2V = 2.0V, which gives worst case results. • Power (core)MAX = VDD_MAX * IDD = 2V * 10mA = 20mW • Output Impedance ROUT Power Dissipation due to Loading 50 to VDD/2 Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 2V / [2 * (50 + 17)] = 14.9mA • Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 17 * (14.9mA)2 = 3.8mW per output • Total Power Dissipation on the ROUT Total Power (ROUT) = 3.8mW * 6 = 22.8mW Dynamic Power Dissipation at 100MHz Power (100MHz) = CPD * Frequency * (VDD)2 = 12pF * 100MHz * (2V)2 = 4.8mW per output Total Power (100MHz) = 4.8mW * 6 = 28.8mW Total Power Dissipation • Total Power = Power (core)MAX + Total Power (ROUT) + Total Power (100MHz) = 20mW + 22.8mW + 28.8mW = 71.6mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 100.3°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.072W *100.3°C/W = 77.2°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance JA for 16-Lead TSSOP, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards REVISION 1 05/01/15 0 1 2.5 100.3°C/W 96.0°C/W 93.9°C/W 15 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 83905-01 DATA SHEET Reliability Information Table 8A. JA vs. Air Flow Table for a 16-Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 100.3°C/W 96.0°C/W 93.9°C/W 0 1 2.5 57.5°C/W 50.3°C/W 45.1°C/W Table 8B. JA vs. Air Flow Table for a 20-Lead VFQFN JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for 83905-01: 505 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 16 REVISION 1 05/01/15 83905-01 DATA SHEET 16-Lead TSSOP Package Outline and Package Dimensions Package Outline - G Suffix for 16-Lead TSSOP Table 9A. Package Dimensions for 16-Lead TSSOP All Dimensions in Millimeters Symbol Minimum N Maximum 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E E1 6.40 Basic 4.30 e 4.50 0.65 Basic L 0.45 0.75  0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 REVISION 1 05/01/15 17 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 83905-01 DATA SHEET 20-Lead VFQFN Package Outline and Package Dimensions Package Outline - K Suffix for 20-Lead VFQFN Table 9C. Package Dimensions for 20-Lead VFQFN NOTE: All Dimensions in Millimeters Symbol Minimum Nom Maximum b 0.20 0.25 0.30 D 3.90 4.00 4.10 E 3.90 4.00 4.10 D2 1.95 2.10 2.25 E2 1.95 2.10 2.25 L 0.45 0.55 0.65 e 0.50 BSC N 20 A 0.80 0.90 1.00 A1 0.00 0.02 0.05 A3 The drawing and dimension data originate from IDT package outline drawing PSC-4170, rev03. 1. Dimensions and tolerances conform to ASME Y14.5M-1994 2. All dimensions are in millimeters. All angles are in degrees. 3. N is the total number of terminals. 4. All specifications comply with JEDEC MO-220. 0.2 REF Reference Document: JEDEC Publication 95, MO-220 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 18 REVISION 1 05/01/15 83905-01 DATA SHEET Ordering Information Table 10. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 83905AG-01LF 3905A01L 16-Lead TSSOP, Lead-Free Tube 0C to 70C 83905AG-01LFT 3905A01L 16-Lead TSSOP, Lead-Free Tape & Reel 0C to 70C 83905AK-01LF 5A01L 20-Lead VFQFN, Lead-Free Tray 0C to 70C 83905AK-01LFT 5A01L 20-Lead VFQFN, Lead-Free Tape & Reel 0C to 70C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 19 REVISION 1 05/01/15 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. 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