Programmable FemtoClock® NG
ICS83PN128I
Differential-to-3.3V, 2.5V LVPECL Synthesizer
DATA SHEET
General Description
Features
The ICS83PN128I is a programmable LVPECL synthesizer that can
be used for frequency conversions. The device uses IDT’s fourth
generation FemtoClock® NG technology for optimal high clock
frequency and low phase noise performance, combined with a low
power consumption and high power supply noise rejection.
Oscillator-level performance is maintained with IDT’s Fourth
Generation FemtoClock® NG PLL technology, which delivers low
rms phase jitter.
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Fourth Generation FemtoClock® NG technology
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Output frequency: 128.90MHz or 161.132813MHz
The ICS83PN128I defaults to 161.132813MHz output using a
156.25MHz input with two select pins floating (pulled up with internal
pullup resistors) but can also be set to four different frequency
multiplier settings to support a wide variety of applications. The
below table shows some of the more common application settings.
Footprint compatible with 5mm x 7mm differential oscillators
One differential LVPECL output pair
CLK, nCLK input pair can accept the following levels: HCSL,
LVDS, LVPECL, LVHSTL
VCO range: 2.0GHz – 2.5GHz
Cycle-to-cycle jitter: 18ps (typical)
RMS phase jitter @ 128.90MHz, 12kHz – 20MHz: 0.53ps (typical)
Full 3.3V or 2.5V operating supply
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Frequency Select Table
156.25
128.90
01
156.25
128.90
10
156.25
128.90
11 (default)
156.25
161.132813
OE
1
Reserved
2
VEE
3
10
9
4
5
CLK
00
Pin Assignment
nCLK
Output Frequency (MHz)
FSEL0
Input
FSEL1
FSEL[1:0]
8
VCC
7
nQ
6
Q
ICS83PN128I
10-Lead VFQFN
5mm x 7mm x 1mm package body
K Package
Top View
Block Diagram
Q
CLK Pulldown
nCLK Pullup/Pulldown
÷P
FemtoClock®
Phase
Detector
VCO
NG
÷N
nQ
÷M
2
FSEL[1:0] Pullup
OE Pullup
ICS83PN128AKI REVISION A MAY 9, 2013
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©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1
OE
2
Reserved
Reserved
3
VEE
Power
4
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. VCC/2 default when left floating
5
CLK
Input
Pulldown
Non-inverting differential clock input.
6, 7
Q, nQ
Output
Differential output pair. LVPECL interface levels.
8
VCC
Power
Power supply pin.
9
FSEL0
Input
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3,
Frequency Select Table.
10
FSEL1
Input
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3,
Frequency Select Table.
Pullup
Output enable. External pullup required for normal operation.
LVCMOS/LVTTL interface levels.
Reserved pin.
Negative supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
3.5
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
Function Table
Table 3. P, M, N Divider Function Table
FSEL[1:0]
P Divider
M Divider
N Divider
Input Frequency (MHz)
Output Frequency (MHz)
00
÷2
26.39872
÷16
156.25
128.90
01
÷2
26.39872
÷16
156.25
128.90
10
÷2
26.39872
÷16
156.25
128.90
1 1 (default)
÷2
33.00
÷16
156.25
161.132813
ICS83PN128AKI REVISION A MAY 9, 2013
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©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
3.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, JA
39.2C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VCC
Power Supply Voltage
IEE
Power Supply Current
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
189
mA
Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VCC
Power Supply Voltage
IEE
Power Supply Current
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
182
mA
Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
OE,
FSEL[1:0]
VCC = VIN = 3.465V or 2.625V
IIL
Input Low Current
OE,
FSEL[1:0]
VCC = 3.465V or 2.625V, VIN = 0V
ICS83PN128AKI REVISION A MAY 9, 2013
Test Conditions
Minimum
VCC = 3.465V
Maximum
Units
2
VCC + 0.3
V
VCC = 2.625V
1.7
VCC + 0.3
V
VCC = 3.465V
-0.3
0.8
V
VCC = 2.625V
-0.3
0.7
V
5
µA
3
-150
Typical
µA
©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Table 4D. Differential DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
IIH
Input High Current CLK, nCLK
IIL
Test Conditions
Minimum
Typical
VCC = VIN = 3.465V or 2.625V
Maximum
Units
150
µA
CLK
VIN = 0V,
VCC = 3.465V or 2.625V
-5
µA
nCLK
VIN = 0V,
VCC = 3.465V or 2.625V
-150
µA
Input Low Current
VPP
Peak-to-Peak Voltage
0.15
1.3
V
VCMR
Common Mode Input Voltage;
NOTE 1
VEE
VCC – 0.85
V
Maximum
Units
NOTE 1: Common mode input voltage is defined at the cross point.
Table 4E. LVPECL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VOH
Output High Voltage; NOTE 1
VCC – 1.4
VCC – 0.8
V
VOL
Output Low Voltage; NOTE 1
VCC – 2.0
VCC – 1.6
V
VSWING
Peak-to-Peak Output Voltage
Swing
0.6
1.0
V
NOTE 1: Outputs termination with 50 to VCC – 2V.
ICS83PN128AKI REVISION A MAY 9, 2013
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©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
AC Electrical Characteristics
Table 6A. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
fMAX
Output Frequency
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
Typical
Maximum
Units
FSEL[1:0] = 00
128.90
MHz
FSEL[1:0] = 11
161.132813
MHz
18
30
ps
128.90MHz,
Integration Range: 12kHz – 20MHz
0.53
ps
161.132813MHz,
Integration Range: 12kHz – 20MHz
0.374
ps
20% to 80%
150
450
ps
49
51
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Please refer to the Phase Noise plots. Measured using low noise input source.
Table 6B. AC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
fMAX
Output Frequency
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
Typical
Maximum
Units
FSEL[1:0] = 00
128.90
MHz
FSEL[1:0] = 11
161.132813
MHz
18
35
ps
128.90MHz,
Integration Range: 12kHz – 20MHz
0.56
ps
161.132813MHz,
Integration Range: 12kHz – 20MHz
0.374
ps
20% to 80%
100
500
ps
49
51
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Please refer to the Phase Noise plots. Measured using low noise input source.
ICS83PN128AKI REVISION A MAY 9, 2013
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©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Typical Phase Noise at 128.90MHz
Noise Power
dBc
Hz
128.90MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.53ps (typical)
Offset Frequency (Hz)
Typical Phase Noise at 161.132813MHz
Noise Power
dBc
Hz
161.132813MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.374ps (typical)
Offset Frequency (Hz)
ICS83PN128AKI REVISION A MAY 9, 2013
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©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Parameter Measurement Information
2V
2V
Q
VCC
SCOPE
VCC
LVPECL
Q
SCOPE
LVPECL
nQ
nQ
VEE
VEE
-1.3V± 0.165V
-0.5V± 0.125V
2.5V LVPECL Output Load AC Test Circuit
3.3V LVPECL Output Load AC Test Circuit
VCC
nQ
Q
nCLK
t PW
V
t
Cross Points
PP
CLK
V
odc =
CMR
PERIOD
t PW
x 100%
t PERIOD
VEE
Output Duty Cycle/Pulse Width/Period
Differential Input Level
Noise Power
Phase Noise Plot
nQ
Q
tcycle n
tcycle n+1
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
Offset Frequency
f1
f2
RMS Phase Jitter =
1
* Area Under Curve Defined by the Offset Frequency Markers
2* *ƒ
RMS Phase Jitter
Cycle-to-Cycle Jitter
ICS83PN128AKI REVISION A MAY 9, 2013
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©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Parameter Measurement Information, continued
nQ
80%
80%
VSW I N G
20%
20%
Q
tR
tF
Output Rise/Fall Time
ICS83PN128AKI REVISION A MAY 9, 2013
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©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Applications Information
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
For the control pins that have internal pullup resistors; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VCC/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1in the center of the input voltage swing. For
example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2
value should be adjusted to set V1 at 1.25V. The values below are for
when both the single ended swing and VCC are at the same voltage.
This configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
impedance. For most 50 applications, R3 and R4 can be 100. The
values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS83PN128AKI REVISION A MAY 9, 2013
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©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
3.3V Differential Clock Input Interface
with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 2A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 2A to 2E show interface examples
for the CLK/nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
R1
50Ω
R1
50Ω
Differential
Input
LVHSTL
IDT
LVHSTL Driver
Differential
Input
LVPECL
nCLK
R2
50Ω
R2
50Ω
R2
50Ω
Figure 2B. CLK/nCLK Input Driven by a 3.3V LVPECL
Driver
Figure 2A. CLK/nCLK Input Driven by an IDT Open
Emitter LVHSTL Driver
3.3V
3.3V
3.3V
3.3V
3.3V
Zo = 50Ω
CLK
CLK
R1
100Ω
nCLK
Zo = 50Ω
Differential
Input
LVPECL
LVDS
Receiver
Figure 2D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
Figure 2C. CLK/nCLK Input Driven by a 3.3V LVPECL
Driver
3.3V
nCLK
3.3V
*R3
CLK
nCLK
HCSL
*R4
Differential
Input
Figure 2E. CLK/nCLK Input Driven by a 3.3V HCSL
Driver
ICS83PN128AKI REVISION A MAY 9, 2013
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©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
2.5V Differential Clock Input Interface
with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 3A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 3A to 3E show interface examples
for the CLK/nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
2.5V
2.5V
2.5V
1.8V
Zo = 50
Zo = 50
CLK
CLK
Zo = 50
Zo = 50
nCLK
nCLK
Differential
Input
LVHSTL
IDT Open Emitter
LVHSTL Driver
R1
50
Differential
Input
LVPECL
R2
50
R1
50
R2
50
R3
18
Figure 3B. CLK/nCLK Input Driven by a
2.5V LVPECL Driver
Figure 3A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
2.5V
2.5V
2.5V
R3
250
2.5V
R4
250
2.5V
Zo = 50
Zo = 50
CLK
CLK
R1
100
Zo = 50
nCLK
Differential
Input
LVPECL
R1
62.5
R2
62.5
Zo = 50
LVDS
nCLK
Differential
Input
Figure 3D. CLK/nCLK Input Driven by a 2.5V LVDS Driver
Figure 3C. CLK/nCLK Input Driven by a
2.5V LVPECL Driver
2.5V
2.5V
2.5V
R5
120Ω
R7
120Ω
Zo = 60Ω
CLK
Zo = 60Ω
nCLK
SSTL
R6
120Ω
R8
120Ω
Differential
Input
Figure 3E. CLK/nCLK Input Driven by a
2.5V SSTL Driver
ICS83PN128AKI REVISION A MAY 9, 2013
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©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 4. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale
ICS83PN128AKI REVISION A MAY 9, 2013
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©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible signals. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
LVPECL
Input
Zo = 50
R1
84
Figure 5A. 3.3V LVPECL Output Termination
ICS83PN128AKI REVISION A MAY 9, 2013
R2
84
Figure 5B. 3.3V LVPECL Output Termination
13
©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Termination for 2.5V LVPECL Outputs
level. The R3 in Figure 5B can be eliminated and the termination is
shown in Figure 6C.
Figure 6A and Figure 6B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
R1
250Ω
50Ω
R3
250Ω
+
50Ω
+
50Ω
–
50Ω
2.5V LVPECL Driver
–
R1
50Ω
2.5V LVPECL Driver
R2
62.5Ω
R2
50Ω
R4
62.5Ω
R3
18Ω
Figure 6A. 2.5V LVPECL Driver Termination Example
Figure 6B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50Ω
R2
50Ω
Figure 6C. 2.5V LVPECL Driver Termination Example
ICS83PN128AKI REVISION A MAY 9, 2013
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©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Schematic Application
Figure 7 shows an example of ICS83PN128I application schematic.
In this example, the device is operated at VCC = 3.3V. As with any
high speed analog circuitry, the power supply pins are vulnerable to
random noise. To achieve optimum jitter performance, power supply
isolation is required. The ICS83PN128I provides separate power
supplies to isolate any high switching noise from coupling into the
internal PLL.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side. The other components can be on the opposite side of the
PCB.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure that the logic control inputs are
properly set.
Logic Control Inp ut Ex amples
S et Log ic
Input to
'1'
VCC
RU1
1K
S et Log ic
Input to
'0'
V CC
3. 3V
RU2
N ot I ns tal l
VCC
F SE L1
FS EL0
C1
RD2
1K
U1
0. 1uF
1
BLM18B B221SN 1
2
C2
Ferri te B ead
C3
0.1uF
10uF
3. 3V
F SE L1
F SEL0
RD1
N ot I ns t al l
To Logic
Input
pins
10
9
To Logic
Input
pins
R1
133
R2
133
Zo = 50 Ohm
OE
1
2
3
OE
R eserv ed
VE E
VC C
nQ
Q
8
7
6
Q
+
Zo = 50 Ohm
-
nC LK
C LK
nQ
4
5
R3
82.5
R4
82. 5
VCC=3.3V
VC C
R5
125
R6
125
Zo = 50 Ohm
+
Zo = 50 Ohm
Z o = 50
C LK
-
nC LK
R7
50
Z o = 50
R9
84
R8
50
R 10
84
LV PE C L D riv er
Optional
Y-Terminat ion
R 11
50
Figure 7. ICS83PN128I Schematic Example
ICS83PN128AKI REVISION A MAY 9, 2013
15
©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS83PN128I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS83PN128I is the sum of the core power plus the power dissipated due to loading.
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 189mA = 654.885mW
•
Power (outputs)MAX = 32mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 654.885mW + 32mW = 686.885mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 39.2°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.687W * 39.2°C/W = 111.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board.
Table 7. Thermal Resistance JA for 10 Lead VFQFN, Forced Convection
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
ICS83PN128AKI REVISION A MAY 9, 2013
0
39.2°C/W
16
©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCC
Q1
VOUT
RL
50Ω
VCC - 2V
Figure 8. LVPECL Driver Circuit and Termination
To calculate power dissipation due to loading, use the following equations which assume a 50 load, and a termination
voltage of VCC – 2V.
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.8V
(VCC_MAX – VOH_MAX) = 0.8V
•
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.6V
(VCC_MAX – VOL_MAX) = 1.6V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.8V)/50] * 0.8V = 19.2mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.6V)/50] * 1.6V = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW
ICS83PN128AKI REVISION A MAY 9, 2013
17
©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Reliability Information
Table 8. JA vs. Air Flow Table for a 10 Lead VFQFN
JA vs. Air Flow
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
39.2°C/W
Transistor Count
The transistor count for ICS83PN128I is: 42,520
Package Dimensions
Table 9. Package Dimensions for 10-Lead VFQFN
Symbol
N
A
A1
b1
b2
D
D2
E
E2
e1
e2
L1
L2
N
ND
NE
aaa
bbb
ccc
VNJR-1
All Dimensions in Millimeters
Minimum
Nominal
10
0.80
0.90
0
0.02
0.35
0.40
1.35
1.40
5.00 Basic
1.55
1.70
7.00 Basic
3.55
3.70
1.0
2.54
0.45
0.55
1.0
1.10
10
2
3
0.15
0.10
0.10
ICS83PN128AKI REVISION A MAY 9, 2013
Maximum
1.00
0.05
0.45
1.45
1.80
3.80
0.65
1.20
18
©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Package Outline
Package Outline - K Suffix for 10-Lead VFQFN
D
e1
A
NX L2
B
0.1mm
0.1mm
→
bbb
C A B
→
4
INDEX AREA
(D/2 xE/2)
7
NX b1
NX b2
7
C A B
e2
aaa C 2x
E2
E
bbb
4
INDEX AREA
(D/2 xE/2)
PIN#1 ID
TOP VIEW
A1
D2
8
BOTTOM VIEW
C
A
ccc C
NX L1
9
aaa C 2x
SEATING
PLANE
SIDE VIEW
0.08 C
Bottom View w/Type A ID
Bottom View w/Type C ID
2
1
2
1
CHAMFER
4
N N-1
RADIUS
4
N N-1
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
ICS83PN128AKI REVISION A MAY 9, 2013
device. The pin count and pin out are shown on the front page. The
package dimensions are in Table 9.
19
©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Ordering Information
Table 10. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
83PN128AKILF
ICS3PN128AIL
“Lead-Free” 10 Lead VFQFN
Tray
-40C to 85C
83PN128AKILFT
ICS3PN128AIL
“Lead-Free” 10Lead VFQFN
Tape & Reel
-40C to 85C
ICS83PN128AKI REVISION A MAY 9, 2013
20
©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
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Copyright 2013. All rights reserved.
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