840002
FEMTOCLOCKS™ Crystal-to-LVCMOS/
LVTTL Frequency Synthesizer
DATASHEET
GENERAL DESCRIPTION
FEATURES
The 840002 is a 2 output LVCMOS/LVTTL Synthesizer optimized
to generate Fibre Channel reference clock frequencies. Using a
26.5625MHz, 18pF parallel resonant crystal, the following frequencies
can be generated based on the 2 frequency select pins (F_SEL1:0):
212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and 53.125MHz.
The 840002 uses low phase noise VCO technology and can achieve
1ps or lower typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The 840002 is packaged in a 16-pin TSSOP package.
• Two LVCMOS outputs @ 3.3V, 17Ω typical output impedance
• Selectable crystal oscillator interface
or LVCMOS single-ended input
• Output frequency range: 46.66MHz - 233.33MHz
• VCO range: 560MHz - 700MHz
• Supports the following output frequencies: 212.5MHz,
159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz
• RMS phase jitter @ 212.5MHz (637kHz - 10MHz):
0.83ps (typical)
Typical phase noise at 212.5MHz:
Offset
Noise Power
100Hz ................-91.3 dBc/Hz
1kHz ..............-114.3 dBc/Hz
10kHz ..............-120.7 dBc/Hz
100kHz ..............-120.2 dBc/Hz
• Full 3.3V or 3.3V core/2.5V output supply modes
• 0°C to 70°C ambient operating temperature
• Available in lead-free RoHS compliant package
FREQUENCY SELECT FUNCTION TABLE FOR FIBRE CHANNEL APPLICATIONS
Inputs
Input Frequency
(MHz)
F_SEL1
F_SEL0
M Divider Value
N Divider Value
M/N Ratio Value
26.5625
0
0
24
3
8
212.5
26.5625
0
1
24
4
6
159.375
26.5625
1
0
24
6
4
106.25
26.5625
1
1
24
12
2
53.125
26.04166
0
1
24
4
6
156.25
BLOCK DIAGRAM
OE
PIN ASSIGNMENT
Pullup
F_SEL0
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
VDD
2
F_SEL1:0 Pullup:Pullup
nPLL_SEL Pulldown
nXTAL_SEL
XTAL_IN
Output Frequency
(MHz)
Pulldown
26.5625MHz
OSC
F_SEL1:0
0
1
00
01
10
11
XTAL_OUT
TEST_CLK Pulldown
1
Phase
Detector
VCO
0
N
÷3
÷4
÷6
÷12 (default)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
F_SEL1
GND
GND
Q0
Q1
VDDO
XTAL_IN
XTAL_OUT
Q0
840002
Q1
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
M = ÷24 (fixed)
MR
Pulldown
840002 REVISION C NOVEMBER 10, 2014
1
©2014 Integrated Device Technology, Inc.
840002 DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
F_SEL0
Type
Input
Description
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
2
nXTAL_SEL
Input
Selects between the crystal or TEST_CLK inputs as the PLL reference
Pulldown source. When HIGH, selects TEST_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
3
TEST_CLK
Input
Pulldown Single-ended LVCMOS/LVTTL clock input.
4
OE
Input
5
MR
Input
6
nPLL_SEL
Input
7
VDDA
Power
Analog supply pin.
8
VDD
Power
Core supply pin.
9,
10
XTAL_OUT,
XTAL_IN
Input
Crystal oscillator interface.
Output enable pin. When HIGH, the outputs are active. When LOW, the
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
Pulldown reset causing active outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output.
When HIGH, the PLL is bypassed and the output frequency = reference
Pulldown
clock frequency/n output divider.
LVCMOS/LVTTL interface levels.
Pullup
11
VDDO
Power
Output supply pin.
12, 13
Q1, Q0
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
14, 15
GND
Power
16
F_SEL1
Input
Power supply ground.
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
8
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
ROUT
Test Conditions
Minimum
Typical
Maximum
4
pF
51
Output Impedance
Units
kΩ
3.3V±5%
14
17
21
Ω
2.5V±5%
16
21
25
Ω
TABLE 3. FREQUENCY SELECT FUNCTION TABLE
Input Frequency
(MHz)
Inputs
M Divider Value N Divider Value
24
3
26.5625
F_SEL1
0
F_SEL0
0
26.5625
0
1
24
26.5625
1
0
26.5625
1
1
26.04166
0
1
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
M/N Divider Value
8
Output Frequency
(MHz)
212.5
4
6
159.375
24
6
4
106.25
24
12
2
53.125
24
4
6
156.25
2
REVISION C 11/10/14
840002 DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA
89°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
Symbol
VDD
Parameter
Core Supply Voltage
VDDA
Analog Supply Voltage
VDDO
Output Supply Voltage
IDD
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
Units
V
3.135
3.3
3.465
V
3.135
3.3
3.465
V
2.375
2.5
2.625
V
Power Supply Current
100
mA
IDDA
Analog Supply Current
12
mA
IDDO
Output Supply Current
5
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
Symbol
VIH
VIL
Parameter
Input
High Voltage
Input
Low Voltage
IIH
Input
High Current
IIL
Input
Low Current
Test Conditions
Minimum
F_SEL1:0, nPLL_SEL,
nXTAL_SEL, OE, MR
TEST_CLK
F_SEL1:0, nPLL_SEL,
nXTAL_SEL, OE, MR
TEST_CLK
OE, F_SEL0, F_SEL1
nPLL_SEL, MR, nXTAL_
SEL, TEST_CLK
OE, F_SEL0, F_SEL1
nPLL_SEL, MR, nXTAL_
SEL, TEST_CLK
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
Typical
Maximum
Units
2
VDD + 0.3
V
2
VDD + 0.3
V
-0.3
0.8
V
-0.3
1.3
V
VDD = VIN = 3.465V
5
µA
VDD = VIN = 3.465V
150
µA
VDD = 3.465V, VIN = 0V
-150
µA
VDD = 3.465V, VIN = 0V
-5
µA
VDDO = 3.3V ± 5%
2.6
V
VDDO = 2.5V ± 5%
1.8
V
VDDO = 3.3V or 2.5V ± 5%
0.5
V
NOTE 1: Outputs terminated with 50W to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Mode of Oscillation
Minimum
Typical
Maximum
Units
Fundamental
Frequency
26.5625
MHz
Ω
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
Drive Level
1
mW
NOTE: Characterized using an 18pf parallel resonant crystal.
REVISION C 11/10/14
3
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
840002 DATA SHEET
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fOUT
Output Frequency Range
tsk(o)
Output Skew; NOTE 1, 3
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
F_SEL[1:0] = 00
186.67
Typical
Maximum
Units
226.67
MHz
F_SEL[1:0] = 01
140
170
MHz
F_SEL[1:0] = 10
93.33
113.33
MHz
F_SEL[1:0] = 11
46.67
56.67
MHz
12
ps
212.5MHz @ Integration Range:
637kHz - 10MHz
159.375MHz @ Integration Range:
637kHz - 10MHz
156.25MHz @ Integration Range:
1.875MHz - 20MHz
106.25MHz @ Integration Range:
637kHz - 10MHz
53.125MHz @ Integration Range:
637kHz - 10MHz
20% to 80%
200
F_SEL[1:0] ¹ 00
46
0.83
ps
0.62
ps
0.59
ps
0.80
ps
0.68
ps
700
F_SEL[1:0] = 00
42
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
ps
54
%
58
%
Maximum
Units
226.67
MHz
TABLE 6B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fOUT
Output Frequency Range
tsk(o)
Output Skew; NOTE 1, 3
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
F_SEL[1:0] = 00
186.67
Typical
F_SEL[1:0] = 01
140
170
MHz
F_SEL[1:0] = 10
93.33
113.33
MHz
F_SEL[1:0] = 11
46.67
56.67
MHz
12
ps
212.5MHz @ Integration Range:
637kHz - 10MHz
159.375MHz @ Integration Range:
637kHz - 10MHz
156.25MHz @ Integration Range:
1.875MHz - 20MHz
106.25MHz @ Integration Range:
637kHz - 10MHz
53.125MHz @ Integration Range:
637kHz - 10MHz
20% to 80%
200
F_SEL[1:0] ¹ 00
46
0.73
ps
0.62
ps
0.56
ps
0.76
ps
0.72
ps
F_SEL[1:0] = 00
42
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
4
700
ps
54
%
58
%
REVISION C 11/10/14
840002 DATA SHEET
TYPICAL PHASE NOISE AT 53.125MHZ @3.3V
➤
0
-10
-20
Fibre Channel Filter
-30
-40
53.125MHz
NOISE POWER dBc
Hz
-50
RMS Phase Jitter (Random)
637KHz to 10MHz = 0.68ps (typical)
-60
-70
-80
-90
-100
Raw Phase Noise Data
-110
-120
➤
-130
-140
-150
➤
-160
-170
Phase Noise Result by adding
Fibre Channel Filter to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 212.5MHZ @3.3V
➤
0
-10
-20
Fibre Channel Filter
-30
-40
212.5MHz
RMS Phase Jitter (Random)
637KHz to 10MHz = 0.83ps (typical)
-60
-70
-80
-90
Raw Phase Noise Data
-100
➤
NOISE POWER dBc
Hz
-50
-110
-120
-130
-140
➤
-150
-160
-170
Phase Noise Result by adding
Fibre Channel to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
REVISION C 11/10/14
5
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
840002 DATA SHEET
PARAMETER MEASUREMENT INFORMATION
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
OUTPUT SKEW
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
6
REVISION C 11/10/14
840002 DATA SHEET
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 840002 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and
VDDO should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VDDA.
3.3V
VDD
.01μF
10Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The 840002 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
determined using a 26.5625MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Cry stal
XTAL_OUT
C2
22p
ICS84332
840002
Figure 2. CRYSTAL INPUt INTERFACE
REVISION C 11/10/14
7
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
840002 DATA SHEET
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating. Though
not required, but for additional protection, a 1kΩ resistor can be
tied from XTAL_IN to ground.
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the TEST_CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
LAYOUT GUIDELINE
Figure 3 shows a schematic example of the 840002. An example
of LVCMOS termination is shown in this schematic. Additional
LVCMOS termination approaches are shown in the LVCMOS
Termination Application Note. In this example, an 18 pF parallel resonant 26.5625MHz crystal is used. The C1=22pF and
C2=22pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy. 1KΩ pullup or pulldown resistors
can be used for the logic control input pins.
Logic Control Input Examples
Set Logic
Input to
'1'
VDD
RU1
1K
Set Logic
Input to
'0'
VDD
R2
33
RU2
Not Install
To Logic
Input
pins
To Logic
Input
pins
U1
RD2
1K
RD1
Not Install
VDD
1
2
3
4
5
6
7
8
VDDA
R1
10
C3
10uF
Zo = 50 Ohm
VDD
C4
0.01u
LVCMOS
FSEL0
XTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
VDD
FSEL1
GND
GND
Q0
Q1
VDDO
XTAL_IN
XTAL_OUT
16
15
14
13
12
11
10
9
VDD
R3
100
C6
0.1u
Zo = 50 Ohm
C5
0.1u
ICS840002
R4
100
XTAL2
If not using the crystal input, it can be left floating.
For additional protection the XTAL_IN pin can be
tied to ground.
LVCMOS
C2
22pF
X1
XTAL1
Optional Termination
C1
22pF
Unused output can be left floating. There should
no trace attached to unused output. Device
characterized with all outputs terminated.
FIGURE 3. 840002 SCHEMATIC EXAMPLE
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
8
REVISION C 11/10/14
840002 DATA SHEET
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
137.1°C/W
89.0°C/W
118.2°C/W
81.8°C/W
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for 840002 is: 3085
REVISION C 11/10/14
9
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
840002 DATA SHEET
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
N
Maximum
16
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
5.10
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
10
REVISION C 11/10/14
840002 DATA SHEET
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS840002AGLF
840002AL
16 Lead “Lead-Free” TSSOP
tube
0°C to 70°C
ICS840002AGLFT
840002AL
16 Lead “Lead-Free” TSSOP
tape & reel
0°C to 70°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
REVISION C 11/10/14
11
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
840002 DATA SHEET
REVISION HISTORY SHEET
Rev
Table
Page
T5
T9
3
6
8
11
B
C
T9
11
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
Description of Change
Crystal Characteristics Table - added Drive Level.
Updated Output Load AC Test Circuit diagrams.
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - corrected standard marking and added lead-free
marking and note.
Ordering information - removed leaded devices - PDN CQ-13-02 expired.
Updated Datasheet format.
12
Date
2/17/06
11/10/14
REVISION C 11/10/14
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, California 95138
Sales
800-345-7015 or +408-284-8200
Fax: 408-284-2775
www.IDT.com
Technical Support
email: clocks@idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others.
This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or
their respective third party owners.
Copyright 2014. All rights reserved.
IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar 2020)
Corporate Headquarters
Contact Information
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
For further information on a product, technology, the most
up-to-date version of a document, or your nearest sales
office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.
© 2020 Renesas Electronics Corporation. All rights reserved.
