840004
FemtoClocks™ Crystal-to-LVCMOS/
LVTTL Frequency Synthesizer
DATASHEET
GENERAL DESCRIPTION
FEATURES
The 840004 is a 4 output LVCMOS/LVTTL Synthesizer optimized
to generate Ethernet reference clock frequencies and is a member
of the HiPerClocksTM family of high performance clock solutions
from IDT. Using a 26.5625MHz, 18pF parallel resonant crystal, the
following frequencies can be generated based on the 2 frequency
select pins (F_SEL1:0): 212.5MHz, 159.375MHz, 156.25MHz,
106.25MHz, and 53.125MHz. The 840004 uses IDT’s 3rd generation
low phase noise VCO technology and can achieve 1ps or lower
typical random rms phase jitter, easily meeting Ethernet jitter
requirements. The 840004 is packaged in a small 20-pin TSSOP
package.
• Four LVCMOS/LVTTL outputs, 17Ω typical output impedance
• Selectable crystal oscillator interface
or LVCMOS single-ended input
• Supports the following input frequencies: 212.5MHz,
159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz
• VCO range: 560MHz - 700MHz
• RMS phase jitter @ 212.5MHz (637kHz - 10MHz):
0.49ps typical, VDDO = 3.3V
Phase noise:
Offset
Noise Power
100Hz ................-88.8 dBc/Hz
1kHz ..............-109.0 dBc/Hz
10kHz ..............-116.1 dBc/Hz
100kHz ..............-117.5 dBc/Hz
• Full 3.3V or mixed 3.3V core/2.5V output supply mode
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
FREQUENCY SELECT FUNCTION TABLE
Inputs
Output Frequency
Range (MHz)
Input Frequency
(MHz)
F_SEL1
F_SEL0
M Divider
Value
N Divider
Value
M/N Ratio
Value
26.5625
0
0
24
3
8
212.5
26.5625
0
1
24
4
6
159.375
26.5625
1
0
24
6
4
106.25
26.5625
1
1
24
12
2
53.125 (default)
26.04166
0
1
24
4
6
156.25
BLOCK DIAGRAM
OE
PIN ASSIGNMENT
Pullup
2
F_SEL1:0 Pullup:Pullup
nPLL_SEL Pulldown
nXTAL_SEL
XTAL_IN
Pulldown
26.5625MHz
OSC
F_SEL1:0
0
1
XTAL_OUT
REF_CLK Pulldown
1
Phase
Detector
VCO
0
00
01
10
11
N
÷3
÷4
÷6
÷12 (default)
Q0
Q1
MR
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
F_SEL1
GND
Q0
Q1
VDDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
840004
20-Lead TSSOP
Q2
M = ÷24 (fixed)
F_SEL0
nc
nXTAL_SEL
REF_CLK
OE
MR
nPLL_SEL
VDDA
nc
VDD
Q3
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
Pulldown
840004 REVISION B 4/1/15
1
©2015 Integrated Device Technology, Inc.
840004 DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
F_SEL0
Input
Type
2, 9
nc
Unused
3
nXTAL_SEL
Input
Selects between the crystal or REF_CLK inputs as the PLL reference
Pulldown source. When HIGH, selects REF_CLK. When LOW, selects XTAL inputs.
LVCMOS/LVTTL interface levels.
4
REF_CLK
Input
Pulldown Single-ended LVCMOS/LVTTL reference clock input.
5
OE
Input
6
MR
Input
7
nPLL_SEL
Input
8
VDDA
Power
Analog supply pin.
10
VDD
Power
Core supply pin.
11,
12
XTAL_OUT,
XTAL_IN
Input
Crystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Pullup
Description
Frequency select pin. LVCMOS/LVTTL interface levels.
No connect.
Output enable pin. When HIGH, the outputs are active. When LOW, the
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
Pulldown reset causing the otuputs to go low. When logic LOW, the internal dividers
and the outputs are enabled. LVCMOS/LVTTL interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output.
When HIGH, the PLL is bypassed and the output frequency = reference
Pulldown
clock frequency/N output divider.
LVCMOS/LVTTL interface levels.
Pullup
13, 19
GND
Power
Power supply ground.
14, 15 17,
18
Q3, Q2,
Q1, Q0
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
17Ω typical output impedance.
16
VDDO
Power
Output supply pin.
20
F_SEL1
Input
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
8
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
ROUT
Output Impedance
VDDO = 3.3V±5%
17
Ω
VDDO = 2.5V±5%
21
Ω
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/
LVTTL FREQUENCY SYNTHESIZER
Test Conditions
Minimum
Typical
4
2
Maximum
Units
pF
REVISION B 4/1/15
840004 DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA
73.2°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
Symbol
VDD
Parameter
Core Supply Voltage
VDDA
Analog Supply Voltage
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
Units
V
3.135
3.3
3.465
V
3.135
3.3
3.465
V
2.375
2.5
VDDO
Output Supply Voltage
2.625
V
IDD
Power Supply Current
100
mA
IDDA
Analog Supply Current
12
mA
IDDO
Output Supply Current
10
mA
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
VIH
Input High Voltage
VIL
Input Low Voltage
OE, F_SEL0, F_SEL1,
nPLL_SEL, MR, nXTAL_
SEL, REF_CLK
OE, F_SEL0, F_SEL1,
nPLL_SEL, MR, nXTAL_
SEL, REF_CLK
IIH
Input
High Current
IIL
Input
Low Current
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
Minimum
Typical
Maximum
Units
2
VDD + 0.3
V
-0.3
0.8
V
VDD = VIN = 3.465V
5
µA
VDD = VIN = 3.465V
150
µA
VDD = 3.465V, VIN = 0V
-150
µA
VDD = 3.465V, VIN = 0V
-5
µA
VDDO = 3.3V ± 5%
2.6
V
VDDO = 2.5V ± 5%
1.8
V
VDDO = 3.3V or 2.5V ± 5%
0.5
V
NOTE 1: Outputs terminated with 50W to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Maximum
Units
29.16
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
Mode of Oscillation
Typical
Fundamental
Frequency
23.3
26.5625
NOTE: Characterized using an 18pF parallel resonant crystal.
REVISION B 4/1/15
3
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/
LVTTL FREQUENCY SYNTHESIZER
840004 DATA SHEET
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
fOUT
tsk(o)
tjit(Ø)
Parameter
Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
F_SEL[1:0] = 00
186.67
212.5
226.66
MHz
F_SEL[1:0] = 01
140
159.375
170
MHz
F_SEL[1:0] = 10
93.33
156.25
113.33
MHz
F_SEL[1:0] = 11
46.67
106.25
56.66
MHz
60
ps
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
212.5MHz (637kHz - 10MHz)
0.49
ps
159.375MHz (637kHz - 10MHz)
0.55
ps
156.25MHz (1.875MHz - 20MHz)
0.56
ps
106.25MHz (637kHz - 10MHz)
0.79
ps
53.125MHz (637kHz - 10MHz)
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
0.65
ps
20% to 80%
200
700
ps
F_SEL[1:0] = 00
41
59
%
F_SEL[1:0] = 01
43
57
%
52
%
Typical
Maximum
Units
F_SEL[1:0] = 10 or 11
48
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
Symbol
fOUT
tsk(o)
tjit(Ø)
Parameter
Output Frequency
Test Conditions
Minimum
F_SEL[1:0] = 00
186.67
212.5
226.66
MHz
F_SEL[1:0] = 01
140
159.375
170
MHz
F_SEL[1:0] = 10
93.33
156.25
113.33
MHz
F_SEL[1:0] = 11
46.67
106.25
56.66
MHz
60
ps
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
212.5MHz (637kHz - 10MHz)
0.46
ps
159.375MHz (637kHz - 10MHz)
0.54
ps
156.25MHz (1.875MHz - 20MHz)
0.57
ps
106.25MHz (637kHz - 10MHz)
0.73
ps
53.125MHz (637kHz - 10MHz)
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
0.63
200
700
ps
F_SEL[1:0] = 00
42
58
%
F_SEL[1:0] = 01
44
56
%
52
%
F_SEL[1:0] = 10 or 11
48
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/
LVTTL FREQUENCY SYNTHESIZER
ps
20% to 80%
4
REVISION B 4/1/15
840004 DATA SHEET
TYPICAL PHASE NOISE AT 53.125MHZ @3.3V
0
➤
-10
-20
Fibre Channel Filter
-30
-40
53.125MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.65ps (typical)
-60
-70
-80
-90
Raw Phase Noise Data
-100
➤
NOISE POWER dBc
Hz
-50
-110
-120
-130
-140
-150
-160
➤
-170
-180
-190
10
100
1k
10k
Phase Noise Result by adding
Fibre Channel Filter to raw data
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 106.25MHZ @3.3V
➤
0
-10
-20
Fibre Channel Filter
-40
106.25MHz
-50
-60
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.79ps (typical)
-70
-80
-90
Raw Phase Noise Data
-100
➤
NOISE POWER dBc
Hz
-30
-110
-120
-130
-140
-150
-160
-170
Phase Noise Result by adding
Fibre Channel Filter to raw data
➤
-180
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
REVISION B 4/1/15
5
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/
LVTTL FREQUENCY SYNTHESIZER
840004 DATA SHEET
TYPICAL PHASE NOISE AT 159.375MHZ @3.3V
0
➤
-10
-20
Fibre Channel Filter
-30
159.375MHz
-50
-60
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.55ps (typical)
-70
-80
Raw Phase Noise Data
-90
-100
➤
NOISE POWER dBc
Hz
-40
-110
-120
-130
-140
-150
-160
➤
-170
-180
-190
10
100
1k
Phase Noise Result by adding
Fibre Channel Filter to raw data
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 212.5MHZ@ 3.3V
➤
0
-10
-20
Fibre Channel Filter
-40
212.5MHz
-50
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.49ps (typical)
-60
-70
-80
Raw Phase Noise Data
-90
➤
NOISE POWER dBc
Hz
-30
-100
-110
-120
-130
-140
-150
-160
➤
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/
LVTTL FREQUENCY SYNTHESIZER
6
REVISION B 4/1/15
840004 DATA SHEET
PARAMETER MEASUREMENT INFORMATION
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
OUTPUT SKEW
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
REVISION B 4/1/15
7
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/
LVTTL FREQUENCY SYNTHESIZER
840004 DATA SHEET
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 840004 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V DD, V DDA, and
V DDO should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VDDA.
3.3V
VDD
.01μF
10Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The 840004 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
determined using a 26.5625MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Cry stal
XTAL_OUT
C2
22p
ICS84332
Figure 2. CRYSTAL INPUt INTERFACE
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/
LVTTL FREQUENCY SYNTHESIZER
8
REVISION B 4/1/15
840004 DATA SHEET
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface diagram
is shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50Ω applications,
R1 and R2 can be 100Ω. This can also be accomplished by
removing R1 and making R2 50Ω.
VDD
VDD
R1
Ro
.1uf
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
Figure 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We recommend that
there is no trace attached.
REF_CLK INPUT:
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
REVISION B 4/1/15
9
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/
LVTTL FREQUENCY SYNTHESIZER
840004 DATA SHEET
LAYOUT GUIDELINE
are recommended for frequency accuracy. For different board layout,
the C1 and C2 may be slightly adjusted for optimizing frequency
accuracy. 1kΩ pullup or pulldown resistors can be used for the logic
control input pins.
Figure 4 shows a schematic example of the 840004. An example
of LVCMOS termination is shown in this schematic. Additional
LVCMOS termination approaches are shown in the LVCMOS
Termination Application Note. In this example, an 18pF parallel
resonant 26.5625MHz crystal is used. The C1=22pF and C2=22pF
Logic Control Input Examples
Set Logic
Input to
'1'
VDD
Set Logic
Input to
'0'
VDD
RU1
1K
VDD=3.3V
VDDO=3.3V
RU2
Not Install
To Logic
Input
pins
R3
36
RD1
Not Install
RD2
1K
U1
VDDO
1
2
3
4
5
6
7
8
9
10
VDD
VDD
VDDA
R2
10
Zo = 50 Ohm
To Logic
Input
pins
C3
10uF
VDD
C4
0.01u
F_SEL0
nc
nXTAL_SEL
REF_CLK
OE
MR
nPLL_SEL
VDDA
nc
VDD
F_SEL1
GND
Q0
Q1
VDDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
LVCMOS
20
19
18
17
16
15
14
13
12
11
C6
0.1u
VDD
R5
100
Zo = 50 Ohm
C5
0.1u
ICS840004
R4
100
XTAL_OUT
C2
22pF
LVCMOS
X1
XTAL_IN
Optional Termination
C1
22pF
If not using the crystal input, it can be left
floating. For additional protection the XTAL_IN
pin can be tied to ground.
Unused outputs can be left floating. There should be
no trace attached to unused outputs. Device
characterized and specification limits set with all
outputs terminated.
FIGURE 4. 840004 SCHEMATIC EXAMPLE
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/
LVTTL FREQUENCY SYNTHESIZER
10
REVISION B 4/1/15
840004 DATA SHEET
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for 840004 is: 3796
REVISION B 4/1/15
11
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/
LVTTL FREQUENCY SYNTHESIZER
840004 DATA SHEET
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
N
MAX
20
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
6.60
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/
LVTTL FREQUENCY SYNTHESIZER
12
REVISION B 4/1/15
840004 DATA SHEET
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS840004AGLF
ICS840004AGL
20 Lead “Lead-Free” TSSOP
tube
0°C to 70°C
ICS840004AGLFT
ICS840004AGL
20 Lead “Lead-Free” TSSOP
tape & reel
0°C to 70°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
REVISION B 4/1/15
13
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/
LVTTL FREQUENCY SYNTHESIZER
840004 DATA SHEET
REVISION HISTORY SHEET
Rev
Table
Page
B
T4
3
Crystal Table - added Frequency min/max values.
8/16/06
13
Ordering Information - removed leaded devices.
Updated data sheet format.
4/2/15
B
T8
Description of Change
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/
LVTTL FREQUENCY SYNTHESIZER
14
Date
REVISION B 4/1/15
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, California 95138
Sales
800-345-7015 or +408-284-8200
Fax: 408-284-2775
www.IDT.com
Technical Support
email: clocks@idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others.
This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
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