840011AGLNT

FemtoClock® Crystal-to-LVCMOS/ LVTTL Clock Generator 840011 PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 DATA SHEET GENERAL DESCRIPTION FEATURES The 840011 is a Fibre Channel Clock Generator and a member of the family of high performance devices from IDT. The 840011 uses a 26.5625MHz or 25MHz crystal to syn-thesize 106.25MHz or 100MHz respectively. The 840011 has excellent phase jitter performance, from 637kHz – 10MHz integration range. The 840011 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • One LVCMOS/LVTTL output, 7Ω output impedence • Crystal oscillator interface designed for 26.5625MHz or 25MHz, 18pF parallel resonant crystal • Output frequency: 106.25MHz (typical) • VCO range: 560MHz to 680MHz • RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal (637KHz - 10MHz): 0.780ps (typical) • RMS phase noise at 125MHz: Offset Noise Power 100Hz ................-95.7 dBc/Hz 1kHz .................-121 dBc/Hz 10kHz .................-129 dBc/Hz 100kHz ..............-129.6 dBc/Hz • 3.3V operating supply • -30°C to 85°C ambient operating temperature • Available in lead-free (RoHS 6) package • Not Recommended for New Designs • For drop in replacement part use 840N011i FREQUENCY TABLE Inputs Crystal Frequency (MHz) Output Frequency (MHz) 26.5625 106.25 25 100 BLOCK DIAGRAM PIN ASSIGNMENT OE (Pullup) XTAL_IN OSC XTAL_OUT Phase Detector VCO 637.5MHz w/ 26.5625MHz Ref. Q0 ÷6 VDDA OE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VDD Q0 GND nc 840011 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View M = ÷24 (fixed) 840011 REVISION A 5/20/16 1 ©2016 Integrated Device Technology, Inc. 840011 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 VDDA Power 2 OE Input 3, 4 XTAL_OUT, XTAL_IN Input 5 nc Unused 6 GND Power Power supply ground. 7 Q0 Output Single-ended clock output. LVCMOS/LVTTL interface levels. 7Ω output impedance. 8 VDD Power Core supply pin. Analog supply pin. Pullup Output enable pin. When HIGH, Q0 output is enabled. When LOW, forces Q0 to HiZ state. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. No connect. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions CIN Input Capacitance CPD Power Dissipation Capacitance RPULLUP Input Pullup Resistor ROUT Output Impedance Minimum VDD, VDDA = 3.465V Typical Maximum 4 pF 24 pF 51 5 7 kΩ 12 TABLE 3. CONTROL FUNCTION TABLE Control Inputs Output OE Q0 0 Hi-Z 1 Active REVISION A 5/20/16 2 Units FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/ LVTTL CLOCK GENERATOR Ω 840011 DATA SHEET ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -30°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 80 mA IDDA Analog Supply Current 10 mA Maximum Units 2 VDD + 0.3 V -0.3 0.8 V 5 µA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -30°C TO 85°C Symbol Parameter VIH Input High Voltage Test Conditions VIL Input Low Voltage IIH Input High Current OE VDD = VIN = 3.465V IIL Input Low Current OE VDD = 3.465V, VIN = 0V VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 Minimum Typical -150 µA 2.6 V 0.5 V Maximum Units NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section, “3.3V Output Load Test Circuit”. TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental Frequency 26.5625 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF TABLE 6. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -30°C TO 85°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter (Random); NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle All parameters are characterized @ 106.25MHz. NOTE 1: Please refer to the Phase Noise Plot. REVISION A 5/20/16 Test Conditions Minimum Typical Maximum Units 93.33 106.25 113.33 MHz fOUT = 106.25MHz, (637kHz to 10MHz) 0.780 ps 20% to 80% 250 600 ps fOUT = 106.25MHz 48 52 % 3 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/ LVTTL CLOCK GENERATOR 840011 DATA SHEET TYPICAL PHASE NOISE AT 106.25MHZ ➤ 0 -10 Fibre Channel Filter -20 -30 106.25MHz -40 RMS Phase Jitter (Random) 637K to 10MHz = 0.780ps (typical) -50 NOISE POWER dBc Hz -60 -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ -120 -130 -140 -150 ➤ -160 -170 -180 Phase Noise Result by adding Fibre Channel Filter to raw data -190 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (HZ) REVISION A 5/20/16 4 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/ LVTTL CLOCK GENERATOR 100M 840011 DATA SHEET PARAMETER MEASUREMENT INFORMATION 3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD LVCMOS OUTPUT RISE/FALL TIME REVISION A 5/20/16 5 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/ LVTTL CLOCK GENERATOR 840011 DATA SHEET APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 840011 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01μF VDDA .01μF 10Ω 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The 840011 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 26.5625MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. FIGURE 2. CRYSTAL INPUt INTERFACE REVISION A 5/20/16 6 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/ LVTTL CLOCK GENERATOR 840011 DATA SHEET LVCMOS TO XTAL INTERFACE The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. VDD VDD R1 Ro Rs .1uf Zo = 50 Zo = Ro + Rs XTAL_IN R2 XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE REVISION A 5/20/16 7 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/ LVTTL CLOCK GENERATOR 840011 DATA SHEET APPLICATION SCHEMATIC Figure 4A shows a schematic example of the 840011. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18pF parallel resonant VDD VDDA R2 10 C3 10uF C4 0.1u OE C2 33pF 26.5625MHz crystal is used for generating 106.25MHz output frequency. The C1 = 27pF and C2pF = 33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy. U1 1 2 3 4 VDD Q0 GND NC VDDA OE XTAL_OUT XTAL_IN X1 R3 43 VDD Q C5 0.1u ICS840011 C1 27pF 8 7 6 5 Zo = 50 Ohm LVCMOS VDD=3.3V FIGURE 4A. 840011 SCHEMATIC EXAMPLE PC BOARD LAYOUT EXAMPLE Figure 4B shows an example of 840011 P.C. board layout. The crystal X1 footprint in this example allows either surface mount (HC49S) or through hole (HC49) package. C3 is 0805. C1 and C2 are 0402. Other resistors and capacitors are 0603. This layout assumes that the board has clean analog power and ground planes. FIGURE 4B. 840011 PC BOARD LAYOUT EXAMPLE REVISION A 5/20/16 8 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/ LVTTL CLOCK GENERATOR 840011 DATA SHEET RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for 840011 is: 1521 REVISION A 5/20/16 9 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/ LVTTL CLOCK GENERATOR 840011 DATA SHEET PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 E E1 3.10 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 REVISION A 5/20/16 10 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/ LVTTL CLOCK GENERATOR 840011 DATA SHEET TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS840011AGLN 011AN 8 lead “Lead Free Annealed” TSSOP tube -30°C to 85°C ICS840011AGLNT 011AN 8 lead “Lead Free Annealed” TSSOP tape & reel -30°C to 85°C NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. REVISION A 5/20/16 11 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/ LVTTL CLOCK GENERATOR 840011 DATA SHEET REVISION HISTORY SHEET Rev Table Page A T9 10 Ordering Information Table - corrected count from 154 per tube to 100. T9 7 11 T9 11 Added LVCMOS to XTAL Interface, Ordering Information Table - deleted quantity from tube count. Updated datasheet format. Ordering Information Table - removed leaded devices. Updated data sheet format. Product Discontinuation Notice - Last time buy expires May 6, 2017. PDN CQ-16-01 A A A REVISION A 5/20/16 Description of Change 12 Date 10/15/04 1/22/07 9/1/15 5/20/16 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/ LVTTL CLOCK GENERATOR Corporate Headquarters 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2016. All rights reserved.