840021AGLF

ICS840021 FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR General Description Features The ICS840021 is a Gigabit Ethernet Clock Generator and a member of the HiPerClocksTM HiPerClockS™ family of high performance devices from IDT. The ICS840021 uses a 25MHz crystal to synthesize 125MHz. The ICS840021 has excellent phase jitter performance, over the 1.875MHz – 20MHz integration range. The ICS840021 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • • One LVCMOS/LVTTL output, 7Ω output impedance • • • Output frequency: 125MHz • • RMS phase noise at 125MHz (typical) ICS Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal VCO range: 560MHz to 680MHz RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.34ps (typical) 3.3V Phase noise: Offset Noise Power 100Hz ................-96.9 dBc/Hz 1kHz ..............-122.2 dBc/Hz 10kHz ..............-131.1 dBc/Hz 100Hz ..............-129.5 dBc/Hz • • • Pullup XTAL_IN 25MHz OSC XTAL_OUT 0°C to 70°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment Block Diagram OE 3.3V operating supply Phase Detector VCO ÷5 Q0 VDDA OE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VDD Q0 GND RESERVED ICS840021 ÷25 (fixed) IDT™ / ICS™ LVCMOS CLOCK GENERATOR 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View 1 ICS840021AG REV. B APRIL 28, 2009 ICS840021 FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Table 1. Pin Descriptions Number Name Type Description 1 VDDA Power 2 OE Input 3, 4 XTAL_OUT, XTAL_IN Input 5 Reserved Reserved 6 GND Power Power supply ground. 7 Q0 Output Single-ended clock output. LVCMOS/LVTTL interface levels. 7Ω output impedance. 8 VDD Power Core supply pin. Analog supply pin. Pullup Output enable pin. When HIGH, Q0 output is enabled. When LOW, forces Q0 to high-impedance state. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Reserve pin. NOTE: Pullup refers to internal input resistors. See Table 1, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance CPD Power Dissipation Capacitance RPULLUP Input Pullup Resistor ROUT Output Impedance Minimum VDD = 3.465V 5 Typical Maximum Units 4 pF 24 pF 51 kΩ 7 12 Ω Function Table Table 3. Control Function Table Control Input Output OE Q0 0 High-Impedance 1 Active IDT™ / ICS™ LVCMOS CLOCK GENERATOR 2 ICS840021AG REV. B APRIL 28, 2009 ICS840021 FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 75 mA IDDA Analog Supply Current 15 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 2 VDD+0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current VDD = VIN = 3.465V 5 µA IIL Input Low Current VDD =3.465V, VIN = 0V VOH Output High Voltage; NOTE 1 VOL Output High Voltage; NOTE 1 -150 µA 2.6 V 0.5 V NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section, "3.3V Output Load Test Circuit" diagram. IDT™ / ICS™ LVCMOS CLOCK GENERATOR 3 ICS840021AG REV. B APRIL 28, 2009 ICS840021 FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Table 5. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW AC Electrical Characteristics Table 6. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter, Random; NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Integration Range: 1.875MHz – 20MHz 20% to 80% Typical Maximum Units 125 MHz 0.34 ps 250 550 ps 48 52 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Please refer to Phase Noise Plots. IDT™ / ICS™ LVCMOS CLOCK GENERATOR 4 ICS840021AG REV. B APRIL 28, 2009 ICS840021 FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Typical Phase Noise at 125MHz 10 Gb Ethernet Filter ← Noise Power dBc Hz ← 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.34ps (typical) Raw Phase Noise Data ← Phase Noise Result by adding a 10 Gb Ethernet filter to raw data Offset Frequency (Hz) IDT™ / ICS™ LVCMOS CLOCK GENERATOR 5 ICS840021AG REV. B APRIL 28, 2009 ICS840021 FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Parameter Measurement Information 1.65V ¬± 5 Noise Power Phase Noise Plot SCOPE VDD, VDDA Qx LVCMOS Phase Noise Mask GND f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot -1.65V ¬± 5 3.3V Output Load AC Test Circuit RMS Phase Jitter V DD 2 Q0 t PW t 80% tR tF PERIOD Q0 odc = 80% t PW 20% 20% x 100% t PERIOD Output Duty Cycle/Pulse Width/Period IDT™ / ICS™ LVCMOS CLOCK GENERATOR Output Rise/Fall Time 6 ICS840021AG REV. B APRIL 28, 2009 ICS840021 FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS840021provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF 10Ω .01µF 10µF VDDA Figure 1. Power Supply Filtering Crystal Input Interface The ICS840021 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 33p X1 18pF Parallel Crystal XTAL_OUT C2 22p Figure 2. Crystal Input Interface IDT™ / ICS™ LVCMOS CLOCK GENERATOR 7 ICS840021AG REV. B APRIL 28, 2009 ICS840021 FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. VDD R1 Ro Rs 0.1µf 50Ω XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface IDT™ / ICS™ LVCMOS CLOCK GENERATOR 8 ICS840021AG REV. B APRIL 28, 2009 ICS840021 FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Application Schematic Figure 4A shows a schematic example of the ICS840021. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18pF parallel resonant 25MHz crystal is used for generating 125MHz VDD VDDA R2 10 C3 C4 10uF 0.1u U1 1 2 3 4 OE C2 33pF output frequency. The C1 = 27pF and C2 = 33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy. VDDA OE XTAL_OUT XTAL_IN VDD Q0 GND Reserv ed 8 7 6 5 X1 Zo = 50 Ohm C5 0.1u ICS840021i C1 22pF R3 43 VDD Q LVCMOS VDD=3.3V Figure 4A. ICS840021 Schematic Example PC BOARD LAYOUT EXAMPLE Figure 4B shows an example of ICS840021 P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed in the Table 7. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane. Table 7. Footprint Table Reference Size C1, C2 0402 C3 0805 C4, C5 0603 R2, R3 0603 NOTE: Table 7, lists component sizes shown in this layout example. Figure 4B. ICS840021 PC Board Layout Example IDT™ / ICS™ LVCMOS CLOCK GENERATOR 9 ICS840021AG REV. B APRIL 28, 2009 ICS840021 FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Reliability Information Table 8. θJA vs. Air Flow Table for a 8 Lead TSSOP θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W Transistor Count The transistor count for ICS840021 is: 1961 IDT™ / ICS™ LVCMOS CLOCK GENERATOR 10 ICS840021AG REV. B APRIL 28, 2009 ICS840021 FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Package Outline and Package Dimensions Package Outline - G Suffix for 8 Lead TSSOP Table 9. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT™ / ICS™ LVCMOS CLOCK GENERATOR 11 ICS840021AG REV. B APRIL 28, 2009 ICS840021 FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Ordering Information Table 10. Ordering Information Part/Order Number 840021AG 840021AGT 840021AGLF 840021AGLFT Marking 021AG 021AG 021AL 021AL Package 8 Lead TSSOP 8 Lead TSSOP “Lead-Free” 8 Lead TSSOP “Lead-Free” 8 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ LVCMOS CLOCK GENERATOR 12 ICS840021AG REV. B APRIL 28, 2009 ICS840021 FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Revision History Sheet Rev Table Page A T10 10 Ordering Information Table - correct count from 154 to 100. 10/14/04 T8 3 8 Absolute Maximum Ratings - corrected Package Thermal Impedance air flow. Corrected air flow in table. 11/30/04 T10 1 10 Features section - added Lead-free bullet. Ordering Information Table - added lead-free part number and marking. 10/7/05 8 Added LVCMOS to XTAL Interface section. Changed formatting throughout data sheet. 1/10/09 1 2 Pin Assignment - changed pin 5 from nc to Reserved. Pin Description Table - changed pin 5 from nc to Reserved. 4/15/09 A A A B T1 Description of Change IDT™ / ICS™ LVCMOS CLOCK GENERATOR Date 13 ICS840021AG REV. B APRIL 28, 2009 ICS840021 FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Contact Information: www.IDT.com www.IDT.com Sales Technical Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contact IDT netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA