Crystal-to-HCSL Clock Synthesizer
w/Spread Spectrum
ICS841202-245
DATA SHEET
General Description
Features
The ICS841202-245 is a two output clock synthesizer optimized to
generate low jitter with or without spread spectrum modulation.
Spread type and amount can be configured via the SSC control pins.
Using a 25MHz, 12pF parallel resonant crystal, the device will
generate HCSL clocks at either 25MHz, 100MHz, 125MHz or
250MHz. The ICS841202-245 uses a low jitter VCO and is packaged
in a 32-pin VFQFN package.
•
Two differential HCSL output pairs at: 100MHz, 125MHz or
250MHz
•
HCSL outputs can be terminated to drive LVDS loads up to
175MHz
•
•
25MHz crystal interface
•
•
•
•
•
•
Supports SSC downspread, centerspread and no spread options
Supports the following output frequencies: 25MHz, 100MHz,
125MHz or 250MHz
Cycle-to-cycle jitter: 55ps (maximum)
Period jitter, RMS: 4.15ps (maximum)
Full 3.3V operating supply mode
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) packaging
Block Diagram
IREF
SSC[1:0]
FSEL[1:0]
Pullup:Pullup
Default = 100MHz
Pulldown:Pullup
2
Spread Spectrum
Control
2
nQ1
nQ1
Q1
VDD
VDDA
GND
nQ0
23
IREF
nc
3
22
GND
nc
4
21
nc
VDD
5
20
nc
nc
6
19
SSC1
FSEL0
7
18
nc
nc
8
17
GND
9
10 11 12 13 14 15 16
GND
Feedback Divider
÷20
Q1
nc
2
OE
XTAL_OUT
24
VDD
XTAL_OUT
VCO
nQ0
nc
Phase
Detector
OSC
PLL Bypass
÷5
÷4
÷2
XTAL_IN
XTAL_IN
00
01
10
11
1
VDD
25MHz
32 31 30 29 28 27 26 25
VDD
SSC0
Q0
GND
Q0
Pullup
FSEL1
OE
Pin Assignment
ICS841202-245
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm ePad Size
K Package
Top View
ICS841202BK-245 REVISION A AUGUST 20, 2013
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©2013 Integrated Device Technology, Inc.
ICS841202-245 Data Sheet
CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2, 5, 11, 27
VDD
Power
3, 4, 6, 8, 12, 18,
20, 21, 24
nc
Unused
7
FSEL0
Input
Pullup
Output frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels.
Output frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels.
Core supply pins.
No connect.
9
FSEL1
Input
Pulldown
10,
19
SSC0,
SSC1
Input
Pullup
13,
14
XTAL_IN,
XTAL_OUT
Input
15
OE
Input
16, 17, 22, 29, 30
GND
Power
Power supply ground.
23
IREF
Power
HCSL current reference resistor output. An external fixed precision resistor
(475) from this pin to ground provides a reference current used for differential
current-mode Qx, nQx clock outputs.
25, 26
nQ1, Q1
Output
Differential output pair. HCSL interface levels.
28
VDDA
Power
Analog supply pin.
31, 32
nQ0, Q0
Output
Differential output pair. HCSL interface levels.
Spread spectrum control pins. See Table 3B. LVCMOS/LVTTL interface levels.
Parallel resonant crystal interface. XTAL_IN is the input, XTAL_OUT is the
output. (PLL reference.)
Pullup
Output enable pin. Logic HIGH, outputs are enabled. Logic LOW, outputs are in
an High-Impedance state. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
CIN
Input Capacitance
RPULLUP
RPULLDOWN
Minimum
OE, FSEL[1:0], SSC[1:0]
Typical
Maximum
Units
4
pF
Input Pullup Resistor
51
k
Input Pulldown Resistor
51
k
Function Tables
Table 3A. FSEL[1:0] Function Table
Inputs
Table 3B. SSC[1:0] Function Table
Inputs
Outputs
FSEL1
FSEL0
Output
Divided by
0
0
PLL Bypass
25MHz
0
0
Center ± 0.3
0
1
5
100MHz (default)
0
1
Down -0.6
1
0
4
125MHz
1
0
Down -0.9
1
1
2
250MHz
1
1
No Spread (default)
ICS841202BK-245 REVISION A AUGUST 20, 2013
Q[0:1], nQ[0:1]
SSC1
SSC0
Spread%
2
©2013 Integrated Device Technology, Inc.
ICS841202-245 Data Sheet
CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
XTAL_IN
Other Inputs
0V to VDD
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, JA
43.4C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
VDD – 0.2
3.3
VDD
V
IDD
Power Supply Current
130
158
mA
IDDA
Analog Supply Current
15
20
mA
Maximum
Units
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VIH
Input High Voltage
2
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input
High Current
IIL
Input
Low Current
FSEL1
VDD = VIN = 3.465V
150
μA
SSC0, SSC1,
FSEL0, OE
VDD = VIN = 3.465V
5
μA
FSEL1
VDD = 3.465V, VIN = 0V
-5
μA
SSC0, SSC1,
FSEL0, OE
VDD = 3.465V, VIN = 0V
-150
μA
Table 5. Crystal Characteristics
Parameter
Test Conditions
Mode of Oscillation
Minimum
Typical
Units
Fundamental
Frequency
25
Equivalent Series Resistance (ESR)
MHz
50
Load Capacitance (CL)
12
Shunt Capacitance
ICS841202BK-245 REVISION A AUGUST 20, 2013
Maximum
pF
7
3
pF
©2013 Integrated Device Technology, Inc.
ICS841202-245 Data Sheet
CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
fOUT
tsk(o)
tjit(cc)
tjit(per)
Parameter
Output Frequency
Test Conditions
Minimum
Typical
Period Jitter, RMS;
NOTE 2, 8, 14
Units
FSEL[1:0] = 00 (PLL Bypass)
25
MHz
FSEL[1:0] = 01 (default)
100
MHz
FSEL[1:0] = 10
125
MHz
FSEL[1:0] = 11
250
MHz
Output Skew; NOTE 1, 2
Cycle-to-Cycle Jitter;
NOTE 2, 3, 8
Maximum
115
ps
25MHz
46
ps
100MHz
55
ps
125MHz
55
ps
250MHz
55
ps
25MHz
1.85
3.50
ps
100MHz
2.30
4.15
ps
125MHz
2.00
2.85
ps
250MHz
1.65
2.35
ps
6
ms
tL
PLL Lock Time
3
FM
SSC Modulation Frequency;
NOTE 4
32
kHz
SSCRED
Spectral Reduction; NOTE 4
10
dB
VMAX
Absolute Maximum Output Voltage;
NOTE 5, 6
VMIN
Absolute Minimum Output Voltage;
NOTE 5, 7
-150
VRB
Ringback Voltage; NOTE 8, 9
-100
tSTABLE
Time before VRB is allowed;
NOTE 8, 9
VCROSS
Absolute Crossing Voltage;
NOTE 5, 10, 11
VCROSS
Total Variation of VCROSS;
NOTE 5, 10, 12
Edge Rate Rise/Fall Edge Rate; NOTE 8, 13
odc
Output Duty Cycle
1150
250
fOUT = 100MHz
0.6
mV
mV
100
mV
10
ms
550
mV
140
mV
4
V/ns
fOUT = 25MHz, 100MHz, 125MHz
45
55
%
fOUT = 250MHz
40
60
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Characterized using an 12pF parallel resonant crystal.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential
cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Only valid within the VCO operating range.
NOTE 4: Spread Spectrum clocking enabled.
NOTE 5: Measurement taken from single-ended waveform.
NOTE 6: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 7: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 8: Measurement taken from a differential waveform.
NOTES continue on next page.
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©2013 Integrated Device Technology, Inc.
ICS841202-245 Data Sheet
CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
NOTE 9: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100 differential range. See Parameter Measurement Information Section.
NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section.
NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement. See Parameter Measurement Information Section.
NOTE 12: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the
VCROSS for any particular system. See Parameter Measurement Information Section.
NOTE 13: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
See Parameter Measurement Information Section.
NOTE 14: Spread Spectrum clocking disabled, i.e. SSC[1:0] = 11 (default).
ICS841202BK-245 REVISION A AUGUST 20, 2013
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©2013 Integrated Device Technology, Inc.
ICS841202-245 Data Sheet
CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
Parameter Measurement Information
3.3V±5%
3.3V±5%
3.3V±5%
3.3V±5%
Measurement
Point
VDD
VDD
VDDA
VDDA
2pF
Measurement
Point
IREF
GND
2pF
0V
0V
This load condition is used for VMAX , VMIN, VRB, tSTABLE,
VCROSS, VCROSS, tSTABLE and Edge Rate measurements.
This load condition is used for IDD, tsk(cc), tsk(o) and tjit(per)
measurements.
3.3V HCSL Output Load Test Circuit
3.3V HCSL Output Load Test Circuit
nQx
nQ0, nQ1
Qx
Q0, Q1
nQy
tcycle n
tcycle n+1
Qy
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
Cycle-to-Cycle Jitter
Output Skew
VOH
VREF
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
Period Jitter, RMS
ICS841202BK-245 REVISION A AUGUST 20, 2013
Differential Measurement Points for Rise/Fall Edge Rate
6
©2013 Integrated Device Technology, Inc.
ICS841202-245 Data Sheet
CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
Parameter Measurement Information, continued
TSTABLE
VRB
+150mV
VRB = +100mV
0.0V
VRB = -100mV
-150mV
Q - nQ
VRB
TSTABLE
Differential Measurement Points for Duty Cycle/Period
Differential Measurement Points for Ringback
Single-ended Measurement Points for Absolute Cross
Point/Swing
Single-ended Measurement Points for Delta Cross Point
PLL Lock Time
ICS841202BK-245 REVISION A AUGUST 20, 2013
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©2013 Integrated Device Technology, Inc.
ICS841202-245 Data Sheet
CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
Differential Outputs
All control pins have internal pullup or pulldown resistors; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by one
side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 1A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
VCC
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 1B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
XTAL_OUT
R1
100
Ro
Rs
C1
Zo = 50 ohms
XTAL_IN
R2
100
Zo = Ro + Rs
.1uf
LVCMOS Driver
Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_IN
.1uf
Zo = 50 ohms
LVPECL Driver
R1
50
R2
50
R3
50
Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface
ICS841202BK-245 REVISION A AUGUST 20, 2013
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©2013 Integrated Device Technology, Inc.
ICS841202-245 Data Sheet
CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 2. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 2. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
ICS841202BK-245 REVISION A AUGUST 20, 2013
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©2013 Integrated Device Technology, Inc.
ICS841202-245 Data Sheet
CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
Recommended Termination
Figure 3A is the recommended source termination for applications
where the driver and receiver will be on a separate PCBs. This
termination is the standard for PCI Express™and HCSL output types.
0.5" Max
Rs
All traces should be 50Ω impedance single-ended or 100Ω
differential.
0.5 - 3.5"
1-14"
0-0.2"
22 to 33 +/-5%
L1
L2
L4
L1
L2
L4
L5
L5
PCI Expres s
PCI Expres s
Connector
Driver
0-0.2"
L3
L3
PCI Expres s
Add-in Card
49.9 +/- 5%
Rt
Figure 3A. Recommended Source Termination (where the driver and receiver will be on separate PCBs)
Figure 3B is the recommended termination for applications where a
point-to-point connection can be used. A point-to-point connection
contains both the driver and the receiver on the same PCB. With a
matched termination at the receiver, transmission-line reflections will
0.5" Max
Rs
0 to 33
L1
be minimized. In addition, a series resistor (Rs) at the driver offers
flexibility and can help dampen unwanted reflections. The optional
resistor can range from 0Ω to 33Ω. All traces should be 50Ω
impedance single-ended or 100Ω differential.
0-18"
0-0.2"
L2
L3
L2
L3
0 to 33
L1
PCI Expres s
Driver
49.9 +/- 5%
Rt
Figure 3B. Recommended Termination (where a point-to-point connection can be used)
ICS841202BK-245 REVISION A AUGUST 20, 2013
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©2013 Integrated Device Technology, Inc.
ICS841202-245 Data Sheet
CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
Application Schematic Example
power supply isolation is required. The ICS841202-245 provides
separate power supplies to isolate any high switching noise from
coupling into the internal PLL.
Figure 4 (next page) shows an example of ICS841202-245
application schematic. The schematic example focuses on functional
connections and is not configuration specific. Refer to the pin
description and functional tables in the datasheet to ensure that the
logic control inputs are properly set.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side. The other components can be on the opposite side of the
PCB. Power supply filter recommendations are a general guideline to
be used for reducing external noise from coupling into the devices
The filter performance is designed for a wide range of noise
frequencies. This low-pass filter starts to attenuate noise at
approximately 10kHz. a specific frequency noise component is
known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally, good general design
practices for power plane voltage stability suggests adding bulk
capacitance in the local area of all devices.
A 12pF parallel resonant 25MHz crystal is used. For this device, the
crystal load capacitors are required for proper operation. The load
capacitance, C1 = C2 = 15pF, are recommended for frequency
accuracy. Depending on the variation of the parasitic stray capacity
of the printed circuit board traces between the crystal and the
XTAL_IN and XTAL_OUT pins, the values of C1 and C2 might require
a slight adjustment to optimize the frequency accuracy. Crystals with
other load capacitance specifications can be used, but this will
require adjusting C1 and C2. When designing the circuit board,
return the capacitors to ground though a single point contact close to
the package.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
ICS841202BK-245 REVISION A AUGUST 20, 2013
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©2013 Integrated Device Technology, Inc.
ICS841202-245 Data Sheet
CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
C9
0.1uF
P la ce e ac h 0. 1u F by pa ss c ap d ir ec tl y
a dj ac en t to i ts c or re sp on di ng V DD o r
V DD A pi n.
C10
0.1uF
7
9
SSC0
SSC1
10
19
OE
15
27
VDDA
C3
10uF
SSC0
SSC1
OE
nQ0
32
Q0
31
nQ0
R3
R2
0 " to 18"
Zo = 50
33
+
33
Zo = 50
XTAL_IN
-
Optional
25 M Hz
(1 2p f)
4
C4
0.1uF
VDDA
C7
0.1uF
Fo x 32 5B S cr ys ta l
13
C5
10uF
R10 10
28
FSEL0
FSEL1
Q0
XTAL_IN
C6
0.1uF
VDD
11
VDD
5
VDD
1
2
FSEL0
FSEL1
VDD
VDD
U1
2
HCSL_Receiv er
R8
50
R5
50
X1
3 XTAL_OUT
C1
15pF
3.3V
1
BLM18BB221SN1
C8
0.1uF
1
FB1
2
VDD
14
XTAL_OUT
PCI Express
Point-to-Point
Connection
C2
15pF
26
Q1
nQ1
23
25
R6
33
Q1
R9
1" to 1 4"
Zo = 50
0 .5" t o 3.5 "
Zo = 50
+
33
nQ1
Zo = 50
Zo = 50
-
IREF
R7
50
nc
nc
nc
nc
nc
nc
nc
nc
nc
R4
50
HCSL_Receiv er
PCI Express Add-In Card
3
4
6
8
12
18
20
21
24
Logic Control Input Examples
VDD
Set Logic
Input to '1'
VDD
Set Logic
Input to '0'
16
17
22
29
30
GND
GND
GND
GND
GND
R1
475
RU1
1K
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
Figure 5. ICS841202-245 Schematic Example
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©2013 Integrated Device Technology, Inc.
ICS841202-245 Data Sheet
CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS841202-245.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS841202-245 is the sum of the core power plus the power dissipated into the load.
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated into the load.
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V *(158mA + 20mA) = 616.77mW
•
Power (outputs)MAX = 44.5mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 44.5mW = 89mW
Total Power_MAX = 616.77mW + 89mW = 705.77mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 43.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.706W * 43.4°C/W = 100.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
ICS841202BK-245 REVISION A AUGUST 20, 2013
0
1
2.5
43.4°C/W
37.9°C/W
34.0°C/W
13
©2013 Integrated Device Technology, Inc.
ICS841202-245 Data Sheet
CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 5.
VDD
IOUT = 17mA
VOUT
RREF =
475 ± 1%
RL
50
IC
Figure 5. HCSL Driver Circuit and Termination
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,
use the following equations which assume a 50 load to ground.
The highest power dissipation occurs when VDD_MAX.
Power = (VDD_MAX – VOUT) * IOUT
since VOUT = IOUT * RL
Power
= (VDD_MAX – IOUT * RL) * IOUT
= (3.465V – 17mA * 50) * 17mA
Total Power Dissipation per output pair = 44.5mW
ICS841202BK-245 REVISION A AUGUST 20, 2013
14
©2013 Integrated Device Technology, Inc.
ICS841202-245 Data Sheet
CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
Reliability Information
Table 8. JA vs. Air Flow Table for a 32 Lead VFQFN
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
43.4°C/W
37.9°C/W
34.0°C/W
Transistor Count
The transistor count for ICS841202-245 is: 4599
ICS841202BK-245 REVISION A AUGUST 20, 2013
15
©2013 Integrated Device Technology, Inc.
ICS841202-245 Data Sheet
CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
A3
N
L
N
Anvil
Anvil
Singulation
Singula tion
e (Ty p.)
2 If N & N
1
are Even
2
OR
E2
(N -1)x e
(Re f.)
E2
2
To p View
b
A
(Ref.)
D
e
D2
2
N &N
Odd
0. 08
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
C
D2
C
Bottom View w/Type A ID
Bottom View w/Type C ID
2
1
2
1
CHAMFER
4
Th er mal
Ba se
N N-1
RADIUS
4
N N-1
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
Table 9. Package Dimensions
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 9.
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.25
0.30
8
ND & NE
D&E
5.00 Basic
D2 & E2
3.0
3.3
e
0.50 Basic
L
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
ICS841202BK-245 REVISION A AUGUST 20, 2013
16
©2013 Integrated Device Technology, Inc.
ICS841202-245 Data Sheet
CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
Ordering Information
Table 10. Ordering Information
Part/Order Number
841202BK-245LF
841202BK-245LFT
Marking
ICS202B245L
ICS202B245L
ICS841202BK-245 REVISION A AUGUST 20, 2013
Package
“Lead-Free” 32 Lead VFQFN
“Lead-Free” 32 Lead VFQFN
17
Shipping Packaging
Tray
Tape & Reel
Temperature
0C to 70C
0C to 70C
©2013 Integrated Device Technology, Inc.
ICS841202-245 Data Sheet
CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
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