841604AGI-01LFT

FemtoClock® Crystal-to-0.7V Differential ICS841604I-01 DATA SHEET General Description Features The ICS841604I-01 is an optimized PCIe and sRIO clock generator. The device uses a 25MHz parallel crystal to generate 100MHz and 125MHz clock signals, replacing solutions requiring multiple oscillator and fanout buffer solutions. The device has excellent phase jitter (< 1ps rms) suitable to clock components requiring precise and low-jitter PCIe or sRIO or both clock signals. Designed for telecom, networking and industrial applications, the ICS841604I-01 can also drive the high-speed sRIO and PCIe SerDes clock inputs of communication processors, DSPs, switches and bridges. • Four 0.7V differential HCSL outputs: configurable for PCIe (100MHz) and sRIO (125MHz) clock signals • Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or LVCMOS/LVTTL single-ended reference clock input • • • • Supports the following output frequencies: 100MHz or 125MHz • PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter compliant • • • Full 3.3V operating supply VCO: 500MHz PLL bypass and output enable RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.5ps (typical) -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Q0 XTAL_IN OSC FemtoClock PLL XTAL_OUT REF_IN 1 0 Pulldown 1 VCO = 500MHz 0 nQ0 M= Pulldown OE0 Q1 ÷4 ÷5 (default) REF_SEL nQ1 Pulldown OE1 Pulldown Q2 M = ÷20 IREF nQ2 BYPASS Pulldown FSEL Pulldown Pulldown OE2 Q3 nQ3 Pulldown OE3 MR Pulldown ICS841604GI-01 REVISION A APRIL 10, 2012 1 REF_SEL REF_IN VDD GND XTAL_IN XTAL_OUT MR VDD OE3 OE2 OE1 OE0 GND VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDDA BYPASS IREF FSEL VDD nQ3 Q3 nQ2 Q2 GND nQ1 Q1 nQ0 Q0 ICS841604I-01 28-Lead TSSOP, 240MIL 6.1mm x 9.7mm x 0.925mm package body G Package Top View ©2012 Integrated Device Technology, Inc. ICS841604I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR Table 1. Pin Descriptions Number Name Type 1 REF_SEL Input Pulldown Reference select. Selects the input reference source. LVCMOS/LVTTL interface levels. See Table 3A. 2 REF_IN Input Pulldown LVCMOS/LVTTL PLL reference clock input. 3, 8, 14, 24 VDD Power 4, 13, 19 GND Power 5, 6 XTAL_IN, XTAL_OUT Input 7 MR Input Pulldown Active HIGH master reset. When logic HIGH, the internal dividers are reset. When logic LOW, the internal dividers are enabled. See Table 3D. LVCMOS/LVTTL interface levels. 9, 10, 11, 12 OE3, OE2, OE1, OE0 Input Pulldown Output enable pins. LVCMOS/LVTTL interface levels. See Table 3D. 15, 16 Q0, nQ0 Output Differential output pair. HCSL interface levels. 17, 18 Q1, nQ1 Output Differential output pair. HCSL interface levels. 20, 21 Q2, nQ2 Output Differential output pair. HCSL interface levels. 22, 23 Q3, nQ3 Output Differential output pair. HCSL interface levels. 25 FSEL Input 26 IREF Output 27 BYPASS Input 28 VDDA Power Description Core supply pins. Power supply ground. Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. (PLL reference.) Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels. See Table 3B. 0.7V current reference resistor output. An external fixed precision resistor (475) from this pin to ground provides a reference current used for differential current-mode Qx, nQx clock outputs. Pulldown Selects PLL operation/PLL bypass operation. Asynchronous function. LVCMOS/LVTTL interface levels. See Table 3C. Analog supply pin. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance Test Conditions RPULLDOWN Input Pulldown Resistor ICS841604GI-01 REVISION A APRIL 10, 2012 2 Minimum Typical Maximum Units 4 pF 51 k ©2012 Integrated Device Technology, Inc. ICS841604I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR Function Tables Table 3A. REF_SEL Function Table Input REF_SEL Input Reference 0 XTAL (default) 1 REF_IN Table 3B. FSEL Function Table (fREF = 25MHz) Inputs Outputs FSEL N Divider Q[0:3], nQ[0:3] 0 5 VCO/5 (100MHz) PCIe (default) 1 4 VCO/4 (125MHz) sRIO Table 3C. BYPASS Function Table Input BYPASS PLL Configuration 0 PLL enabled (default) 1 PLL bypassed (fOUT = fREF/N) Table 3D. MR, OEx Function Table Inputs MR 0 (default) 1 Outputs OE[0:3] Q[0:3], nQ[0:3] OE3 = 0 Q3, nQ3 are High-Impedance (default) OE3 = 1 Q3, nQ3 are enabled OE2 = 0 Q2, nQ2 are High-Impedance (default) OE2 = 1 Q2, nQ2 are enabled OE1 = 0 Q1, nQ1 are High-Impedance (default) OE1 = 1 Q1, nQ1 are enabled OE0 = 0 Q0, nQ0 are High-Impedance (default) OE0 = 1 Q0, nQ0 are enabled X All outputs are High-Impedance, all internal dividers are reset ICS841604GI-01 REVISION A APRIL 10, 2012 3 ©2012 Integrated Device Technology, Inc. ICS841604I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 64.5C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VDD Core Supply Voltage VDDA Analog Supply Voltage IDD Power Supply Current IDDA Analog Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V VDD – 0.20 3.3 VDD V OE[0:3] = 0 87 mA OE[0:3] = 0 20 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current REF_IN, REF_SEL, BYPASS, F_SEL, MR, OE{0:3] VDD = VIN = 3.465V 150 µA IIL Input Low Current REF_IN, REF_SEL, BYPASS, F_SEL, MR, OE{0:3] VDD = 3.465V, VIN = 0V -5 µA Table 5. Crystal Characteristics Parameter Test Conditions Mode of Oscillation Minimum Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50  Shunt Capacitance 7 pF NOTE: Characterized using an 18pF parallel resonant crystal. ICS841604GI-01 REVISION A APRIL 10, 2012 4 ©2012 Integrated Device Technology, Inc. ICS841604I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR AC Electrical Characteristics Table 6A. PCI Express Jitter Specifications, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol tj (PCIe Gen 1) tREFCLK_HF_R MS (PCIe Gen 2) tREFCLK_LF_R MS (PCIe Gen 2) tREFCLK_RMS (PCIe Gen 3) Parameter Phase Jitter Peak-to-Peak; NOTE 1, 4 Phase Jitter RMS; NOTE 2, 4 Phase Jitter RMS; NOTE 2, 4 Phase Jitter RMS; NOTE 3, 4 Test Conditions Minimum PCIe Industry Specification Typical Maximum Units ƒ = 100MHz, 25MHz Crystal Input Evaluation Band: 0Hz - Nyquist (clock frequency/2) 12.1 28 ƒ = 125MHz, 25MHz Crystal Input Evaluation Band: 0Hz - Nyquist (clock frequency/2) 11.7 30 ps ƒ = 100MHz, 25MHz Crystal Input High Band: 1.5MHz - Nyquist (clock frequency/2) 0.82 2.15 ps ƒ = 125MHz, 25MHz Crystal Input High Band: 1.5MHz - Nyquist (clock frequency/2) 0.8 2.2 ƒ = 100MHz, 25MHz Crystal Input Low Band: 10kHz - 1.5MHz 0.15 0.47 ƒ = 125MHz, 25MHz Crystal Input Low Band: 10kHz - 1.5MHz 0.15 0.55 ps ƒ = 100MHz, 25MHz Crystal Input Evaluation Band: 0Hz - Nyquist (clock frequency/2) 0.17 0.41 ps ƒ = 125MHz, 25MHz Crystal Input Evaluation Band: 0Hz - Nyquist (clock frequency/2) 0.17 ps 86 3.1 ps ps 3.0 0.8 0.45 ps NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet. NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification. NOTE 4: This parameter is guaranteed by characterization. Not tested in production. ICS841604GI-01 REVISION A APRIL 10, 2012 5 ©2012 Integrated Device Technology, Inc. ICS841604I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR AC Electrical Characteristics Table 6B. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency Test Conditions Minimum VCO/5 Typical Maximum 100 Units MHz VCO/4 125 100MHz (1.875MHz – 20MHz) 0.47 0.98 MHz ps 125MHz (1.875MHz – 20MHz) 0.50 1.02 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 1 tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 60 ps tsk(o) Output Skew; NOTE 2, 3 70 ps VMAX Absolute Maximum Output Voltage; NOTE 4, 5 1150 mV VMIN Absolute Minimum Output Voltage; NOTE 4, 6 -300 VRB Ringback Voltage; NOTE 7, 8 -100 tSTABLE Time before VRB is allowed; NOTE 7, 8 500 VCROSS Absolute Crossing Voltage; NOTE 4, 9, 10 220 VCROSS Total Variation of VCROSS; NOTE 4, 9, 11 tSLEW Rising/Falling Edge Rate; NOTE 7, 12 odc Output Duty Cycle; NOTE 7 tL mV 100 mV ps 530 mV 150 mV 0.6 4.0 V/ns 47 53 % PLL Lock Time 90 ms tPLZ, HZ Output Disable Time 5 ns tPZL, ZH Output Enable Time 5 ns Measured between -150mV to +150mV NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Refer to the Phase Noise Plots. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3 Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4 Measurement taken from a single-ended waveform. NOTE 5: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 6: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 7: Measurement taken from a differential waveform. NOTE 8: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100 differential range. See Parameter Measurement Information Section. NOTE 9: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx. See Parameter Measurement Information Section. NOTE 10: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Parameter Measurement Information Section. NOTE 11: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the VCROSS for any particular system. See Parameter Measurement Information Section. NOTE 12: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. See Parameter Measurement Information Section. ICS841604GI-01 REVISION A APRIL 10, 2012 6 ©2012 Integrated Device Technology, Inc. ICS841604I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR Noise Power dBc Hz Typical Phase Noise at 100MHz Offset Frequency (Hz) ICS841604GI-01 REVISION A APRIL 10, 2012 7 ©2012 Integrated Device Technology, Inc. ICS841604I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR Noise Power dBc Hz Typical Phase Noise at 125MHz Offset Frequency (Hz) ICS841604GI-01 REVISION A APRIL 10, 2012 8 ©2012 Integrated Device Technology, Inc. ICS841604I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR Parameter Measurement Information 3.3V±5% 3.3V±5% 3.3V±5% 3.3V±5% SCOPE Measurement Point 50Ω 33Ω VDD VDDA 49.9Ω 2pF HCSL IREF 50 Measurement Point 50Ω 33Ω 50 IREF GND 475 GND 49.9Ω 2pF 475Ω 0V 0V 0V This load condition is used for IDD, tjit(cc) and tsk(o) measurements. 3.3V HCSL Output Load AC Test Circuit 3.3V HCSL Output Load AC Test Circuit nQ0:nQ3 nQx Q0:Q3 Qx ➤ ➤ tcycle n tcycle n+1 ➤ nQy ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles Qy tsk(o) Cycle-to-Cycle Jitter Output Skew Phase Noise Plot Noise Power Rise Edge Rate Fall Edge Rate +150mV 0.0V -150mV Q - nQ f1 Offset Frequency f2 RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers RMS Phase Jitter ICS841604GI-01 REVISION A APRIL 10, 2012 Differential Measurement Points for Rise/Fall Edge Rate 9 ©2012 Integrated Device Technology, Inc. ICS841604I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR Parameter Measurement Information, continued TSTABLE Clock Period (Differential) VRB Positive Duty Cycle (Differential) +150mV VRB = +100mV 0.0V VRB = -100mV -150mV Negative Duty Cycle (Differential) 0.0V Q - nQ VRB Q - nQ TSTABLE Differential Measurement Points for Duty Cycle/Period Differential Measurement Points for Ringback VMAX nQ nQ VCROSS_MAX ΔVCROSS VCROSS_MIN Q VMIN Q Single-ended Measurement Points for Delta Cross Point Single-ended Measurement Points for Absolute Cross Point/Swing PLL Locktime ICS841604GI-01 REVISION A APRIL 10, 2012 10 ©2012 Integrated Device Technology, Inc. ICS841604I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR Application Information Recommendations for Unused Input and Output Pins Inputs: Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. LVCMOS Control Pins All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: REF_IN Differential Outputs For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_IN to ground. All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Overdriving the XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 1A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. 3.3V 3.3V R1 100 Ro ~ 7 Ohm C1 Zo = 50 Ohm XTAL_IN RS 43 R2 100 Driv er_LVCMOS 0.1uF XTAL_OUT Cry stal Input Interf ace Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface VCC=3.3V C1 Zo = 50 Ohm XTAL_IN R1 50 Zo = 50 Ohm 0.1uF XTAL_OUT LVPECL Cry stal Input Interf ace R2 50 R3 50 Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface ICS841604GI-01 REVISION A APRIL 10, 2012 11 ©2012 Integrated Device Technology, Inc. ICS841604I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR PCI Express Application Note individual transfer functions as well as the overall transfer function Ht. PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: Ht  s  = H3  s    H1  s  – H2  s   The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: Y  s  = X  s   H3  s    H1  s  – H2  s   In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. PCIe Gen 2A Magnitude of Transfer Function PCI Express Common Clock Architecture For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is reported in peak-peak. PCIe Gen 2B Magnitude of Transfer Function For PCI Express Gen 3, one transfer function is defined and the evaluation is performed over the entire spectrum. The transfer function parameters are different from Gen 1 and the jitter result is reported in RMS. PCIe Gen 1 Magnitude of Transfer Function PCIe Gen 3 Magnitude of Transfer Function For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High Band). The plots show the ICS841604GI-01 REVISION A APRIL 10, 2012 For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements. 12 ©2012 Integrated Device Technology, Inc. ICS841604I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR Recommended Termination Figure 2A is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This termination is the standard for PCI Express™ and HCSL output 0.5" Max Rs types. All traces should be 50Ω impedance single-ended or 100Ω differential. 0.5 - 3.5" 1-14" 0-0.2" 22 to 33 +/-5% L1 L2 L4 L5 L1 L2 L4 L5 PCI Expres s PCI Expres s Connector Driver 0-0.2" L3 L3 PCI Expres s Add-in Card 49.9 +/- 5% Rt Figure 2A. Recommended Source Termination (where the driver and receiver will be on separate PCBs) Figure 2B is the recommended termination for applications where a point-to-point connection can be used. A point-to-point connection contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line reflections will 0.5" Max Rs 0 to 33 L1 be minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections. The optional resistor can range from 0Ω to 33Ω. All traces should be 50Ω impedance single-ended or 100Ω differential. 0-18" 0-0.2" L2 L3 L2 L3 0 to 33 L1 PCI Expres s Driver 49.9 +/- 5% Rt Figure 2B. Recommended Termination (where a point-to-point connection can be used) ICS841604GI-01 REVISION A APRIL 10, 2012 13 ©2012 Integrated Device Technology, Inc. ICS841604I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR Schematic Example Figure 3 shows an example of ICS841604I-01 application schematic. In this example, the device is operated at VDD = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The load capacitance C1 =27pF and C2 = 27pF are recommended for frequency accuracy. Depending on the parasitic of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. This will require adjusting C1 and C2. For this device, the crystal load capacitors are required for proper operation. pins as possible. If space is limited, the 0.1uf capacitor in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10 kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS841604I-01 provides separate power supplies to isolate any high switching noise from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power VDD The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. R1 V D DA 10 VD D C3 10u C4 0. 1u R2 33 Q3 Q1 Ro ~ 7 OhmR 3 Zo = 50 + Zo = 50 Ohm R4 475 R5 33 nQ3 Zo = 50 - 43 U1 D riv er_LVC MOS R EF_SE L R EF_I N V DD MR VD D 25MH z F p 8 1 X1 OE3 OE2 OE1 OE0 VD D C1 27pF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 R EF _S EL R EF _I N VD D GN D XTAL_I N XTAL_OU T MR VD D OE3 OE2 OE1 OE0 GN D VD D V D DA B YP ASS IR EF FS EL VD D nQ3 Q3 nQ2 Q2 GN D nQ1 Q1 nQ0 Q0 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R6 50 B Y PAS S F SEL VDD=3.3V R8 0-33 Zo = 50 R9 Zo = 50 Set Logic Input to '0' V DD HCSL Optional Term ination R D1 N ot Ins t all To Logic Input pins RD2 1K - R 10 50 RU2 N ot I nst all To Logic Input pins + 0-33 nQ0 Logic Control Input Examples R U1 1K HCSL Term ination Opt ional Q0 Set Logic Input t o '1' Recommended for PCI Express Add-In Card VD D C2 27pF VD D R7 50 R 11 50 Recommended for PCI Express Point-to-Point Connection 3.3V (U1:3) FB 1 2 MU RA TA, BLM18BB 221SN 1 C6 C5 0.1uF (U1:8) (U1:14) (U1:24) VD D 10uF C7 0. 1uF C8 0.1uF C9 0. 1uF C 10 0.1uF Figure 3. ICS841604I-01 Application Schematic ICS841604GI-01 REVISION A APRIL 10, 2012 14 ©2012 Integrated Device Technology, Inc. ICS841604I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR Power Considerations This section provides information on power dissipation and junction temperature for the ICS841604I-01 Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS841604I-01 is the sum of the core power plus analog plus the power dissipation in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipation in the load. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (87mA + 20mA) = 370.755mW • Power (outputs)MAX = 44.5mW/Loaded Output pair Power (output)MAX = 44.5mW * 4 = 178mW Total Power_MAX = (3.465V, with all outputs switching) = 370.755mW +178mW = 548.755mW • 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 64.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.549W * 64.5°C/W = 120.4°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance JA for 28 Lead TSSOP, Forced Convection JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS841604GI-01 REVISION A APRIL 10, 2012 0 1 2.5 64.5°C/W 60.4°C/W 58.5°C/W 15 ©2012 Integrated Device Technology, Inc. ICS841604I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 4. VDD IOUT = 17mA ➤ VOUT RREF = 475Ω ± 1% RL 50Ω IC Figure 4. HCSL Driver Circuit and Termination HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDD_MAX. Power = (VDD_MAX – VOUT) * IOUT, since VOUT – IOUT * RL = (VDD_MAX – IOUT * RL) * IOUT = (3.465V – 17mA * 50) * 17mA Total Power Dissipation per output pair = 44.5mW ICS841604GI-01 REVISION A APRIL 10, 2012 16 ©2012 Integrated Device Technology, Inc. ICS841604I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR Reliability Information Table 8. JA vs. Air Flow Table for a 28 Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 64.5°C/W 60.4°C/W 58.5°C/W Transistor Count The transistor count for ICS841604I-01 is: 2760 Package Outline and Package Dimensions Package Outline - G Suffix for 28 Lead TSSOP Table 9. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 28 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 9.60 9.80 E 8.10 Basic E1 6.00 6.20 e 0.65 Basic L 0.45 0.75  0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS841604GI-01 REVISION A APRIL 10, 2012 17 ©2012 Integrated Device Technology, Inc. ICS841604I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR Ordering Information Table 10. Ordering Information Part/Order Number 841604AGI-01LF 841604AGI-01LFT Marking ICS841604AGI01L ICS841604AGI01L Package “Lead-Free” 28 Lead TSSOP “Lead-Free” 28 Lead TSSOP Shipping Packaging Tube 1000 Tape & Reel Temperature -40C to 85C -40C to 85C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. 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ICS841604GI-01 REVISION A APRIL 10, 2012 18 ©2012 Integrated Device Technology, Inc. ICS841604I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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