FemtoClock® NG Crystal-to-HCSL
Frequency Synthesizer
841N4830
Datasheet
General Description
Features
The 841N4830 is a 3 HCSL, 1 LVPECL and 2 LVCMOS output
Synthesizer optimized to generate PCI Express reference clock
frequencies. The device uses IDT’s fourth generation FemtoClock®
NG technology for synthesis of high clock frequency at very low
phase noise. It provides low power consumption with good power
supply noise rejection. Using a 25MHz, 12pF parallel resonant
crystal, the following frequencies can be generated: 100MHz,
50MHz and 25MHz. Maximum rms phase jitter of 0.36ps, easily
meets PCI Express jitter requirements. The 841N4830 is packaged
in a small 32-pin VFQFN package.
•
•
Fourth generation FemtoClock® Next Generation (NG) technology
•
Crystal oscillator interface designed for a 25MHz, 12pF parallel
resonant crystal
•
CLK/nCLK input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
•
A 25MHz crystal generates output frequencies of: 100MHz,
50MHz and 25MHz
•
•
VCO frequency: 2GHz
•
•
•
•
•
Power supply noise rejection PSNR: -45dB (typical)
Three differential HCSL outputs, one differential LVPECL and
two single-ended LVCMOS/LVTTL outputs
RMS Phase Jitter @ 100MHz, (12kHz – 20MHz) using a 25MHz
crystal: 0.36ps (maximum)
PCI Express Gen 2 (5 Gb/s) jitter compliant
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
FemtoClock® NG
VCO
2GHz
÷20
3
nQA[2:0]
0
100MHz LVCMOS
1
QA3
CLK_SEL Pullup
÷1
0
IREF
100/50MHz
LVCMOS
÷80
DIV2_QB
÷2
QB
1
DIV2_QB
4
VDDA
5
CLK
6
nCLK
7
VDDO_REF
8
GND
nQA0
QA0
IREF
841N4830
23
nQA1
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
22
VDDO
21
QA2
20
nQA2
19
GND
18
QA3
17
VDDO_QA3
9
10 11 12 13 14 15 16
QB
PFD
&
LPF
XTAL_OUT
nCLK Pullup
3
QA[2:0]
0
3
QA1
VDD_OSC
OSC
CLK Pulldown
100MHz HCSL
1
nOEB
24
VDDO_QB
XTAL_IN
nOE_REF
2
XTAL_OUT
25MHz
1
XTAL_IN
nOEA Pulldown
32 31 30 29 28 27 26 25
PLL_BYPASS
CLK_SEL
nREF_OUT
PLL_BYPASS Pulldown
VDDO
REF_OUT
nOEA
VDDA
25MHz LVPECL
REF_OUT
nOE_REF Pulldown
VDD
Pin Assignment
nREF_OUT
Block Diagram
Pullup
nOEB Pulldown
©2016 Integrated Device Technology, Inc.
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841N4830 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1
PLL_BYPASS
Input
Pulldown
When HIGH, PLL is bypassed and outputs are driven by input crystal or clock. When
LOW outputs are driven by PLL. LVCMOS/LVTTL interface levels. See Table 3D.
2
nOE_REF
Input
Pulldown
Output enable signal for REF_OUT output. When LOW, outputs are enabled.
LVCMOS/LVTTL interface levels. See Table 3C.
3
nOEB
Input
Pulldown
Output enable signal for Bank B. When LOW, QB output is enabled. When HIGH,
selects high impedance mode. LVCMOS/LVTTL interface levels.See Table 3B.
4
DIV2_QB
Input
Pullup
Select signal for the output divider for Bank B. LVCMOS/LVTTL clock output. See
Table 3F.
5, 32
VDDA
Power
6
CLK
Input
7
nCLK
Input
8
VDDO_REF
Power
Output power supply pin for LVPECL reference outputs.
9, 10
REF_OUT,
nREF_OUT
Output
25MHz differential reference output pair. LVPECL interface levels.
11
CLK_SEL
Input
12
13
XTAL_IN
XTAL_OUT
Input
14
VDD_OSC
Power
Core supply pin for crystal oscillator.
15
VDDO_QB
Power
Output power supply pin for Bank B LVCMOS output.
16
QB
Output
Single-ended output. LVCMOS/LVTTL interface levels.
17
VDDO_QA3
Power
Output power supply pin for QA3 LVCMOS output.
18
QA3
Output
Single-ended output. LVCMOS/LVTTL interface levels.
19, 25
GND
Power
Power supply ground.
20, 21
nQA2, QA2
Output
100MHz differential output pair. HCSL interface levels.
22, 29
VDDO
Power
Output power supply pins for Bank A HCSL outputs.
23, 24
nQA1, QA1
Output
100MHz differential output pair. HCSL interface levels.
26, 27
nQA0, QA0
Output
100MHz differential output pair. HCSL interface levels.
28
IREF
30
nOEA
Input
31
VDD
Power
Analog supply pins.
Pulldown Non-inverting differential clock input.
Pullup
Pullup
Inverting differential clock input.
Input select signal. When HIGH, selects CLK, nCLK inputs. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.See Table 3E.
Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output.
0.7V current reference resistor output. An external fixed precision resistor (475) from
this pin to ground provides a reference current used for differential current-mode QAx,
nQAx clock outputs.
Pulldown
Output Enable signal for Bank A. When LOW enables output. When HIGH selects
high impedance mode. LVCMOS/LVTTL interface levels.See Table 3A.
Core supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2016 Integrated Device Technology, Inc.
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841N4830 Datasheet
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
CIN
Input Capacitance
RPULLUP
Minimum
Typical
Maximum
Units
CLK, nCLK
2
pF
Control Pins
4
pF
Input Pullup Resistors
100
k
RPULLDOWN
Input Pulldown Resistors
100
k
CPD
Power Dissipation
Capacitance (per output)
VDD, VDD_OSC, VDDO, VDDO_REF,
VDDO_QA3, VDDO_QB = 3.6V
5
pF
ROUT
Output
Impedance
VDDO_QA3, VDDO_QB = 3.6V
25
QA3, QB
Function Tables
Table 3A. nOEA Function Table
Table 3B. nOEB Function Table
Input
Outputs
Input
Outputs
nOEA
QA
nOEB
QB
0 (default)
Active
0 (default)
Active
1
High-Impedance
1
High-Impedance
Table 3C. nOE_REF Function Table
Table 3D. PLL_BYPASS Function Table
Input
Outputs
Input
Outputs
nOE_REF
REF_OUT
PLL_BYPASS
QA, QB
0 (default)
Active
0 (default)
PLL
1
High-Impedance
1
Bypass PLL
Table 3E. CLK_SEL Function Table
Table 3F. DIV2_QB Function Table
Input
Input
CLK_SEL
Selected Input
DIV2_QB
Output Frequency
0
XTAL
0
100MHz
1 (default)
CLK, nCLK
1 (default)
50MHz
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841N4830 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics
or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
3.63V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, VO (LVCMOS, HCSL)
-0.5V to VDDO + 0.5V
Outputs, IO (LVPECL)
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, JA
37.7C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDD_OSC = 3.0V to 3.6V, VDDO = VDDO_QA3 = VDDO_QB = VDDO_REF =
2.7V to 3.6V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD,
VDD_OSC
Core Supply Voltage
3.0
3.3
3.6
V
VDDA
Analog Supply Voltage
VDD – 0.32
3.3
VDD
V
VDDO,
VDDOx
Output Supply Voltage
2.7
3.3
3.6
V
IEE
Power Supply Current
170
mA
IDDA
Analog Supply Current
32
mA
Included in IEE
VDDOx denotes VDDO_REF, VDDO_QA3 and VDDO_QB.
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.0V to 3.6V, VDDO_QA3 = VDDO_QB = 2.7V to 3.6V, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
Input
High Current
Input
Low Current
Test Conditions
Minimum
Typical
Maximum
Units
2
VDD + 0.3
V
-0.3
0.8
V
CLK_SEL,
DIV2_QB
VDD = VIN = 3.6V
5
µA
nOEA, nOEB,
nOE_REF,
PLL_BYPASS
VDD = VIN = 3.6V
150
µA
CLK_SEL,
DIV2_QB
VDD = 3.6V, VIN = 0V
-150
µA
nOEA, nOEB,
nOE_REF,
PLL_BYPASS
VDD = 3.6V, VIN = 0V
-5
µA
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841N4830 Datasheet
Table 4C. Differential DC Characteristics, VDD = 3.0V to 3.6V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
IIH
Input High
Current
IIL
Input Low
Current
VPP
Peak-to-Peak Voltage; NOTE 1
VCMR
Common Mode Input Voltage;
NOTE 1, 2
Minimum
Typical
Maximum
Units
CLK
VDD = VIN = 3.6V
150
µA
nCLK
VDD = VIN = 3.6V
5
µA
CLK
VDD = 3.6V, VIN = 0V
-5
µA
nCLK
VDD = 3.6V, VIN = 0V
-150
µA
0.15
1.3
V
GND + 0.5
VDD – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. LVPECL DC Characteristics, VDDO_REF = 2.7V to 3.6V, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
Typical
Maximum
Units
VDDO_REF – 1.4
VDDO _REF – 0.9
V
VDDO_REF – 2.0
VDDO_REF – 1.7
V
0.6
1.0
V
NOTE 1: Output termination with 50 to VDDO_REF – 2V.
Table 5. Crystal Characteristics
Parameter
Test Conditions
Mode of Oscillation
Minimum
Typical
Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
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841N4830 Datasheet
AC Electrical Characteristics
Table 6A. LVCMOS AC Characteristics, VDD = 3.0V to 3.6V, VDDO_QA3 = VDDO_QB = 2.7V to 3.6V, TA = -40°C to 85°C
Symbol
fOUT
Parameter
Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
QB
PLL mode
50
MHz
QA3
PLL mode
100
MHz
PLL Bypass
tjit(Ø)
RMS Phase Jitter (Random); NOTE 1
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
VOH
Output High Voltage;
NOTE 2
QA3, QB
VOL
Output Low Voltage;
NOTE 2
QA3, QB
20
MHz
100MHz, Integration Range:
12kHz – 20MHz
0.34
ps
200
600
ps
47
53
%
2.2
V
ƒ 100MHz
0.9
V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
Using a 25MHz, 12pF quartz crystal.
NOTE 1: Refer to the Phase Noise plot.
NOTE 2: Outputs are terminated with 50 to VDDO_X/2. See Parameter Measurement Information, Output Load Test Circuit diagram.
Table 6B. LVPECL AC Characteristics, VDD = 3.0V to 3.6V, VDDO_REF = 2.7V to 3.6V, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
fOUT
Output Frequency
REF_OUT,
nREF_OUT
tR / tF
Output
Rise/Fall Time
REF_OUT,
nREF_OUT
odc
Output Duty Cycle
REF_OUT,
nREF_OUT
Minimum
Typical
Maximum
25
20% to 80%
Units
MHz
100
600
ps
49
51
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
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841N4830 Datasheet
Table 6C. HCSL AC Characteristics, VDD = 3.0V to 3.6V, VDDO = 2.7V to 3.6V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
fOUT
Output Frequency
fREF
Reference Frequency
tsk(b)
Bank Skew; NOTE 1, 10
tjit(Ø)
Phase Jitter, RMS (Random);
NOTE 11
100MHz, Integration Range:
12kHz – 20MHz
tREFCLK_HF_RMS
Phase Jitter RMS; NOTE 2
100MHz, 25MHz crystal input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
0.600
ps
tREFCLK_LF_RMS
Phase Jitter RMS; NOTE 2
100MHz, 25MHz crystal input
Low Band: 10kHz - 1.5MHz
0.023
ps
tjit(cc)
Cycle-to-Cycle Jitter
tL
PLL Lock Time
VRB
Ring-back Voltage Margin;
NOTE 4, 9
-100
tSTABLE
Time before VRB is allowed;
NOTE 4, 9
500
VHIGH
Voltage High
520
920
mV
VLOW
Voltage Low
-150
150
mV
VCROSS
Absolute Crossing Voltage;
NOTE 3, 6, 7
160
460
mV
VCROSS
Total Variation of VCROSS over
all edges; NOTE 3, 6, 8
140
mV
PLL
Typical
Maximum
100
PLL Bypass
Units
MHz
20
MHz
25
PLL Mode
MHz
50
ps
0.36
ps
30
ps
10
ms
100
mV
ps
Rising Edge Rate; NOTE 4, 5
0.6
4.0
V/ns
Falling Edge Rate; NOTE 4, 5
0.6
4.0
V/ns
PSNR
Power Supply Noise
Reduction
odc
Output Duty Cycle; NOTE 4
-45
49
dB
51
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS
(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). See IDT Application Note PCI Express Reference Clock Requirements and also
the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.
NOTE 3: Measurement taken from single ended waveform.
NOTE 4: Measurement taken from differential waveform.
NOTE 5: Measured from -150mV to +150mV on the differential waveform (derived from Q minus nQ). The signal must be monotonic through
the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
NOTE 6: Measured at the crosspoint where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ.
NOTE 7: Refers to the total variation from the lowest crosspoint to the highest, regardless of which edge is crossing. Refers to all crosspoints
for this measurement.
NOTE 8: Defined as the total variation of all crossing voltages of rising Q and falling nQ, This is the maximum allowed variance in VCROSS for
any particular system.
NOTE 9: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100mV differential range.
NOTE 10: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 11: See Phase Noise Plot.
©2016 Integrated Device Technology, Inc.
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Revision F, May 23, 2016
841N4830 Datasheet
Noise Power dBc
Typical Phase Noise at 100MHz (3.3V)
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc.
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841N4830 Datasheet
Parameter Measurement Information
1.85V±0.15V
2V
1.65V±9.1%
2V
1.65V±9.1%
SCOPE
VDDA
VDDA
VDD_OSC
REF_OUT
VDDO_REF
SCOPE
VDDA
VDD,
VDD_OSC,
VDDOB,
VDDO_QA3,
VDDA
VDD,
1.575V±0.225V
VEE
Q
VEE
nREF_OUT
-1.3V±0.3V
-1.65V±9.1%
3.3V LVPECL Output Load Test Circuit
3.3V±9.1%
3.3V LVCMOS Output Load Test Circuit
3.15V±14.3%
3.3V±9.1%
3.15V±14.3%
3.3V±9.1%
3.3V±9.1%
SCOPE
VDDA
VDD,
VDDA
VDD_OSC
50Ω
33Ω
VDDO
VEE
Qx
49.9Ω
Qx
DDO
50Ω
VEE
nQx
49.9Ω
475Ω
50Ω
2pF
50Ω
33Ω
VDDA
VDD,
VDDA
VDD_OSC
V
nQx
2pF
475Ω
475Ω
This load condition is used for VHIGH, VLOW, VRB, tSTABLE and
VCROSS, VCROSS measurements.
475Ω
This load condition is used for IDD, tjit(cc), tsk(b), odc and tjit(Ø)
measurements.
3.3V HCSL Output Load Test Circuit
3.3V HCSL Output Load Test Circuit
VDD
nREF_OUT
80%
nCLK
V
PP
Cross Points
80%
VSW I N G
V
CMR
20%
20%
CLK
QA3, QB,
REF_OUT
tR
tF
GND
Output Rise/Fall Time (LVPECL, LVCMOS)
Differential Input Level
©2016 Integrated Device Technology, Inc.
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841N4830 Datasheet
Parameter Measurement Information, continued
nREF_OUT
REF_OUT
RMS Phase Jitter
LVPECL Output Duty Cycle/Pulse Width/Period
nQA[0:2]
QA3, QB
t PW
t
QA[0:2]
PERIOD
tcycle n
odc =
t PW
tcycle n+1
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
x 100%
t PERIOD
LVCMOS Output Duty Cycle/Pulse Width/Period
Cycle-to-Cycle Jitter
nQAx
QAx
nQAx
QAx
tsk(b)
PLL Lock Time
©2016 Integrated Device Technology, Inc.
Bank Skew
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Revision F, May 23, 2016
841N4830 Datasheet
Parameter Measurement Information, continued
Differential Measurement Points for Duty Cycle/Period
Single-ended Measurement Points for Delta Cross Point
Differential Measurement Points for Rise/Fall Edge Rate
Single-ended Measurement Points for Absolute Cross
Point/Swing
TSTABLE
VRB
+150mV
VRB = +100mV
0.0V
VRB = -100mV
-150mV
Q - nQ
VRB
TSTABLE
Differential Measurement Points for Ringback
©2016 Integrated Device Technology, Inc.
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841N4830 Datasheet
Applications Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 841N4830 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. VDD, VDD_OSC, VDDA, VDDO, and VDDOx should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10 resistor along with a 10F bypass
capacitor be connected to the VDDA pin.
3.3V
VDD
.01µF
10Ω
VDDA
10Ω
.01µF
10µF
VDDA
.01µF
10µF
Figure 1. Power Supply Filtering
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, HCSL and other differential
signals. Both VSWING and VOH must meet the VPP and VCMR input
requirements. Figures 2A to 2D show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
3.3V
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 2A, the input termination
applies for open emitter LVHSTL drivers. If you are using an LVHSTL
driver from another vendor, use their termination recommendation.
3.3V
*R3
CLK
nCLK
HCSL
*R4
Differential
Input
Figure 2A. CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Figure 2B. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2C. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input
Driven by a 3.3V LVDS Driver
©2016 Integrated Device Technology, Inc.
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841N4830 Datasheet
Crystal Input Interface
The 841N4830 has been characterized with 12pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 3 below were determined using a 25MHz, 12pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
XTAL_IN
C1
5pF
X1
12pF Parallel Crystal
XTAL_OUT
C2
5pF
Figure 3. Crystal Input Interface
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 4A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100. This can also be accomplished
by removing R1 and making R2 50. By overdriving the crystal
oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
3.3V
3.3V
R1
100
Ro ~ 7 Ohm
C1
Zo = 50 Ohm
XTAL_IN
RS
43
R2
100
Driv er_LVCMOS
0.1uF
XTAL_OUT
Cry stal Input Interf ace
Figure 4A. General Diagram for LVCMOS Driver to XTAL Input Interface
VCC=3.3V
C1
Zo = 50 Ohm
XTAL_IN
R1
50
Zo = 50 Ohm
0.1uF
XTAL_OUT
LVPECL
Cry stal Input Interf ace
R2
50
R3
50
Figure 4B. General Diagram for LVPECL Driver to XTAL Input Interface
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841N4830 Datasheet
Recommended Termination
Figure 5A is the recommended source termination for applications
where the driver and receiver will be on a separate PCBs. This
termination is the standard for PCI Express™ and HCSL output
0.5" Max
Rs
types. All traces should be 50 impedance single-ended or 100
differential.
0.5 - 3.5"
1-14"
0-0.2"
22 to 33 +/-5%
L1
L2
L4
L1
L2
L4
L5
L5
PCI Expres s
PCI Expres s
Connector
Driver
0-0.2"
L3
L3
PCI Expres s
Add-in Card
49.9 +/- 5%
Rt
Figure 5A. Recommended Source Termination (where the driver and receiver will be on separate PCBs)
Figure 5B is the recommended termination for applications where a
point-to-point connection can be used. A point-to-point connection
contains both the driver and the receiver on the same PCB. With a
matched termination at the receiver, transmission-line reflections will
0.5" Max
Rs
0 to 33
L1
be minimized. In addition, a series resistor (Rs) at the driver offers
flexibility and can help dampen unwanted reflections. The optional
resistor can range from 0 to 33. All traces should be 50
impedance single-ended or 100 differential.
0-18"
0-0.2"
L2
L3
L2
L3
0 to 33
L1
PCI Expres s
Driver
49.9 +/- 5%
Rt
Figure 5B. Recommended Termination (where a point-to-point connection can be used)
©2016 Integrated Device Technology, Inc.
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Revision F, May 23, 2016
841N4830 Datasheet
Recommendations for Unused Input Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVPECL Output
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
The unused LVPECL output pair can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
Crystal Inputs
LVCMOS Outputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
All unused LVCMOS output can be left floating. There should be no
trace attached.
Differential Outputs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.
functionality. These outputs are designed to drive 50 transmission
lines. Matched impedance techniques should be used to maximize
operating frequency and minimize signal distortion. Figures 6A and
6B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process variations.
The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
Figure 6A. 3.3V LVPECL Output Termination
©2016 Integrated Device Technology, Inc.
R2
84
Figure 6B. 3.3V LVPECL Output Termination
15
Revision F, May 23, 2016
841N4830 Datasheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 7. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 7. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
©2016 Integrated Device Technology, Inc.
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Revision F, May 23, 2016
841N4830 Datasheet
Schematic Example
Figure 8 shows an example of 841N4830 application schematic. The
schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure that the logic control inputs are
properly set.
power supply isolation is required. The 841N4830 provides separate
power supplies to isolate any high switching noise from coupling into
the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uf capacitor in each power pin filter should be placed on the device
side. The other components can be on the opposite side of the PCB.
In this example, the device is operated at VDD = VDDO_REF =
VDD_OSC = VDDO = 3.3V. The 12pF parallel resonant 25MHz crystal
is used. The C1 = 5pF and C2 = 5pF are recommended for frequency
accuracy. For different board layouts, the C1 and C2 may be slightly
adjusted for optimizing frequency accuracy. When designing the
circuit board, return the capacitors to ground though a single point
contact close to the package.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10 kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
Two examples of HCSL terminations are shown in this schematic.
The decoupling capacitors should be located as close as possible to
the power pin.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
©2016 Integrated Device Technology, Inc.
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Revision F, May 23, 2016
841N4830 Datasheet
3.3 V
3.3V
FB1
FB2
1
2
VD D
VDDO
2
BLM18 BB221 SN1
1
BLM18 BB221 SN1
C14
0. 1uF
C15
10uF
C17
10uF
C1 6
0. 1uF
3 .3V_Rec eive r
R1
1 33
C13
0. 1uF
C8
0. 1uF
R6
10
R2
133
Zo = 50 O hm
R3
4 75
REF_OUT
TL1
nOEA
+
Zo = 50 O hm
nREF_OUT
-
TL2
C3
0. 1uF
R8
10
LVPECL Termination
32
31
30
29
28
27
26
25
C9
10u
R4
8 2.5
R5
82.5
VDDA
VD D
nO EA
VDD O
IR EF
QA0
nQA0
G ND
U1
C4
10u
C5
0. 1u
1
2
3
4
5
6
7
8
PLL_ BYPASS
nREF_OE
nOEB
QB_DIV2
nCLK
Zo = 5 0
C7
0.1u F
VDDO
R14
50
VDDO
C12
0. 1uF
VDDO
C6
0. 1uF
R7
33
QA0
Zo = 50
33
nQA0
Zo = 50
R 10
50
QB
F
p
2
1
XTAL_ OUT
Use for PCI Express
Add-In Card
C11
0. 1uF
R2 1
HCSL Termination
10
C10
0 .1uF
Logic Control Input Examples
VDD
R1 1
50
VDDO
VDD
Set Logic
Input to '1'
-
2 5MHz
C2
5 pF
VDD
+
TL3
R9
XTAL_ IN
X1
C1
5pF
24
23
22
21
20
19
18
17
TL4
REF_OUT 9
nREF_ OUT 10
CLK_SEL 11
12
13
14
15
16
R 22
50
R2 3
50
L VPECL Dr ive r
QA1
n QA1
VDD O
QA2
n QA2
GN D
QA3
VDDO_ QA3
REF_OUT
nREF_ OUT
CL K_SEL
XTAL_IN
XTAL_ OUT
VDD_ OSC
VDDO_QB
QB
CLK
Zo = 5 0
PL L_BYPASS
nREF_ OE
nOEB
DIV2_QB
VDD A
CLK
nCLK
VDD O_REF
Optional
Set Logic
Input to '0 '
R1 6
33
QA2
Zo = 50
+
TL7
RU1
1K
RU2
Not Ins tall
To Logic
Input
pins
RD1
Not Ins tall
To Lo gic
Input
pins
R1 7
33
n QA2
V DD=VD DO=3.3 V
Zo = 50
-
TL8
V DDO_R EF= VD D_OSC=3. 3V
R18
50
V DDO_QA 3=VD DO_QB =3.3 V
R19
50
RD2
1K
Use for PCI Express
Point-to-Point Connection
R20
25
Zo = 50
QB
LVCMOS
Figure 8. 841N4830 Application Schematic
©2016 Integrated Device Technology, Inc.
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Revision F, May 23, 2016
841N4830 Datasheet
PCI Express Application Note
PCI Express jitter analysis methodology models the system
response to reference clock jitter. The block diagram below shows the
most frequently used Common Clock Architecture in which a copy of
the reference clock is provided to both ends of the PCI Express Link.
In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs
are modeled as well as the phase interpolator in the receiver. These
transfer functions are called H1, H2, and H3 respectively. The overall
system transfer function at the receiver is:
Ht s = H3 s H1 s – H2 s
The jitter spectrum seen by the receiver is the result of applying this
system transfer function to the clock spectrum X(s) and is:
Y s = X s H3 s H1 s – H2 s
In order to generate time domain jitter numbers, an inverse Fourier
Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].
PCIe Gen 2B Magnitude of Transfer Function
For a more thorough overview of PCI Express jitter analysis
methodology, please refer to IDT Application Note PCI Express
Reference Clock Requirements.
PCI Express Common Clock Architecture
For PCI Express Gen 2, two transfer functions are defined with 2
evaluation ranges and the final jitter number is reported in rms. The
two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz
(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the
individual transfer functions as well as the overall transfer function Ht.
PCIe Gen 2A Magnitude of Transfer Function
©2016 Integrated Device Technology, Inc.
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Revision F, May 23, 2016
841N4830 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 841N4830.
Equations and example calculations are also provided.
1.
Power Dissipation
The total power dissipation for the 841N4830 is the sum of the core power plus the power dissipated due to loading. The following is the power
dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results.
NOTE: Please refer to Section 3A and 3B for details on calculating power dissipation due to loading.
Core
•
Power(core) = VDD_MAX * IEE = 3.6V * 170mA = 612mW
LVPECL Output
LVPECL driver power dissipation is 30mW/Loaded output pair, total LVPECL output dissipation:
•
Power(LVPECL) = 30mW
HSCL Output
HSCL driver power dissipation is 46.8mW/Loaded output pair, total HSCL output dissipation:
•
Power(HSCL) = 46.75mW * 3 = 140.25mW
LVCMOS Output
•
Output Impedance ROUT Power Dissipation due to Loading 50 to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.6V / [2 * (50 + 25)] = 24mA
•
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 25 * (24mA)2 = 14.4mW per output
•
Total Power Dissipation on the ROUT
Total Power (ROUT) = 14.4mW * 2 = 28.8mW
Dynamic Power Dissipation at 100MHz
Power (100MHz) = CPD * Frequency * (VDD)2 = 5pF * 100MHz * (3.6V)2 = 6.48mW per output
Total Power (100MHz) = 6.48mW * 2 = 12.96mW
Total Power Dissipation
•
Total Power
= Power (core) + Power(LVPECL) + Power(HCSL) + Total Power (ROUT) + Total Power (100MHz)
= 612mW + 30mW + 140.25mW + 28.8mW +12.96mW
= 824mW
©2016 Integrated Device Technology, Inc.
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Revision F, May 23, 2016
841N4830 Datasheet
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature for devices is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures
that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 37.7°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.824W *37.7°C/W = 116°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
©2016 Integrated Device Technology, Inc.
0
1
2.5
37.7°C/W
32.9°C/W
29.5°C/W
21
Revision F, May 23, 2016
841N4830 Datasheet
3A. Calculations and Equations for LVPECL.
The purpose of this section is to calculate power dissipation on the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 9.
VDDO
Q1
VOUT
RL
VDDO - 2V
Figure 9. LVPECL Driver Circuit and Termination
To calculate power dissipation per output due to loading, use the following equations which assume a 50 load, and a termination voltage of
VDDO – 2V.
•
For logic high, VOUT = VOH_MAX = VDDO_MAX – 0.9V
(VCC_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VDDO_MAX – 1.7V
(VCC_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VDDO_MAX – 2V))/RL] * (VDDO_MAX – VOH_MAX) = [(2V – (VDDO_MAX – VOH_MAX))/RL] * (VDDO_MAX – VOH_MAX) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VDDO_MAX – 2V))/RL] * (VDDO_MAX – VOL_MAX) = [(2V – (VDDO_MAX – VOL_MAX))/RL] * (VDDO_MAX – VOL_MAX) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
©2016 Integrated Device Technology, Inc.
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Revision F, May 23, 2016
841N4830 Datasheet
3B. Calculations and Equations for HCSL.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pairs.
HCSL output driver circuit and termination are shown in Figure 10.
VDDO
IOUT = 17mA
➤
VOUT
RREF =
475Ω ± 1%
RL
50Ω
IC
Figure 10. HCSL Driver Circuit and Termination
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,
use the following equations which assume a 50 load to ground.
The highest power dissipation occurs when VDD_MAX.
Power
= (VDD_MAX – VOUT) * IOUT,
since VOUT – IOUT * RL
= (VDD_MAX – IOUT * RL) * IOUT
= (3.6V – 17mA * 50) * 17mA
Total Power Dissipation per output pair = 46.75mW
©2016 Integrated Device Technology, Inc.
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Revision F, May 23, 2016
841N4830 Datasheet
Reliability Information
Table 8. JA vs. Air Flow Table for a 32 Lead VFQFN
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
37.7°C/W
32.9°C/W
29.5°C/W
Transistor Count
The transistor count for 841N4830 is: 23,123
©2016 Integrated Device Technology, Inc.
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Revision F, May 23, 2016
841N4830 Datasheet
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
A3
N
L
N
Anvil
Anvil
Singulation
Singula tion
e (Ty p.)
2 If N & N
1
are Even
2
OR
E2
(N -1)x e
(Re f.)
E2
2
To p View
b
A
(Ref.)
D
e
D2
2
N &N
Odd
0. 08
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
C
D2
C
Bottom View w/Type A ID
Bottom View w/Type C ID
2
1
2
1
CHAMFER
4
Th er mal
Ba se
RADIUS
N N-1
4
N N-1
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
Table 9. Package Dimensions
Symbol
N
A
A1
A3
b
ND & NE
D&E
D2 & E2
e
L
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Minimum
Nominal
32
0.80
0
0.25 Ref.
0.18
0.25
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pin-out are shown on the front page. The
package dimensions are in Table 9.
Maximum
1.00
0.05
0.30
8
5.00 Basic
3.0
0.30
3.3
0.50 Basic
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
©2016 Integrated Device Technology, Inc.
25
Revision F, May 23, 2016
841N4830 Datasheet
Ordering Information
Table 10. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
841N4830BKILF
ICSN4830BIL
“Lead-Free” 32 Lead VFQFN
Tray
-40C to 85C
841N4830BKILFT
ICSN4830BIL
“Lead-Free” 32 Lead VFQFN
Tape & Reel, pin 1 orientation: EIA-481-C
-40C to 85C
841N4830BKILF/W
ICSN4830BIL
“Lead-Free” 32 Lead VFQFN
Tape & Reel, pin 1 orientation EIA-481-D
-40C to 85C
Table 11. Pin 1 Orientation in Tape and Reel Packaging
Part Number Suffix
Pin 1 Orientation
T
Quadrant 1 (EIA-481-C)
/W
Quadrant 2 (EIA-481-D)
©2016 Integrated Device Technology, Inc.
Illustration
26
Revision F, May 23, 2016
841N4830 Datasheet
Revision History Sheet
Rev
Table
A
B
T6A
T6C
Page
Description of Change
Date
4
Supply Voltage, VDD. Rating changed from 4.5V min. to 3.63V per Errata NEN-11-03.
5/3/11
1
General Description: Maximum rms phase jitter changed to 0.34ps
Per PCN:
Features: changed to: RMS Phase Jitter @ 100MHz, (12kHz – 20MHz) using a 25MHz
crystal: 0.34ps (maximum)
Added 0.34 Maximum to tjit RMS Phase Jitter.
Added 0.34 Maximum to tjit, RMS Phase Jitter., Added 0.582 Typical to tREFCLK_HF_RMS
RMS Phase Jitter. Added 0.023 Typical to tREFCLK_LF_RMS RMS Phase Jitter.
Added updated Phase Noise Plot.
Added updated PCI Express Application Note
Changed Package Drawing
Changed Marking to ICSN4830BIL.
3/5/12
Per PCN #N1206-01, changed IEE to 170mA Max.
Changed device reference to ICS841N4830BKI throughout the datasheet.
8/29/12
6
7
8
18
23
24
C
T4A
4
Per PCN #N1206-01
Updated VDD min/max voltage from 3.135V min/3.465V max to 3.0V min / 3.6V max.
Updated VDDO min/max voltage from 3.135V min/3.465V max to 2.7V min / 3.6V max.
1
D
4-7
4
T6A
6
LVCMOS AC Characteristic Table - changed odc min / max spec.
T6C
7
HCSL AC Characteristic Table - changed Phase Jitter, RMS (Random) max spec.;
changed Phase Jitter (HF_RMS) typical spec.;
changed Cycle-to-Cycle max spec.
9
Parameter Measurement Information - updated Test Circuit diagrams.
18
PCI Express Application Note - deleted Gen 1 information.
D
F
DC / AC Characteristic Tables - changed voltage supply table descriptions.
Power Supply DC Characteristics Table - changed Core supply voltage min / max specs;
changed VDDO supply voltage min / max specs;
corrected VDDA min spec from VDD - 0.16V to VDD - 0.32V.
T4A
19 - 20, 22
E
General Description and Features, updated RMS Phase Jitter spec to 0.36ps.
17, 18
T11
T10
26
26
1/22/2013
Power Considerations - changed VDD = 3.465V to VDD = 3.6V, updated equations.
Updated schematic
8/5/2013
Added P1 Orientation in Tape and Reel Table.
Ordering Information - Added W part number.
7/1/15
Updated datasheet header/footer.
5/23/16
©2016 Integrated Device Technology, Inc.
27
Revision F, May 23, 2016
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Sales
Tech Support
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www.idt.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications
and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein
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