841S012DI
Crystal-to-0.7V Differential HCSL/
LVCMOS Frequency Synthesizer
Datasheet
GENERAL DESCRIPTION
FEATURES
The 841S012DI is an optimized PCIe, sRIO and Gigabit Ethernet
Frequency Synthesizer and a member of high performance clock
solutions from IDT. The 841S012DI uses a 25MHz parallel resonant
crystal to generate 33.33MHz - 200MHz clock signals, replacing
multiple oscillators and fanout buffer solutions. The device supports
±0.25% center-spread, and -0.5% down-spread clocking with two
spread select pins (SSC[1:0]). The VCO operates at a frequency of
2GHz. The device has three output banks: Bank A with two 100MHz
– 250MHz HCSL outputs; Bank B with seven 33.33MHz – 200MHz
LVCMOS/ LVTTL outputs; and Bank C with one 33.33MHz – 200MHz
LVCMOS/LVTTL output.
• Two 0.7V differential HCSL outputs (Bank A), configurable for
PCIe (100MHz or 250MHz) and sRIO (100MHz or 125MHz)
clock signals
Eight LVCMOS/LVTTL outputs (Banks B/C),
18Ω typical output impedance
Two REF_OUT LVCMOS/LVTTL clock outputs,
23Ω typical output impedance
• Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or one LVCMOS/LVTTL single-ended reference clock input
• Supports the following output frequencies:
HCSL Bank A: 100MHz, 125MHz, 200MHz and 250MHz
LVCMOS/LVTTL Bank B/C: 33.33MHz, 50MHz, 66.67MHz,
100MHz, 125MHz, 133.33MHz, 166.67MHz and 200MHz
All Banks A, B and C have their own dedicated frequency
select pins and can be independently set for the frequencies
mentioned above. The low jitter characteristic of the 841S012DI
makes it an ideal clock source for PCIe, sRIO and Gigabit Ethernet
applications. Designed for networking and industrial applications,
the 841S012DI can also drive the high-speed clock inputs of communication processors, DSPs, switches and bridges.
• VCO: 2GHz
• Spread spectrum clock: ±0.25% center-spread (typical) and
-0.6% down-spread (typical)
• PLL bypass and output enable
• RMS period jitter: 10ps (typical), QAx/nQAx outputs
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
VDDOB
VDDOB
QB6
GND
QB5
VDDOB
QB4
GND
QB3
VDDOB
QB2
GND
QB1
QB0
PIN ASSIGNMENT
56 55 54 53 52 51 50 49 48 47 46 45 44 43
VDD_REFOUT
REF_OUT0
1
2
42
REF_OUT1
GND
GND
3
4
5
6
7
8
9
10
11
40
39
38
©2016 Integrated Device Technology, Inc
1
56-Lead VFQFN
8mm x 8mm x 0.925mm
package body
K Package
Top View
37
36
35
34
33
32
31
30
29
VDDOC
QC
GND
QBC_OE
VDDA
VDDA
GND
GND
IREF
QA0
nQA0
QA1
nQA1
VDD
GND
VDD
F_SELB2
F_SELB1
F_SELB0
F_SELC2
F_SELC1
F_SELC0
F_SELA1
F_SELA0
QA_OE
12
13
14
15 16 17 18 19 20 21 22 23 24 25 26 27 28
GND
REF_OE
nMR
VDD
ICS841S012DI
SSC1
SSC0
REF_IN
VDD
REF_SEL
XTAL_IN
XTAL_OUT
BYPASS
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841S012DI Datasheet
BLOCK DIAGRAM
QA_OE
Pullup
F_SELA[1:0]
Pulldown
BYPASS
Pulldown
2
QA0
nQA0
÷NA
25MHz
XTAL_IN
OSC
nQA1
1
0
PLL
VCO
XTAL_OUT
QB0
2GHz
REF_IN
Pulldown
REF_SEL
Pulldown
QA1
0
1
QB1
QB2
M = ÷80
QB3
÷NB
QB4
F_SELB[2:0]
Pulldown
3
QB5
IREF
QB6
÷NC
F_SELC[2:0]
Pulldown
nMR
Pullup
QBC_OE
Pullup
SSC[1:0]
Pullup
QC
3
2
Spread
Spectrum
REF_OUT0
REF_OUT1
REF_OE
Pulldown
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841S012DI Datasheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VDD_REFOUT
Power
Output supply pin for REF_OUT.
7, 14, 28, 29
VDD
Power
Core supply pins.
2,
3
4, 5, 15, 27, 35,
36, 40, 46, 50,
54
REF_OUT0,
REF_OUT1
Output
Single-ended LVCMOS/LVTTL reference clock outputs.
23Ω typical output impedance.
GND
Power
Power supply ground.
6
REF_IN
Input
8
REF_SEL
Input
9,
10
XTAL_IN, XTAL_
OUT
Input
11
BYPASS
Input
12
REF_OE
Input
13
nMR
Input
16,
17
18,
19,
20
21,
22,
23
24,
25
SSC1,
SSC0
F_SELB2, F_
SELB1,
F_SELB0
F_SELC2, F_
SELC1,
F_SELC0
F_SELA1, F_
SELA0
26
Pulldown Single-ended LVCMOS/LVTTL reference clock input.
Reference select pin. When HIGH selects REF_IN. When LOW,
selects crystal. LVCMOS/LVTTL interface levels. See Table 3E.
Crystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input.
External tuning capacitor must be used for proper operation.
When HIGH bypasses PLL. When LOW, selects PLL.
Pulldown
LVCMOS/LVTTL interface levels. See Table 3J.
Active HIGH REF_OUT enables/disables pin.
Pulldown
LVCMOS/LVTTL interface levels. See Table 3H.
Active LOW Master Reset. When logic LOW, the internal dividers are reset
and the outputs are in high impedance (HI-Z). When logic HIGH, the internal
Pullup
dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels. See Table 3I.
Pulldown
Input
Pullup
Input
Pulldown
Frequency select pins for QBx outputs. See Table 3B.
LVCMOS/LVTTL interface levels.
Input
Pulldown
Frequency select pins for QC output. See Table 3C.
LVCMOS/LVTTL interface levels.
Input
Pulldown
QA_OE
Input
Pullup
30, 31
32, 33
nQA1, QA1
nQA0, QA0
Output
Differential Bank A clock outputs. HCSL interface levels.
34
IREF
Output
External fixed precision resistor (475Ω) from this pin to ground provides a
reference current used for differential current-mode QAx/nQAx clock outputs.
37, 38
VDDA
Power
Analog supply pin.
39
QBC_OE
Input
41
QC
Output
42
VDDOC
Power
Output supply pin for QC LVCMOS output.
43, 48, 52, 56
VDDOB
Power
Output supply pins for QBx LVCMOS outputs.
44, 45,
47, 49,
51, 53, 55
QB0, QB1, QB2,
QB3, QB4, QB5, Output
QB6
Pullup
SSC control pin. LVCMOS/LVTTL interface levels. See Table 3D.
Frequency select pins for QAx/nQAx outputs. See Table 3A.
LVCMOS/LVTTL interface levels.
Output enable pin for Bank A outputs. See Table 3F. LVCMOS/LVTTL interface levels.
Output enable pin for Bank B and Bank C outputs.
LVCMOS/LVTTL Interface levels. See Table 3G.
Single-ended Bank C clock output. LVCMOS/LVTTL interface levels.
18Ω typical output impedance.
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.
18Ω typical output impedance.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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841S012DI Datasheet
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
CIN
Input Capacitance
CPD
Power Dissipation
Capacitance
QB[0:6], QC
Minimum
Typical
VDD, VDD_REFOUT, VDDOB, VDDOC = 3.465V
Maximum
Units
4
pF
19
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
ROUT
Output Impedance
QB[0:6], QC
18
Ω
REF_OUT[1:0]
23
Ω
TABLE 3A. F_SELA FREQUENCY SELECT FUNCTION TABLE
Inputs
Output Frequency (25MHz Ref.)
F_SELA1
F_SELA0
M Divider Value
NA Divider Value
QA[0:1]/nQA[0:1] (MHz)
L
L
80
20
100 (default)
L
H
80
16
125
H
L
80
10
200
H
H
80
8
250
TABLE 3B. F_SELB FREQUENCY SELECT FUNCTION TABLE
Inputs
F_SELB2
F_SELB1
F_SELB0
Output Frequency (25MHz Ref.)
M Divider Value
NB Divider Value
QB[0:6] (MHz)
L
L
L
80
60
33.33 (default)
L
L
H
80
40
50
L
H
L
80
30
66.67
L
H
H
80
20
100
H
L
L
80
16
125
H
L
H
80
15
133.33
H
H
L
80
12
166.67
H
H
H
80
10
200
TABLE 3C. F_SELC FREQUENCY SELECT FUNCTION TABLE
Inputs
F_SELC2
F_SELC1
F_SELC0
Output Frequency (25MHz Ref.)
M Divider Value
NC Divider Value
QC (MHz)
L
L
L
80
60
33.33 (default)
L
L
H
80
40
50
L
H
L
80
30
66.67
L
H
H
80
20
100
H
L
L
80
16
125
H
L
H
80
15
133.33
H
H
L
80
12
166.67
H
H
H
80
10
200
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841S012DI Datasheet
TABLE 3D. SSC FUNCTION TABLE
TABLE 3E. REF_SEL FUNCTION TABLE
Input
Input
SSC1
SSC0
Mode
0
0
0 to -0.5% Down-spread
0
XTAL
0
1
±0.25% Center-spread
1
REF_IN
1
0
±0.25% Center-spread
1
1
SSC Off (default)
REF_SEL
TABLE 3F. QA_OE FUNCTION TABLE
Input Reference
TABLE 3G. QBC_OE FUNCTION TABLE
Input
QA_OE
0
1(default)
Input
Function
QBC_OE
QA[0:1]/nQA[0:1] disabled (High-Impedance)
0
QA[0:1]/nQA[0:1] enabled
Function
QB[0:6] and QC disabled (High-Impedance)
1 (default) QB[0:6] and QC enabled
TABLE 3H. REF_OE FUNCTION TABLE
TABLE 3I. nMR FUNCTION TABLE
Input
REF_OE
Input
Function
nMR
0 (default) REF_OUT[0:1] disabled (High-Impedance
1
0
REF_OUT[0:1] enabled
Function
Device reset, output divider disabled
(High-Impedance)
1 (default) Output enabled
NOTE: This device requires a reset signal after power-up to
function properly.
TABLE 3J. BYPASS FUNCTION TABLE
Input
BYPASS
Function
0 (default) PLL
1
Bypass (reference ÷N)
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841S012DI Datasheet
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA
31.4°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDD_REFOUT = VDDOB = VDDOC = 3.3V±5%, TA = -40°C TO 85°C
Symbol
VDD
Parameter
Core Supply Voltage
VDDA
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
Units
V
Analog Supply Voltage
VDD – 0.20
3.3
VDD
V
VDDOB, VDDOC
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
300
mA
IDDA
Analog Supply Current
20
mA
HCSL Loaded, LVCMOS No Load
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDD_REFOUT = VDDOB = VDDOC = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
Input
High Current
Input
Low Current
Test Conditions
QA_OE, QBC_OE,
nMR, SSC0, SSC1,
F_SELA[0:1], F_
SELB[0:2].
F_SELC[0:2],
REF_OE, BYPASS,
REF_IN, REF_SEL
Minimum
Typical
Maximum
Units
2
VDD + 0.3
V
-0.3
0.8
V
VDD = VIN = 3.465V
10
µA
VDD = VIN = 3.465V
150
µA
QA_OE, QBC_OE,
nMR, SSC0, SSC1,
VDD = 3.465V, VIN = 0V
-150
µA
F_SELA[0:1], F_
SELB[0:2].
F_SELC[0:2],
REF_OE, BYPASS,
REF_IN, REF_SEL
VDD = 3.465V, VIN = 0V
-10
µA
2.6
V
VOH
Output High Voltage
VDDOB, VDDOC = IOH = -2mA
VOL
Output Low Voltage
VDDOB, VDDOC = IOL = 2mA
0.5
V
Maximum
Units
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Mode of Oscillation
Minimum
Typical
Fundamental
Frequency
25
Equivalent Series Resistance (ESR)
MHz
50
Shunt Capacitance
Drive Level
Ω
7
pF
100
µW
NOTE: Characterized using an 18pF parallel resonant crystal.
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841S012DI Datasheet
TABLE 6. AC CHARACTERISTICS, VDD = VDD_REFOUT = VDDOB = VDDOC = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
QB[0:6]
fOUT
Output Frequency
33.33
QA[0:1]/nQA[0:1]
Bank Skew;
NOTE 1, 2
MHz
250
MHz
MHz
QB[0:6]
50
ps
QA[0:1]/nQA[0:1]
50
ps
160
ps
65
ps
10
ps
20
ps
20
ps
29
33.33
kHz
1200
mV
tjit(cc)
Cycle-to-Cycle
Jitter; NOTE 1
QA[0:1]/nQA[0:1]
across Banks B and C
(at Same Frequency)
All Outputs at Same Frequency
QA[0:1]/nQA[0:1]
QB[0:6]
REF_OE = 0, All Outputs
at Same Frequency
tjit(per)
RMS Period Jitter
FM
SSC Modulation
Frequency
VHIGH
Voltage High; NOTE 4, 5
580
VLOW
Voltage Low; NOTE 4, 6
-150
QC
Banks A, B, C
ΔVCROSS
Absolute Crossing Voltage;
NOTE 4, 7, 8
Total Variation of VCROSS over all edges;
NOTE 4, 7, 9
tR / tF
Output Rise/Fall
Time
Output Duty Cycle
Units
200
200
Output Skew; NOTE 1, 3
odc
Maximum
100
tsk(o)
VCROSS
Typical
33.33
QC
tsk(b)
Minimum
Bank A
Banks B, C
200
mV
600
mV
200
mV
±150mV from crosspoint
25
100
ps
20% - 80%
0.4
1.3
ns
45
55
%
Bank A
Banks B, C
42
58
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDOB, C/2.
NOTE 4: Measurement taken from single-ended waveform.
NOTE 5: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information
Section.
NOTE 6: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information
Section.
NOTE 7: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of
nQx. See Parameter Measurement Information Section.
NOTE 8: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Parameter Measurement Information Section.
NOTE 9: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the VCROSS for any particular system. See Parameter Measurement Information Section.
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841S012DI Datasheet
PARAMETER MEASUREMENT INFORMATION
3.3V CORE/3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
RMS PERIOD JITTER
HCSL OUTPUT SKEW
LVCMOS OUTPUT SKEW
LVCMOS BANK SKEW
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841S012DI Datasheet
PARAMETER MEASUREMENT INFORMATION, CONTINUED
DIFFERENTIAL CYCLE-TO-CYCLE JITTER
LVCMOS RISE/FALL TIME
SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT
SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS
POINT AND SWING
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE/PERIOD
DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME
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841S012DI Datasheet
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 841S012DI
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, VDDOB, and
V DDOC should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be
used for each pin. Figure 1 illustrates this for a generic VDD pin
and also shows that VDDA requires that an additional10Ω resistor
along with a 10µF bypass capacitor be connected to the VDDA pin.
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
LVCMOS OUTPUTS
All unused LVCMOS output can be left floating. We recommend that
there is no trace attached.
DIFFERENTIAL OUTPUTs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
REF_IN INPUT
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_IN to ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
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841S012DI Datasheet
CRYSTAL INPUT INTERFACE
The 841S012DI has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2 below
were determined using a 25MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error. NOTE: External tuning
capacitors must be used for proper operations.
XTAL_IN
C1
15pF
X1
18pF Parallel Crystal
XTAL_OUT
C2
22pF
FIGURE 2. CRYSTAL INPUT INTERFACE
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS signals, it
is recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be done
in one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1 and
R2 can be 100Ω. This can also be accomplished by removing R1
and making R2 50Ω. By overdriving the crystal oscillator, the device
will be functional, but note the device performance is guaranteed
by using a quartz crystal.
VDD
VDD
R1
Ro
.1uf
Rs
Zo = 50
Zo = Ro + Rs
XTAL_IN
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
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841S012DI Datasheet
SPREAD SPECTRUM
Spread-spectrum clocking is a frequency modulation technique for
EMI reduction. When spread-spectrum is enabled, a 32kHz triangle
waveform is used with 0.6% down-spread (+0.0% / -0.5%) from
the nominal output frequency. An example of a triangle frequency
modulation profile is shown in Figure 4A below. The ramp profile
can be expressed as:
The 841S012DI triangle modulation frequency deviation will not
exceed 0.7% down-spread from the nominal clock frequency (+0.0%
/ -0.5%). An example of the amount of down spread relative to the
nominal clock frequency can be seen in the frequency domain,
as shown in Figure 4B. The ratio of this width to the fundamental
frequency is typically 0.4%, and will not exceed 0.7%. The resulting
spectral reduction will be greater than 5dB, as shown in Figure 4B. It
is important to note the 841S012DI 5dB minimum spectral reduction
is the component-specific EMI reduction, and will not necessarily
be the same as the system EMI reduction.
Fnom = Nominal Clock Frequency in Spread OFF mode
Fm = Nominal Modulation Frequency (30kHz)
δ = Modulation Factor (0.6% down spread)
➤
(1 - δ) fnom + 2 Fm x δ x Fnom x t when 0 < t < 1,
2Fm
(1 - δ) fnom - 2 Fm x δ x Fnom x t when 1 < t < 1
2Fm
Fm
Fnom
Frequency
Δ − 10 dBm
B
A
(1 - δ) Fnom
1/fm
➤
0.5/fm
➤
δ = .6% ➤
Time
FIGURE 4A. TRIANGLE FREQUENCY MODULATION
FIGURE 4B. 200MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN
(A) SPREAD-SPECTRUM OFF (B) SPREAD-SPECTRUM ON
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841S012DI Datasheet
VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on
the package, as shown in Figure 5. The solderable area on the PCB,
as defined by the solder mask, should be at least the same size/
shape as the exposed pad/slug area on the package to maximize
the thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
specific and dependent upon the package power dissipation as well
as electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern.
It is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This
is desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used as a
guideline only. For further information, refer to the Application Note
on the Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern
must be connected to ground through these vias. The vias act as
“heat pipes”. The number of vias (i.e. “heat pipes”) are application
FIGURE 5. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
©2016 Integrated Device Technology, Inc
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841S012DI Datasheet
RECOMMENDED TERMINATION
Figure 6A is the recommended termination for applications which
require the receiver and driver to be on a separate PCB. All traces
should be 50Ω impedance.
FIGURE 6A. RECOMMENDED TERMINATION
Figure 6B is the recommended termination for applications
which require a point to point connection and contain the
driver and receiver on the same PCB. All traces should all be 50Ω
impedance.
FIGURE 6B. RECOMMENDED TERMINATION
©2016 Integrated Device Technology, Inc
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841S012DI Datasheet
SCHEMATIC EXAMPLE
Figure 7 shows an example of the 841S012DI application schematic.
In this example, the device is operated at VD D= VDDOB = VDDOC = 3.3V.
The 18pF parallel resonant 25MHz crystal is used. The C1= 33pF
and C2 = 33pF are recommended for frequency accuracy. For
different board layouts, the C1 and C2 may be slightly adjusted
for optimizing frequency accuracy. Two examples of HCSL and
one example of LVCMOS termination are shown in this schematic.
The decoupling capacitors should be located as close as possible
to the power pin.
Logic Control Input Examples
R1
35
Zo = 50
QB0
Set Logic
Input to '1'
VDD
Set Logic
Input to '0'
VDD
VDD
R2
10
LVCMOS
VDDA
RU1
1K
RU2
Not Install
VDDO
C5
10u
C6
0.01u
VDD
To Logic
Input
pins
To Logic
Input
pins
RD2
1K
R4
REF_OUT0
REF_OUT1
Q1
Zo = 50 Ohm
REF_IN
43
REF_SEL
C1
15pF
BY PASS
REF_OE
nMR
X1
XTAL_OUT
GND
SSC1
SSC0
F_SELB2
F_SELB1
F_SELB0
F_SELC2
F_SELC1
F_SELC0
F_SELA1
F_SELA0
QA_OE
GND
VDD
Note: External tuning
capacitors must be used for
proper operation.
XTAL_IN
VDD_REFOUT
REF_OUT0
REF_OUT1
GND
GND
REF_IN
VDD
REF_SEL
XTAL_IN
XTAL_OUT
BY PASS
REF_OE
nMR
VDD
C2
22pF
ICS841S012DI
C3
0.01u
C4
10u
VDDOC
QC
GND
QBC_OE
VDDA
VDDA
GND
GND
IREF
QA0
nQA0
QA1
nQA1
VDD
42
41
40
39
38
37
36
35
34
33
32
31
30
29
R5
33
R7
33
Zo = 50
+
TL3
Zo = 50
IREF
-
TL5
QA0
nQA0
R8
50
QA1
R9
50
Using for PCI Express
Add-In Card
R10
475 Ohm
15
16
17
18
19
20
21
22
23
24
25
26
27
28
25MHz, CL=18pF
Driv er_LVCMOS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
10
VDDA
VDDOB
QB6
GND
QB5
VDDOB
QB4
GND
QB3
VDDOB
QB2
GND
QB1
QB0
VDDOB
U1
R6
Zo = 50
LVCMOS
VDD
Ro ~ 7 Ohm
30
VDD
VDDO
56
55
54
53
52
51
50
49
48
47
46
45
44
43
RD1
Not Install
R3
REF_OUT1
HCSL Termination
SSC1
SSC0
F_SELB2
F_SELB1
F_SELB0
F_SELC2
F_SELC1
F_SELC0
F_SELA1
F_SELA0
QA_OE
Note: This device requires a
reset signal at nMR after
power-up to function properly.
Zo = 50
+
TL6
nQA1
VDDO
VDD=3.3V
(U1, 42) VDDO
VDD
(U1, 43)
(U1, 48)
(U1, 52)
(U1, 56)
(U1, 1)
VDD
0.1u
C8
0.1u
C9
0.1u
C10
0.1u
C11
0.1u
C12
0.1u
-
TL7
(U1, 7)
(U1, 14)
(U1, 28)
R11
50
(U1, 29)
VDDO=3.3V
C7
Zo = 50
C13
C14
0.1u
0.1u
C15
0.1u
C16
R12
50
Using for PCI Express
Point-to-Point
Connection
0.1u
FIGURE 7. 841S012DI SCHEMATIC EXAMPLE
©2016 Integrated Device Technology, Inc
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841S012DI Datasheet
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 841S012DI.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 841S012DI is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
Core and HCSL Output Power Dissipation
The maximum IDD current at 85° is 284mA. The HCSL output current (17mA per output pair) is included in this value. For power
considerations, this output current is treated separately from the core currents, so for power calculations,
IDD = 284mA - 2 * 17mA = 250mA.
•
Power (core) = VDD_MAX * (IDD + IDDA ) = 3.465V * (250mA + 20mA) = 935.6mW
Power (HCSL) = 44.5mW/Load Output Pair
If all outputs are loaded, the total power is 2 * 44.5mW = 89mW
LVCMOS Output Power Dissipation
• Dynamic Power Dissipation at 200MHz, (QB, QC)
Power (200MHz) = CPD * Frequency * (VDDO)2 = 19pF * 200MHz * (3.465V)2 = 45mW per output
Total Power (200MHz) = 45mW * 8 = 360mW
•
Dynamic Power Dissipation at 25MHz, (REF_OUT)
Power (25MHz) = CPD * Frequency * (VDDO)2 = 19pF * 25MHz * (3.465V)2 = 5.6mW per output
Total Power (25MHz) = 5.6mW * 2 = 11.2mW
Total Power Dissipation
•
Total Power
= Power (core) + Power (HCSL) + Total Power (200MHz) + Total Power (25MHz)
= 935.6mW + 89mW + 360mW + 11mW
= 1396mW
©2016 Integrated Device Technology, Inc
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841S012DI Datasheet
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming 1
meter per second air flow and a multi-layer board, the appropriate value is 27.5°C/W per Table 7.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.396W * 27.5°C/W = 123.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 56 LEAD VFQFN, FORCED CONVECTION
θJA by Velocity (Meters per second)
Multi-Layer PCB, JEDEC Standard Test Boards
©2016 Integrated Device Technology, Inc
17
0
1
2.5
31.4°C/W
27.5°C/W
24.6°C/W
January 4, 2016
841S012DI Datasheet
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 8.
VDD
IOUT = 17mA
VOUT
RREF =
475 ± 1%
RL
50
IC
FIGURE 8. HCSL DRIVER CIRCUIT AND TERMINATION
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power
dissipation, use the following equations which assume a 50Ω load to ground.
The highest power dissipation occurs at maximum VDD .
Power
= (VDD_MAX – VOUT ) * IOUT,
since VOUT = IOUT * RL
= (VDD_MAX – IOUT * RL) * IOUT
= (3.465V – 17mA * 50Ω) * 17mA
Total Power Dissipation per output pair = 44.5mW
©2016 Integrated Device Technology, Inc
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841S012DI Datasheet
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 56 LEAD VFQFN
θJA by Velocity (Meters per second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
31.4°C/W
27.5°C/W
24.6°C/W
TRANSISTOR COUNT
The transistor count for 841S012DI is: 11,537
©2016 Integrated Device Technology, Inc
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January 4, 2016
841S012DI Datasheet
PACKAGE OUTLINE - K SUFFIX FOR 56 LEAD VFQFN
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 9 below.
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
N
MAXIMUM
56
A
0.80
1.0
A1
0
0.05
A3
b
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
14
NE
14
D
D2
8.0
4.35
E
4.65
8.0
E2
5.05
5.35
L
0.3
0.55
Reference Document: JEDEC Publication 95, MO-220
©2016 Integrated Device Technology, Inc
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January 4, 2016
841S012DI Datasheet
TABLE 10. ORDERING INFORMATION
Part/Order Number
841S012DKILF
841S012DKILFT
Marking
ICS841S012DIL
ICS841S012DIL
©2016 Integrated Device Technology, Inc
Package
56 lead “Lead-Free” VFQFN
56 lead “Lead-Free” VFQFN
21
Shipping Packaging
tray
tape & reel
Temperature
-40°C to 85°C
-40°C to 85°C
January 4, 2016
841S012DI Datasheet
REVISION HISTORY SHEET
Rev
Table
Page
1
A
Description of Change
Removed ICS chip and Hiperclocks from the General Description.
Removed ICS from the part number.
Updated data sheet header and footer.
©2016 Integrated Device Technology, Inc
22
Date
1/4/16
January 4, 2016
841S012DI Datasheet
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