841S101
Crystal-to-HCSL, 100MHz PCI Express™
Clock Synthesizer
General Description
Features
The 841S101 is a PLL-based clock synthesizer specifically designed
for PCI_Express™ Clock applications. This device generates a
100MHz differential HCSL clock from a input reference of 25MHz.
The input reference may be derived from an external source or by the
addition of a 25MHz crystal to the on-chip crystal oscillator. An
external reference is applied to the XTAL_IN pin with the XTAL_OUT
pin left floating.The device offers spread spectrum clock output for
reduced EMI applications. An I2C bus interface is used to enable or
disable spread spectrum operation as well as select either a down
spread value of -0.35% or -.5%.The 841S101 is available in a
lead-free 16-Lead TSSOP package.
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Datasheet
One 0.7V current mode differential HCSL output pair
Crystal oscillator interface: 25MHz
Output frequency: 100MHz
RMS phase jitter @ 100MHz (12kHz – 20MHz): 1.23ps (typical)
Cycle-to-cycle jitter: 20ps (maximum)
I2C support with readback capabilities up to 400kHz
Spread Spectrum for electromagnetic interference (EMI) reduction
3.3V operating supply mode
-40°C to 85°C ambient operating temperature
Available in a lead-free (RoHS 6) package
PCI Express Gen 1, 2 and 3 jitter compliant
HiPerClockS™
Block Diagram
XTAL_IN
Pin Assignment
VSS
SRCT0
VDD
1
2
SRCC0
SRCT0
SRCC0
VD D
VSS
3
4
5
6
IREF
VSS
7
8
25MHz
OSC
PLL
XTAL_OUT
SDATA
Pullup
SCLK
Pullup
Divider
Network
I2C
Logic
IREF
©2016 Integrated Device Technology, Inc.
16
15
14
13
12
11
10
9
VD D
SDATA
SCLK
XTAL_ OUT
XTAL_IN
VD D
VSS
VD DA
841S101
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
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Revision B, May 25, 2016
841S101 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 6, 8, 10
VSS
Power
Power supply ground.
2, 5, 11, 16
VDD
Power
Power supply pins.
3, 4
SRCT0, SRCC0
Output
Differential output pair. HCSL interface levels.
7
IREF
Input
9
VDDA
Power
12, 13
XTAL_IN,
XTAL_OUT
Input
14
SCLK
Input
Pullup
I2C compatible SCLK. This pin has an internal pullup resistor. Open drain.
LVCMOS/LVTTL interface levels.
15
SDATA
I/O
Pullup
I2C compatible SDATA. This pin has an internal pullup resistor.
LVCMOS/LVTTL interface levels.
An external fixed precision resistor (475) from this pin to ground provides a
reference current used for differential current-mode SRCCx, SRCTx clock
outputs.
Analog supply for PLL.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
2
pF
RPULLUP
Input Pullup Resistor
51
k
©2016 Integrated Device Technology, Inc.
Test Conditions
2
Minimum
Typical
Maximum
Units
Revision B, May 25, 2016
841S101 Datasheet
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a
two-signal I2C serial interface is provided. Through the Serial Data
Interface, various device functions, such as clock output buffers, can
be individually enabled or disabled. The registers associated with the
serial interface initialize to their default setting upon power-up, and
therefore, use of this interface is optional. Clock device register
changes are normally made upon system initialization, if any are
required.
Data Protocol
The clock driver serial protocol accepts bye write, byte read, block
write and block read operations from the controller. For block
write/read operation, the bytes must be accessed is sequential order
from lowest to highest byte (most significant bit first) with the ability to
stop after any complete byte has been transferred. For byte write and
byte read operations, the system controller can access individually
indexed bytes. The offset of the indexed byte is encoded in the
command code, as described in Table 3A.
The block write and block read protocol is outlined in Table 3B, while
Table 3C outlines the corresponding byte write and byte read
protocol. The slave receiver address is 11010010 (D2h).
Table 3A.Command Code Definition
Bit
7
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation.
6:5
Chip select address, set to “00” to access device.
4:0
Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be “00000”.
©2016 Integrated Device Technology, Inc.
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841S101 Datasheet
Table 3B. Block Read and Block Write Protocol
Bit
1
2:8
Description = Block Write
Start
Slave address - 7 bits
Bit
Description = Block Read
1
Start
2:8
Slave address - 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code - 8 bits
11:18
Command Code - 8 bits
Acknowledge from slave
19
Acknowledge from slave
Byte Count - 8 bits
20
Repeat start
19
20:27
28
29:36
37
38:45
46
Acknowledge from slave
Data byte 1 - 8 bits
Acknowledge from slave
Data byte 2 - 8 bits
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N - 8 bits
Acknowledge from slave
Stop
21:27
Slave address - 7 bits
28
Read = 1
29
Acknowledge from slave
30:37
Byte Count from slave - 8 bits
38
Acknowledge
39:46
Data Byte 1 from slave - 8 bits
47
Acknowledge
48:55
Data Byte 2 from slave - 8 bits
56
Acknowledge
Data Bytes from Slave/Acknowledge
Data Byte N from slave - 8 bits
Not Acknowledge
Table 3C. Byte Read and Byte Write Protocol
Bit
1
2:8
Description = Byte Write
Start
Slave address - 7 bits
Bit
Description = Byte Read
1
Start
2:8
Slave address - 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code - 8 bits
11:18
Command Code - 8 bits
Acknowledge from slave
19
Acknowledge from slave
Data Byte - 8 bits
20
Repeat start
19
20:27
28
Acknowledge from slave
29
Stop
©2016 Integrated Device Technology, Inc.
21:27
Slave address - 7 bits
28
Read
29
Acknowledge from slave
30:37
Data from slave - 8 bits
38
Not Acknowledge
39
Stop
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Revision B, May 25, 2016
841S101 Datasheet
Control Registers
Table 3D. Byte 0: Control Register 0
Bit
@Pup
Name
7
0
Reserved
6
1
5
1
4
Table 3G. Byte 3:Control Register 3
Description
Bit
@Pup
Name
Description
Reserved
7
1
Reserved
Reserved
Reserved
Reserved
6
0
Reserved
Reserved
Reserved
Reserved
5
1
Reserved
Reserved
1
Reserved
Reserved
4
0
Reserved
Reserved
3
1
Reserved
Reserved
3
1
Reserved
Reserved
1
Reserved
Reserved
1
SRC[T/C]0
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z)
1 = Enable
2
2
1
1
Reserved
Reserved
1
0
Reserved
Reserved
0
1
Reserved
Reserved
0
0
Reserved
Reserved
NOTE: Pup denotes Power-up.
Table 3H. Byte 4: Control Register 4
Table 3E. Byte 1: Control Register 1
Bit
@Pup
Name
Description
Bit
@Pup
Name
Description
7
0
Reserved
Reserved
7
0
Reserved
Reserved
6
0
Reserved
Reserved
6
0
Reserved
Reserved
5
0
Reserved
Reserved
5
0
Reserved
Reserved
0
Reserved
Reserved
4
0
Reserved
Reserved
4
3
0
Reserved
Reserved
3
0
Reserved
Reserved
2
0
Reserved
Reserved
2
0
Reserved
Reserved
1
0
Reserved
Reserved
1
0
Reserved
Reserved
Reserved
0
1
Reserved
Reserved
0
0
Reserved
Table 3I. Byte 5: Control Register 5
Table 3F. Byte 2: Control Register 2
Bit
@Pup
Name
Description
Spread Spectrum Selection
0 = -0.35%, 1 = - 0.5%
7
0
Reserved
Reserved
6
0
Reserved
Reserved
Reserved
Reserved
5
0
Reserved
Reserved
1
Reserved
Reserved
4
0
Reserved
Reserved
0
Reserved
Reserved
3
0
Reserved
Reserved
1
Reserved
Reserved
2
0
Reserved
Reserved
SRC Spread Spectrum Enable
0 = Spread Off,
1 = Spread On
1
0
Reserved
Reserved
0
0
Reserved
Reserved
Bit
@Pup
Name
7
1
SRCT/C
6
1
5
4
3
Description
2
0
SRC
1
1
Reserved
Reserved
0
1
Reserved
Reserved
©2016 Integrated Device Technology, Inc.
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Revision B, May 25, 2016
841S101 Datasheet
Table 3J. Byte 6: Control Register 6
Bit
@Pup
Name
7
0
TEST_SEL
Table 3K. Byte 7: Control Register 7
Description
Bit
@Pup
Name
Description
REF/N or Hi-Z Select
0 = Hi-Z, 1 = REF/N
7
0
Revision Code Bit 3
6
0
Revision Code Bit 2
TEST Clock Mode Entry
Control
0 = Normal Operation,
1 = REF/N or Hi-Z Mode
5
0
Revision Code Bit 1
4
0
Revision Code Bit 0
6
0
TEST_MODE
3
0
Vendor ID Bit 3
5
0
Reserved
Reserved
2
0
Vendor ID Bit 2
4
1
Reserved
Reserved
1
0
Vendor ID Bit 1
3
0
Reserved
Reserved
0
1
Vendor ID Bit 0
2
0
Reserved
Reserved
1
1
Reserved
Reserved
0
1
Reserved
Reserved
NOTE: Pup denotes Power-up.
©2016 Integrated Device Technology, Inc.
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Revision B, May 25, 2016
841S101 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.5V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, JA
86.9C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
VDD – 0.22
3.3
VDD
V
IDD
Power Supply Current
80
mA
IDDA
Analog Supply Current
22
mA
Maximum
Units
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VIH
Input High Voltage
SDATA, SCLK
2.2
VDD + 0.3
V
VIL
Input Low Voltage
SDATA, SCLK
-0.3
0.8
V
IIH
Input High Current
SDATA, SCLK
VDD = VIN = 3.465V
10
µA
IIL
Input Low Current
SDATA, SCLK
VDD = 3.465V, VIN = 0V
-150
µA
Table 5. Crystal Characteristics
Parameter
Test Conditions
Mode of Oscillation
Minimum
Typical
Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
©2016 Integrated Device Technology, Inc.
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Revision B, May 25, 2016
841S101 Datasheet
AC Electrical Characteristics
Table 6A. PCI Express Jitter Specifications, VDD = 3.3V±5%, TA = -40°C to 85°C
Typical
Maximum
PCIe Industry
Specification
Units
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
13.3
19.3
86
ps
tREFCLK_HF_RMS Phase Jitter RMS;
NOTE 2, 4
(PCIe Gen 2)
ƒ = 100MHz, 25MHz Crystal Input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
1.1
1.53
3.1
ps
tREFCLK_LF_RMS
(PCIe Gen 2)
Phase Jitter RMS;
NOTE 2, 4
ƒ = 100MHz, 25MHz Crystal Input
Low Band: 10kHz - 1.5MHz
0.19
0.32
3.0
ps
tREFCLK_RMS
(PCIe Gen 3)
Phase Jitter RMS;
NOTE 3, 4
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
0.18
0.30
0.8
ps
Parameter
Symbol
tj
(PCIe Gen 1)
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
Test Conditions
Minimum
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the
datasheet.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen
1 is 86ps peak-to-peak for a sample size of 106 clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS
(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
©2016 Integrated Device Technology, Inc.
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Revision B, May 25, 2016
841S101 Datasheet
Table 6B. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
100
MHz
fREF
Reference frequency
25
MHz
tjit(Ø)
Phase Jitter, RMS (Random);
NOTE 1
25MHz crystal, ƒ = 100MHz,
Integration Range: 12kHz – 20MHz
1.23
ps
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 2
PLL Mode
tL
PLL Lock Time
FM
SSC Modulation Frequency;
NOTE 4
SSCRED
Spectral Reduction; NOTE 4
VRB
Ring-back Voltage Margin;
NOTE 4, 5
VMAX
Absolute Max. Output Voltage;
NOTE 6, 7
VMIN
Absolute Min. Output Voltage;
NOTE 6, 8
-300
VCROSS
Absolute Crossing Voltage;
NOTE 6, 9, 10
250
VCROSS
Total Variation of VCROSS over
all edges; NOTE 6, 9, 11
Rise/Fall Edge Rate;
NOTE 6, 12
odc
25MHz Crystal
30
32
-7
-10
-100
Measured between 150mV to +150mV
Output Duty Cycle
20
ps
55
ms
33.33
kHz
dB
100
mV
1150
mV
mV
550
mV
140
mV
0.6
4.0
V/ns
48
52
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Characterized using a 25MHz quartz crystal.
NOTE 1: Refer to phase jitter plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Spread Spectrum clocking enabled.
NOTE 4: Measurement taken from differential waveform.
NOTE 5: TSTABLE is the time the differential clock must maintain a minimum ± 150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100mV differential range.
NOTE 6: Measurement taken from single-ended waveform.
NOTE 7: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 8: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 9: Measured at crossing point where the instantaneous voltage value of the rising edge of SRCT equals the falling edge of SRCC.
NOTE 10: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement.
NOTE 11: Defined as the total variation of all crossing voltages of rising SRCT and falling SRCC, This is the maximum allowed variance in
Vcross for any particular system.
NOTE 12: Measured from -150mV to +150mV on the differential waveform (SRCT minus SRCC). The signal must be monotonic through the
measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
©2016 Integrated Device Technology, Inc.
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Revision B, May 25, 2016
841S101 Datasheet
Noise Power dBc
Hz
Typical Phase Noise at 100MHz
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc.
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Revision B, May 25, 2016
841S101 Datasheet
Parameter Measurement Information
3.3V±5
3.3V±5
3.3V±5
3.3V±5
VDD
Measurement
Point
VDD
VDDA
VDDA
2pF
Measurement
Point
IREF
GND
2pF
0V
This load condition is used for IDD, tjit(cc) and tjit(Ø)
measurements.
0V
3.3V HCSL Output Load AC Test Circuit
3.3V HCSL Output Load AC Test Circuit
SRCC0
SRCT0
tcycle n
tcycle n+1
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
Cycle-to-Cycle Jitter
RMS Phase Jitter
VMAX
SRCC
SRCC
VCROSS_MAX
VCROSS
VCROSS_MIN
SRCT
SRCT
VMIN
Single-ended Measurement Points for Absolute Cross
Point and Swing
©2016 Integrated Device Technology, Inc.
Single-ended Measurement Points for Delta Cross Point
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Revision B, May 25, 2016
841S101 Datasheet
Parameter Measurement Information, continued
TSTABLE
Rise Edge Rate
VRB
+150mV
VRB = +100mV
0.0V
VRB = -100mV
-150mV
Fall Edge Rate
+150mV
0.0V
-150mV
SRCC SRCT
SRCT SRCC
VRB
TSTABLE
Differential Measurement Points for Rise/Fall Edge Rate
Differential Measurement Points for Ringback
Clock Period (Differential)
Positive Duty
Cycle (Differential)
Negative Duty
Cycle (Differential)
0.0V
SRCT SRCC
Differential Measurement Points for Duty Cycle/Period
©2016 Integrated Device Technology, Inc.
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Revision B, May 25, 2016
841S101 Datasheet
Applications Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 841S101 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. VDD and VDDA should be individually connected
to the power supply plane through vias, and 0.01µF bypass
capacitors should be used for each pin. Figure 1 illustrates this for a
generic VDD pin and also shows that VDDA requires that an additional
10 resistor along with a 10F bypass capacitor be connected to the
VDDA pin.
3.3V
VDD
.01µF
10Ω
.01µF
10µF
VDDA
Figure 1. Power Supply Filtering
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
©2016 Integrated Device Technology, Inc.
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Revision B, May 25, 2016
841S101 Datasheet
Crystal Input Interface
The 841S101 has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 2 below
were determined using a 25MHz, 18pF parallel resonant crystal and
were chosen to minimize the ppm error. The optimum C1 and C2
values can be slightly adjusted for different board layouts.
XTAL_IN
C1
33p
X1
18pF Parallel Crystal
XTAL_OUT
C2
18p
Figure 2. Crystal Input Interface
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100. This can also be
accomplished by removing R1 and making R2 50. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
3.3V
3.3V
R1
100
Ro ~ 7 Ohm
C1
Zo = 50 Ohm
XTAL_IN
RS
43
R2
100
Driv er_LVCMOS
0.1uF
XTAL_OUT
Cry stal Input Interf ace
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
VCC=3.3V
C1
Zo = 50 Ohm
XTAL_IN
R1
50
Zo = 50 Ohm
0.1uF
XTAL_OUT
LVPECL
Cry stal Input Interf ace
R2
50
R3
50
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
©2016 Integrated Device Technology, Inc.
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Revision B, May 25, 2016
841S101 Datasheet
Recommended Termination
Figure 4A is the recommended termination for applications which
require the receiver and driver to be on a separate PCB. All traces
should be 50Ω impedance.
Figure 4A. Recommended Termination
Figure 4B is the recommended termination for applications which
require a point to point connection and contain the driver and receiver
on the same PCB. All traces should all be 50Ω impedance.
Figure 4B. Recommended Termination
©2016 Integrated Device Technology, Inc.
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Revision B, May 25, 2016
841S101 Datasheet
PCI Express Application Note
PCI Express jitter analysis methodology models the system
response to reference clock jitter. The block diagram below shows
the most frequently used Common Clock Architecture in which a
copy of the reference clock is provided to both ends of the PCI
Express Link.
In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs
are modeled as well as the phase interpolator in the receiver. These
transfer functions are called H1, H2, and H3 respectively. The overall
system transfer function at the receiver is:
Ht s = H3 s H1 s – H2 s
The jitter spectrum seen by the receiver is the result of applying this
system transfer function to the clock spectrum X(s) and is:
Y s = X s H3 s H1 s – H2 s
PCIe Gen 2A Magnitude of Transfer Function
In order to generate time domain jitter numbers, an inverse Fourier
Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].
PCI Express Common Clock Architecture
PCIe Gen 2B Magnitude of Transfer Function
For PCI Express Gen 1, one transfer function is defined and the
evaluation is performed over the entire spectrum: DC to Nyquist (e.g
for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is
reported in peak-peak.
For PCI Express Gen 3, one transfer function is defined and the
evaluation is performed over the entire spectrum. The transfer
function parameters are different from Gen 1 and the jitter result is
reported in RMS.
PCIe Gen 1 Magnitude of Transfer Function
PCIe Gen 3 Magnitude of Transfer Function
For PCI Express Gen 2, two transfer functions are defined with 2
evaluation ranges and the final jitter number is reported in rms. The
two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz
(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the
individual transfer functions as well as the overall transfer function Ht.
©2016 Integrated Device Technology, Inc.
For a more thorough overview of PCI Express jitter analysis
methodology, please refer to IDT Application Note PCI Express
Reference Clock Requirements.
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Revision B, May 25, 2016
841S101 Datasheet
Schematic Layout
Figure 5 shows an example of 841S101 application schematic. In this
example, the device is operated at VDD = 3.3V. The 18pF parallel
resonant 25MHz crystal is used. The C1 =18pF and C2 = 33pF are
recommended for frequency accuracy. For different board layouts,
the C1 and C2 may be slightly adjusted for optimizing frequency
accuracy. Two examples of HCSL termination are shown in this
schematic. The decoupling capacitors should be located as close as
possible to the power pin.
R1
33
SRCT0
Zo = 50
+
TL1
R2
33
SRCC0
Zo = 50
-
TL2
VDD
VDD
R3
50
8
7
6
5
4
3
2
1
IREF
Recommended for PCI
Express Add-In Card
U1
VSS
IREF
VSS
VDD
SRCC0
SRCT0
VDD
VSS
R5
R4
50
475 Ohm
HCSL Termination
9
10
11
12
13
14
15
16
VDDA
VSS
VDD
XTAL_IN
XTAL_OUT
SCLK
SDATA
VDD
VDD=3.3V
VDD
Zo = 50
VDDA
+
VDD
TL3
R6
10
C3
VDD
C4
0.01u
10uF
Zo = 50
-
TL4
C1
18pF
R9
SP
R7
50
R10
SP
R8
50
Recommended for PCI
Express Point-to-Point
Connection
SCLK
SDATA
X1
F
p
8
1
25MHz
C2
33pF
VDD
VDD
J1
R11
5 SDA
4
3
2
SCL
1
R12
(U1-2)
0
0
VDD
C5
0.1uF
(U1-5)
C6
0.1uF
(U1-11)
C7
0.1uF
(U1-16)
C8
0.1uF
Figure 5. 841S101 Application Schematic.
©2016 Integrated Device Technology, Inc.
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Revision B, May 25, 2016
841S101 Datasheet
Spread Spectrum
Spread-spectrum clocking is a frequency modulation technique for
EMI reduction. When spread-spectrum is enabled, a 32kHz triangle
waveform is used with 0.5% down-spread from the nominal 100MHz
clock frequency. An example of a triangle frequency modulation
profile is shown in Figure 6A below.
amount of down spread relative to the nominal clock frequency can
be seen in the frequency domain, as shown in Figure 6B. The ratio of
this difference to the fundamental frequency is typically 0.5%. The
resulting spectral reduction will be greater than 7dB, as shown in
Figure 2B. It is important to note the 841S101 7dB minimum spectral
reduction is the component-specific EMI reduction, and will not
necessarily be the same as the system EMI reduction.
➤
The 841S101 triangle modulation frequency deviation is 0.5%
down-spread from the nominal clock frequency. An example of the
Fnom
(1 - δ) Fnom
0.5/fm
➤
1/fm
Figure 6A. Triangle Frequency Modulation
– 7dBm
A
B
➔
➔
= 0.25%
Figure 6B. 100MHz Clock Output In Frequency Domain
(A) Spread-Spectrum OFF
(B) Spread-Spectrum ON
©2016 Integrated Device Technology, Inc.
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Revision B, May 25, 2016
841S101 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 841S101.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 841S101 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
The maximum current at 85°C is as follows:
IDD_MAX = 73mA
IDDA_MAX = 19mA
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V *(73mA + 19mA) = 318.78mW
•
Power (outputs)MAX = 44.5mW/Loaded Output pair
Total Power_MAX = 318.78mW + 44.5mW = 363.28mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 86.9°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.363W * 86.9°C/W = 116.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
©2016 Integrated Device Technology, Inc.
0
1
2.5
86.9°C/W
82.5°C/W
80.4°C/W
19
Revision B, May 25, 2016
841S101 Datasheet
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 7.
VDD
IOUT = 17mA
VOUT
RREF =
475 ± 1%
RL
50
IC
Figure 7. HCSL Driver Circuit and Termination
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,
use the following equations which assume a 50 load to ground.
The highest power dissipation occurs when VDD_MAX.
Power
= (VDD_MAX – VOUT) * IOUT,
since VOUT – IOUT * RL
= (VDD_MAX – IOUT * RL) * IOUT
= (3.465V – 17mA * 50) * 17mA
Total Power Dissipation per output pair = 44.5mW
©2016 Integrated Device Technology, Inc.
20
Revision B, May 25, 2016
841S101 Datasheet
Reliability Information
Table 8. JA vs. Air Flow Table for a 16 Lead TSSOP
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
86.9°C/W
82.5°C/W
80.4°C/W
Transistor Count
The transistor count for 841S101 is: 11,775
Package Outline and Package Dimensions
Package Outline - G Suffix for 16 Lead TSSOP
Table 9. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
16
A
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
5.10
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
©2016 Integrated Device Technology, Inc.
21
Revision B, May 25, 2016
841S101 Datasheet
Ordering Information
Table 10. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
841S101EGILF
1S101EIL
“Lead-Free” 16 Lead TSSOP
Tube
-40C to 85C
841S101EGILFT
1S101EIL
“Lead-Free” 16 Lead TSSOP
Tape & Reel
-40C to 85C
©2016 Integrated Device Technology, Inc.
22
Revision B, May 25, 2016
841S101 Datasheet
Revision History Sheet
Rev
Table
Page
A
10
21
Ordering Information Table - corrected marking.
6/24/10
10
22
Ordering Information Table - deleted Tape & Reel count and table note.
Updated datasheet header/footer.
Deleted “ICS” prefix, “I” suffix from part number
5/25/16
B
Description of Change
©2016 Integrated Device Technology, Inc.
Date
23
Revision B, May 25, 2016
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