8427DY-02LFT

ICS8427-02 500MHZ, LOW JITTER LVCMOS/CRYSTALTO-LVHSTL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS8427-02 is a general purpose, six LVHSTL ICS output high frequency synthesizer and a member HiPerClockS™ of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS8427-02 can support a very wide output frequency range of 15.625MHz to 500MHz. The device powers up at a default output frequency of 200MHz with a 16.6667MHz crystal interface, and the frequency can then be changed using the serial programming interface to change the M feedback divider and N output divider. Frequency steps as small as 125kHz can be achieved using a 16.6667MHz crystal and the output divider set for ÷16. The low jitter and frequency range of the ICS8427-02 make it an ideal clock generator for most clock tree applications. • Six differential LVHSTL outputs • Selectable crystal input interface or TEST_CLK input • TEST_CLK accepts the following input types: LVCMOS, LVTTL • Output frequency range: 15.625MHz to 500MHz • VCO range: 250MHz to 500MHz • Serial interface for programming feedback and output dividers • Supports SSC, -0.5% downspread. Can be enabled through use of the serial programming interface. • Output skew: 100ps (maximum) • Cycle-to-cycle jitter: 50ps (maximum) • 2.5V core/1.8V output supply voltage • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT VCO_SEL XTAL_IN VDD VCO_SEL FOUT0 1 nFOUT0 OSC VDDO 0 XTAL_IN FOUT1 nFOUT1 XTAL_SEL TEST_CLK 32 31 30 29 28 27 26 25 XTAL_OUT ÷ 16 PLL PHASE DETECTOR VCO MR ÷M 0 1 ÷2 ÷ 1, ÷ 2, ÷ 4, ÷ 8, ÷ 16 FOUT0 nFOUT0 FOUT1 nFOUT1 4 21 VDDA FOUT3 5 20 S_LOAD nFOUT3 6 19 S_DATA OE 7 18 S_CLOCK GND 8 17 MR ICS8427-02 9 10 11 12 13 14 15 16 GND 1 XTAL_SEL VDDO nFOUT5 IDT ™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER TEST 22 FOUT5 S_CLOCK CONFIGURATION INTERFACE LOGIC 3 VDDO S_DATA TEST_CLK nFOUT2 nFOUT4 OE S_LOAD FOUT5 nFOUT5 XTAL_OUT 23 FOUT4 FOUT4 nFOUT4 24 2 VDD FOUT3 nFOUT3 1 TEST FOUT2 nFOUT2 VDDO FOUT2 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 32-Lead VFQFN 5mm x 5mm x 0.75mm package body K Package Top View ICS8427DY-02 REV A OCTOBER 13, 2006 ICS8427-02 500MHZ, LOW JITTER, LVCMOS/CRYSSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes operation using a 16.6667MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 6 NOTE 1. The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 16.6667MHz reference are defined as 120 ≤ M ≤ 240. The frequency out is defined as follows: fout = fVCO = fxtal x 2M N 16 N The ICS8427-02 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a 16.6667MHz crystal, this provides a 1.0417MHz reference frequency. The VCO of the PLL operates over a range of 250MHz to 500MHz. The output of the M divider is also applied to the phase detector. Serial operation occurs when S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N outputdivider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The ICS8427-02 powers up by default to 200MHz output frequency, using a 16.6667MHz crystal (M = 192, N = 2). The output frequency can be changed after power-up by using the serial interface to program the M feedback divider and the N output divider. T1 T0 0 0 1 1 0 1 0 1 TEST Output (Power-up Default) LOW S_Data, Shift Register Input Output of M divider CMOS Fout The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x 2M 16 S_CLOCK T1 S_DATA t S_LOAD S T0 N2 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 SSC t H t Time S FIGURE 1. SERIAL LOAD OPERATIONS NOTE: Default Output Frequency, using a 16.6667MHz crystal on power-up = 200MHz (M = 192, N = 2) SSC off IDT ™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 2 ICS8427DY-02 REV A OCTOBER 13, 2006 ICS8427-02 500MHZ, LOW JITTER, LVCMOS/CRYSSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER M AND N DIVIDERS, SSC AND TEST MODE CONTROL BITS Test Mode Control Register N Divider ➤➤ M Divider ➤➤ ➤ T1 T0 N2 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 SSC ➤ ➤ ➤ ➤ ➤ ➤ ➤ ➤ ➤ ➤ ➤ ➤ ➤ ➤ ➤➤ ➤ ➤ SSC Control Register ➤ S_DATA ➤ T1 T0 N2 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 SSC Data transfer from shift register to M and N dividers and SSC and Test Control Bits on a low-to-high transition of S_LOAD. Shift Register TEST Output T1:T0 = 01 TABLE 1. SSC FUNCTION TABLE SSC 0 1 SSC State Off (power-up default) 0.5% down-spread ICS8427-02 SHIFT REGISTER OPERATION – READ BACK CAPABILITY 1. Device powers up by default in Test Mode 01. The Test Output in this case is wired to the shift register. 2. Shift in serial data stream and latch into M, N, T1, T0 and SSC Control Bits. Shift in T1:T0=00, so that the TEST Output will be turned off after the bits are shifted in and latched. T1 TEST Output T0 N2 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 SSC S_CLOCK T1 S_DATA t S_LOAD S T0 N2 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 SSC t H Time t S Data transferred to M, N dividers, TEST and SSC Control Bits. Changes to M, N, SSC and TEST mode bits take affect at this time. Data latched into M, N Dividers, TEST and SSC control bits. IDT ™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 3 ICS8427DY-02 REV A OCTOBER 13, 2006 ICS8427-02 500MHZ, LOW JITTER, LVCMOS/CRYSSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER TABLE 2. PIN DESCRIPTIONS Number Name 1, 4, 13, 30 VDDO FOUT2, nFOUT2 FOUT3, nFOUT3 2, 3 5, 6 Type Description Power Output supply pins. Output Differential output pair. HSTL interface levels. Output Differential output pair. HSTL interface levels. 7 OE Input 8 , 16 GND Power 9 TEST Output 1 0, 26 VDD FOUT4, nFOUT4 FOUT5, nFOUT5 Power Active High output enable. When HIGH, the outputs are enabled. When LOW, FOUTx = Low, nFOUTx = High. LVCMOS/LVTTL interface levels. Power supply ground. Test output which is ACTIVE in the serial mode of operation. LVCMOS/LVTTL interface levels. Core supply pins. Output Differential output pair. HSTL interface levels. Output Differential output pair. HSTL interface levels. 11, 12 14, 15 17 MR Input 18 S_CLOCK Input 19 S_DATA Input 20 S_LOAD Input 21 VDDA Power 22 23 24, 25 27 XTAL_SEL TEST_CLK XTAL_OUT, XTAL_IN VCO_SEL Input Input Input Input Pullup Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inver ted Pulldown outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Input clock to load serial S_DATA into the shift register. Pullup LVCMOS/LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of Pullup S_CLOCK. LVCMOS/LVTTL interface levels. Controls transition of data from shift register into the dividers. Pulldown LVCMOS/LVTTL interface levels. Analog supply pin. Selects between XTAL input or test input as the PLL reference Pullup source. Selects XTAL input when HIGH. Selects TEST_CLK when LOW. LVCMOS/LVTTL interface levels. Pulldown Test clock input. LVCMOS/LVTTL interface levels. Cr ystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Determines whether synthesizer is in PLL or bypass mode. Pullup LVCMOS/LVTTL interface levels. FOUT0, Output Differential output pair. HSTL interface levels. nFOUT0 FOUT1, 31, 32 Output Differential output pair. HSTL interface levels. nFOUT1 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 28, 29 TABLE 3. PIN CHARACTERISTICS Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor IDT ™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER Test Conditions 4 Minimum Typical 4 51 51 Maximum Units pF kΩ kΩ ICS8427DY-02 REV A OCTOBER 13, 2006 ICS8427-02 500MHZ, LOW JITTER, LVCMOS/CRYSSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER TABLE 4A. CONTROL INPUT FUNCTION TABLE Inputs OE XTAL_SEL Outputs Selected Source FOUT0:FOUT5 nFOUT0:nFOUT5 0 0 TEST_CLK Disabled; LOW Disabled; HIGH 0 1 XTAL_IN, XTAL_OUT Disabled; LOW Disabled; HIGH 1 0 TEST_CLK Enabled Enabled 1 1 XTAL_IN, XTAL_OUT Enabled Enabled After OE switches, the clock outputs are disabled or enabled following a rising and falling VCO edge as shown in Figure 2. nVCO Enabled Disabled VCO OE nFOUT0:5 FOUT0:5 FIGURE 2. OE TIMING DIAGRAM IDT ™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 5 ICS8427DY-02 REV A OCTOBER 13, 2006 ICS8427-02 500MHZ, LOW JITTER, LVCMOS/CRYSSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER TABLE 4B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLENOTE 1 120 256 M8 0 128 M7 0 64 M6 1 32 M5 1 16 M4 1 8 M3 1 4 M2 0 2 M1 0 1 M0 0 121 122 • 192 • 239 240 0 0 • 0 • 0 0 0 0 • 1 • 1 1 1 1 • 1 • 1 1 1 1 • 0 • 1 1 1 1 • 0 • 0 1 1 1 • 0 • 1 0 0 0 • 0 • 1 0 0 1 • 0 • 1 0 1 0 • 0 • 1 0 VCO Frequency (MHz) M Divide 250 252.08 254.17 • 400 • 497.92 500 NOTE 1: These M divide values and the resulting frequencies correspond to an input frequency of 16.6667MHz. TABLE 4C. SERIAL MODE FUNCTION TABLE Inputs Conditions MR S_LOAD S_CLOCK S_DATA H X X X L L X X L L ↑ Data L ↑ L Data Reset. Forces outputs differential LOW. FOUTx = Low, nFOUTx = High. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. L ↓ L Data M divider and N output divider values are latched. L L X X L H Data ↑ NOTE: L = LOW H = HIGH X = Don't care ↑ = Rising edge transition ↓ = Falling edge transition Serial input do not affect shift registers. S_DATA passed directly to M divider as it is clocked. TABLE 4D. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE N2 0 Input N1 0 0 0 1 4 62.5 125 0 1 0 8 31.25 62.5 31.25 N0 0 N Divider Value 2 Output Frequency (MHz) Minimum Maximum 125 250 0 1 1 16 15.625 1 0 0 1 25 0 500 1 0 1 2 125 250 1 1 0 4 62.5 125 1 1 1 8 31.25 62.5 IDT ™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 6 ICS8427DY-02 REV A OCTOBER 13, 2006 ICS8427-02 500MHZ, LOW JITTER, LVCMOS/CRYSSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the -0.5V to VDD + 0.5V device. These ratings are stress specifications only. Functional op- Outputs, IO Continuous Current Surge Current 50mA 100mA eration of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not Package Thermal Impedance, θJA for 32 Lead LQFP 47.9°C/W (0 lfpm) for 32 Lead VFQFN 34.8°C/W (0 lfpm) implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. -65°C to 150°C Storage Temperature, TSTG TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Minimum Typical Maximum Units VDD Core Supply Parameter Test Conditions 2.375 2.5 2.625 V VDDA Analog Voltage 2.375 2.5 2.625 V VDDO Output Voltage 1.6 1.8 IDD Power Supply Current IDDA Analog Supply Current IDD0 Output Supply Current No Load 2.0 V 175 mA 15 mA 0 mA TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 1.7 VDD + 0.3 V VIL Input Low Voltage -0.3 0.7 V IIH Input High Current IIL Input Low Current MR, S_LOAD, TEST_CLK VDD = VIN = 2.625V 150 µA XTAL_SEL, VCO_SEL, S_CLOCK, S_DATA, OE VDD = VIN = 2.625V 5 µA MR, S_LOAD, TEST_CLK VDD = 2.625V, VIN = 0V -5 µA XTAL_SEL, VCO_SEL, S_CLOCK, S_DATA, OE VDD = 2.625V, VIN = 0V -150 µA 1. 5 V Output TEST; NOTE 1 High Voltage Output TEST; NOTE 1 VOL Low Voltage NOTE 1: Outputs terminated with 50Ω to VDDO/2. VOH IDT ™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 0.4 7 V ICS8427DY-02 REV A OCTOBER 13, 2006 ICS8427-02 500MHZ, LOW JITTER, LVCMOS/CRYSSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER TABLE 5C. LVHSTL DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 0.9 1.3 V VOL Output Low Voltage; NOTE 1 0 0.4 V VOX Output Crossover Voltage; NOTE 2 40 60 % 1. 1 V Peak-to-Peak Output Voltage Swing 0.6 VSWING NOTE 1: Outputs terminated with 50Ω to GND. See 2.5V Output Load Test Circuit figure in the Parameter Measurement Information section. NOTE 2: Defined with respect to output voltage swing at a given condition. TABLE 6. CRYSTAL CHARACTERISTICS Parameter Test Conditions Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Minimum Typical Maximum Units Fundamental 12 40 50 MHz Ω Shunt Capacitance 7 pF Drive Level 1 mW TABLE 7. INPUT CHARACTERISTICS, VDD = VDDA = 2.5V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum VCO select = 1 12 Typical Maximum Units 40 MHz 400 MHz 40 MHz S_CLOCK 50 MHz TEST_CLK 5 ns TEST_CLK VCO select = 0 (bypass mode) fIN tr_INPUT Input Frequency XTAL; NOTE 1 Input Rise Time 12 NOTE 1: For the crystal frequency range the M value must be set to achieve the minimum or maximum VCO frequency range of 250MHz or 500MHz. Using the minimum frequency of 12MHz valid values of M are 167 ≤ M ≤ 256. Using the maximum frequency of 40MHz valid values of M are 50 ≤ M ≤ 100. IDT ™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 8 ICS8427DY-02 REV A OCTOBER 13, 2006 ICS8427-02 500MHZ, LOW JITTER, LVCMOS/CRYSSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER TABLE 8. AC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter FMAX Output Frequency tjit(cc) tjitt(T50) Test Conditions Cycle-to-Cycle Jitter ; NOTE 1, 3 T50 Cycle Jitter tjit(per) Period Jitter, RMS; NOTE 1 tsk(o) Output Skew; NOTE 2, 3 FM FMF SSCred Refspur SSC Modulation Frequency; NOTE 4, 5 SSC Modulation Factor ; NOTE 4, 5 Spectral Reduction; NOTE 4, 5 Reference Spur tR / tF Output Rise/Fall Time tS Setup Time tH Hold Time odc Output Duty Cycle tLOCK PLL Lock Time Minimum Typical Maximum Units 500 MHz FOUT = 200MHz 30 50 ps FOUT = 267MHz 30 50 ps FOUT = 333MHz 30 50 ps FOUT = 400MHz 30 50 ps FOUT = 200MHz 200 ps FOUT = 267MHz 200 ps FOUT = 333MHz 200 ps FOUT = 400MHz 200 ps 5 ps 2.5 100 ps FOUT = 200MHz 30 65 33.33 kHz FOUT = 267MHz 30 33.33 kHz FOUT = 333MHz 30 33.33 kHz FOUT = 400MHz 30 33.33 kHz FOUT = 200MHz 0.3 0. 6 % FOUT = 267MHz 0.4 0.6 % FOUT = 333MHz 0.3 0. 6 % FOUT = 400MHz 0.3 0. 6 % FOUT = 200MHz -7 -10 dB FOUT = 267MHz -7 -12 dB FOUT = 333MHz -7 -11 dB FOUT = 400MHz -7 -12 dB FOUT = 200MHz -40 dB FOUT = 267MHz -40 dB FOUT = 333MHz -45 dB FOUT = 400MHz -50 dB 20% to 80% 333 667 ps S_DATA to S_CLOCK 5 S_CLOCK to S_LOAD 5 ns ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns N=1 40 60 % N=2 45 55 % 1 ms See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Spread Spectrum clocking enabled. NOTE 5: Using a 16.6667MHz quar tz cr ystal. IDT ™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 9 ICS8427DY-02 REV A OCTOBER 13, 2006 ICS8427-02 500MHZ, LOW JITTER, LVCMOS/CRYSSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2.5V±5% 1.8V±0.2V 2.5V±5% nFOUTx VDD VDDO SCOPE Qx FOUTx VDDA nFOUTy FOUTy LVHSTL t sk(o) nQx GND 0V 2.5V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW nFOUT0:5 nFOUT0:5 FOUT0:5 FOUT0:5 ➤ tcycle n ➤ tcycle n+1 Period n + 50 Period n ➤ Period n + 50 + 50 tjit (50) = Period n – Period n +50 Minimum 16,667 consective cycles 334 measurements ➤ t jit(cc) = tcycle n –tcycle n+1 1000 Cycles T50 CYCLE-TO-CYCLE JITTER CYCLE-TO-CYCLE JITTER VOH Reference Spur dBm VREF VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Reference Point (Trigger Edge) (First edge after trigger) Frequency SPUR REDUCTION IDT ™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER Histogram Mean Period PERIOD JITTER 10 ICS8427DY-02 REV A OCTOBER 13, 2006 ICS8427-02 500MHZ, LOW JITTER, LVCMOS/CRYSSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER nFOUT0:5 V OH 60% V OX 50% nFOUT0:5 FOUT0:5 t PW 40% t V OL odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT CROSSOVER VOLTAGE 80% 80% VSW I N G Clock Outputs 20% 20% tR tF OUTPUT RISE/FALL TIME IDT ™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 11 ICS8427DY-02 REV A OCTOBER 13, 2006 ICS8427-02 500MHZ, LOW JITTER, LVCMOS/CRYSSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8427-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 3 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VDDA pin. 2.5V VDD .01µF 10Ω VDDA .01µF 10µF FIGURE 3. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. OUTPUTS: LVHSTL OUTPUT All unused LVHSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. TEST_CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the TEST_CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT ™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 12 ICS8427DY-02 REV A OCTOBER 13, 2006 ICS8427-02 500MHZ, LOW JITTER, LVCMOS/CRYSSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER CRYSTAL INPUT INTERFACE resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS8427-02 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 4 below were determined using a 16.66MHz, 18pF parallel XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p Figure 4. CRYSTAL INPUt INTERFACE LVCMOS TO XTAL INTERFACE the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 5. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals VDD VDD R1 Ro .1uf Rs Zo = 50 Zo = Ro + Rs XTAL_IN R2 XTAL_OUT FIGURE 5. GENERAL DIAGRAM FOR LVCMOS DRIVER IDT ™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 13 TO XTAL INPUT INTERFACE ICS8427DY-02 REV A OCTOBER 13, 2006 ICS8427-02 500MHZ, LOW JITTER, LVCMOS/CRYSSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER THERMAL RELEASE PATH solder as shown in Figure 6. For further information, please refer to the Application Note on Surface Mount Assembly of Amkor’s Thermally /Electrically Enhance Leadframe Base Package, Amkor Technology. The expose metal pad provides heat transfer from the device to the P.C. board. The expose metal pad is ground pad connected to ground plane through thermal via. The exposed pad on the device to the exposed metal pad on the PCB is contacted through EXPOSED PAD SOLDER M ASK SOLDER SIGNAL TRACE SIGNAL TRACE GROUND PLANE Expose Metal Pad THERM AL VIA FIGURE 6. P.C. BOARD FOR (GROUND PAD) EXPOSED PAD THERMAL RELEASE PATH EXAMPLE SPREAD SPECTRUM Spread-spectrum clocking is a frequency modulation technique for EMI reduction. When spread-spectrum is enabled, a 32.55kHz triangle waveform is used with 0.5% down-spread (+0.0% / -0.5%) from the nominal 200MHz clock frequency. An example of a triangle frequency modulation profile is shown in Figure 5A below. The ramp profile can be expressed as: The ICS8427-02 triangle modulation frequency deviation will not exceed 0.6% down-spread from the nominal clock frequency (+0.0% / -0.5%). An example of the amount of down spread relative to the nominal clock frequency can be seen in the frequency domain, as shown in Figure 7B. The ratio of this width to the fundamental frequency is typically 0.4%, and will not exceed 0.6%. The resulting spectral reduction will be greater than 7dB, as shown in Figure 7B. It is important to note the ICS8427-02 7dB minimum spectral reduction is the component-specific EMI reduction, and will not necessarily be the same as the system EMI reduction. • Fnom = Nominal Clock Frequency in Spread OFF mode (200MHz with 16.6667MHz IN) • Fm = Nominal Modulation Frequency = Reference Frequency 16 x 32 • δ = Modulation Factor (0.5% down spread) ➤ (1 - δ) fnom + 2 fm x δ x fnom x t when 0 < t < 1 , 2 fm 1 (1 - δ) fnom - 2 fm x δ x fnom x t when