843001AG-21LFT-HT

FemtoClocks™ Crystal-to-3.3V LVPECL Frequency Synthesizer 843001-21 DATA SHEET Description Features The 843001-21 is a a highly versatile, low phase noise LVPECL Synthesizer which can generate low jitter reference clocks for a variety of communications applications. The dual crystal interface allows the synthesizer to support up to two communications standards in a given application (i.e. 1GB Ethernet with a 25MHz crystal and 1Gb Fibre Channel using a 26.5625MHz crystal). The rms phase jitter performance is typically less than 1ps, thus making the device acceptable for use in demanding applications such as OC48 SONET and 10Gb Ethernet. The 843001-21 is packaged in a small 24-pin TSSOP package. • One 3.3Vdifferential LVPECL output pair and one LVCMOS/LVTTL single-ended reference clock output • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • • VCO range: 560MHz – 700MHz • • Selectable ÷1 or ÷2 operation Supports the following applications: SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV RMS phase jitter @ 622.08MHz (12kHz - 20MHz): 0.80ps (typical) Offset Noise Power 100Hz ................ -60.3 dBc/Hz 1kHz .................. -88.5 dBc/Hz 10kHz ................ -111.9 dBc/Hz 100kHz .............. -113.0 dBc/Hz • • • Full 3.3V supply mode 0°C to 70°C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment Block Diagram VCCO_CMOS N0 N1 N2 3 N2:N0 SEL0 Pulldown SEL1 Pulldown N XTAL_IN0 OSC 00 11 XTAL_OUT0 XTAL_IN1 OSC 01 Phase Detector VCO 10 01 00 XTAL_OUT1 TEST_CLK Pulldown 10 000 001 010 011 100 101 M ÷18 ÷22 ÷24 ÷25 ÷32 (default) ÷40 000 001 010 011 ÷1 ÷2 ÷3 ÷4 (default) 100 101 110 111 ÷5 ÷6 ÷8 ÷10 VCCO_PECL Q0 Q0 VEE VCCA VCC XTAL_OUT1 XTAL_IN1 Q0 Q0 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 REF_CLK VEE OE_REF M2 M1 M0 MR SEL1 SEL0 TEST_CLK XTAL_IN0 XTAL_OUT0 843001-21 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View MR Pulldown M2:M0 3 REF_CLK OE_REF Pulldown 843001-21 Rev A 4/6/15 1 ©2015 Integrated Device Technology, Inc. 843001-21 DATA SHEET Table 1. Pin Descriptions Number Name 1 VCCO_CMOS Power Type 2, 3 N0, N1 Input Pullup 4 N2 Input Pulldown Description Output supply pin for REF_CLK output. Output divider select pins. Default ÷4. LVCMOS/LVTTL interface levels. See Table 3C. 5 VCCO_PECL Power Output supply pin for LVPECL output. 6, 7 Q0, Q0 Output Differential output pair. LVPECL interface levels. 8, 23 VEE Power Negative supply pins. 9 VCCA Power Analog supply pin. 10 VCC Power Core supply pin. 11, 12 XTAL_OUT1, XTAL_IN1 Input Parallel resonant crystal interface. XTAL_OUT1 is the output, XTAL_IN1 is the input. 13, 14 XTAL_OUT0, XTAL_IN0 Input Parallel resonant crystal interface. XTAL_OUT0 is the output, XTAL_IN0 is the input. 15 TEST_CLK Input Pulldown LVCMOS/LVTTL clock input. 16, 17 SEL0, SEL1 Input Pulldownp Input MUX select pins. LVCMOS/LVTTL interface levels. See Table 3D. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q0 to go low and the inverted output Q0 to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 18 MR Input Pulldown 19, 20 M0, M1 Input Pulldown 21 M2 Input Pullup Pulldown 22 OE_REF Input 24 REF_CLK Output Feedback divider select pins. Default ÷32. See Table 3B LVCMOS/LVTTL interface levels. Reference clock output enable. Default Low. LVCMOS/LVTTL interface levels. Reference clock output. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to intenal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k ROUT Output Impedance 7  Rev A 4/6/15 Test Conditions 2 Minimum Typical Maximum Units FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 843001-21 DATA SHEET Function Tables Table 3A. Common Configuration Table Input Reference Clock (MHz) M Divider Value N Divider Value VCO (MHz) Output Frequency (MHz) Application 27 22 8 594 74.25 HDTV 24.75 24 8 594 74.25 HDTV 14.8351649 40 8 593.4066 74.1758245 HDTV 19.44 32 4 622.08 155.52 SONET 19.44 32 8 622.08 77.76 SONET 19.44 32 1 622.08 622.08 SONET 19.44 32 2 622.08 311.04 SONET 19.53125 32 4 625 156.25 10 GigE 25 25 5 625 125 1 GigE 25 25 10 625 62.5 1 GigE 25 24 6 600 100 PCI Express 25 24 4 600 150 SATA 25 24 8 600 75 SATA 26.5625 24 6 637.5 106.25 Fibre Channel 1 26.5625 24 3 637.5 212.5 4 Gig Fibre Channel 26.5625 24 4 637.5 159.375 10 Gig Fibre Channel 31.25 18 5 562.5 187.5 12 GigE Table 3B. Programmable M Output Divider Function Table Inputs Input Frequency (MHz) M2 M1 M0 M Divider Value 0 0 0 18 31.1 38.9 0 0 1 22 25.5 31.8 0 1 0 24 23.3 29.2 0 1 1 25 22.4 28.0 1 0 0 32 17.5 21.9 1 0 1 40 14.0 17.5 Minimum Maximum Table 3C. Programmable N Output Divider Function Table Inputs N2 N1 N0 M Divider Value 0 0 0 1 0 0 1 2 0 1 0 3 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Inputs 3 N2 N1 N0 M Divider Value 0 1 1 4 1 0 0 5 Rev A 4/6/15 843001-21 DATA SHEET Inputs N2 N1 N0 M Divider Value 1 0 1 6 1 1 0 8 1 1 1 10 Table 3D. Bypass Mode Function Table Inputs SEL1 SEL0 Reference PLL Mode 0 0 XTAL0 1 0 1 XTAL1 2 1 0 TEST_CLK 8 1 1 TEST_CLK1 10 Rev A 4/6/15 4 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 843001-21 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characterisitcs is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Outputs, VO (LVCMOS) -0.5V to VCCO_CMOS + 0.5V Package Thermal Impedance, JA 70C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = VCCA = VCCO_CMOS = VCCO_PECL = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VCC VCCA Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V Analog Supply Voltage 3.135 3.3 3.465 V VCCO_PECL, Output Supply Voltage VCCO_CMOS 3.135 3.3 3.465 V IEE Power Supply Current 170 mA ICCA Analog Supply Current 11 mA ICCO_PECL, ICCO_CMOS Output Supply Current 8 mA FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 5 Rev A 4/6/15 843001-21 DATA SHEET Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCA = VCCO_CMOS = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions Minimum Typical Maximum Units 2 VCC + 0.3 V SEL0, SEL1, OE_REF, N0:N2, MR, M0:M2 -0.3 0.8 V TEST_CLK -0.3 1.3 V TEST_CLK, M0, M1, N2, MR, OE_REF, SEL0, SEL1 VCC = VIN = 3.465V 150 µA M2, N0, N1 VCC = VIN = 3.465V 5 µA TEST_CLK, M0, M1, N2, MR, OE_REF, SEL0, SEL1 VCC = 3.465V, VIN = 0V -5 µA M2, N0, N1 VCC = 3.465V, VIN = 0V -150 µA 2.6 V VOH Output High Voltage: NOTE 1 REF_CLK VOL Output Low Voltage: NOTE 1 REF_CLK 0.5 V NOTE 1: Output terminated with 50 to VCCO _CMOS/2. See Parameter Measurement Information Section, ""3.3V LVCMOS Output Load Test Circuit Diagram"". Table 4C. LVPECL DC Characteristics, VCC = VCCA = VCCO_PECL = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VOH Output High Current; NOTE 1 VOL Output Low Current; NOTE 1 VSWING Peak-toPeak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCCO – 1.4 VCCO – 0.9 µA VCCO – 2.0 VCCO – 1.7 µA 0.6 1.0 V Maximum Units 40 MHz Equivalent Series Resistance (ESR) 50  Shunt Capacitance 7 pF NOTE 1: Outputs termination with 50 to VCCO_PECL – 2V. Table 5. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental Frequency 12 NOTE: Characterized using an 18pF parallel resonant crystal. Rev A 4/6/15 6 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 843001-21 DATA SHEET AC Electrical Characteristics Table 6. AC Characteristics, VCC = VCCA = VCCO_CMOS = VCCO_PECL = 3.3V ± 5%, TA = 0°C to 70°C Parameter Symbol fOUT Output Frequency tPD Propagation Delay; TEST_CLK to NOTE 1 REF_CLK tjit(Ø) RMS Phase Jitter, (Random); NOTE 2, 3 tVCO PLL VCO Lock Range tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Maximum Units 56 700 MHz 2.3 2.8 ns 622.08MHz, (12kHz – 20MHz) Typical 0.80 ps 560 700 MHz Q0, Q0 20% to 80% 200 500 ps REF_CLK 20% to 80% 300 800 ps Q0, Q0 45 55 % REF_CLK 44 56 % NOTE 1: Measured from the VCC/2 of the input to VCCO_CMOS/2 of the output. NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. Typical Phase Noise at 622.08MHz ➝ 0 -10 OC-12 Filter -20 -30 622.08MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.80ps (typical) -40 -50 -70 -80 -90 ➝ Raw Phase Noise Data -100 -110 ➝ Noise Power dBc Hz -60 -120 -130 Phase Noise Result by adding a Sonet OC-12 filter to raw data -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M Offset Frequency (Hz) FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 7 Rev A 4/6/15 843001-21 DATA SHEET Parameter Measurement Information 2V% 1.65V±5% VCC, VCCA, VCCO_PECL Qx SCOPE SCOPE VCC, VCCA, VCCO_CMOS nQx Qx GND VEE -1.65V±5% - -1.3V ± 0.165V 3.3V LVPECL Output Load AC Test Circuit 3.3V LVCMOS Output Load AC Test Circuit Noise Power Phase Noise Plot VCC 2 TEST_CLK Phase Noise Mask VCCO_LVCMOS REF_CLK 2 t f1 Offset Frequency PD f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS Phase Jitter Propagation Delay V Q0 CCO_CMOS Q0 2 REF_CLK t PW t odc = PERIOD t PW x 100% t PERIOD LVPECL Output Duty Cycle/Pulse Width/Period Rev A 4/6/15 LVCMOS Output Duty Cycle/Pulse Width/Period 8 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 843001-21 DATA SHEET Parameter Measurement Information, continued 80% 80% 80% 80% VSW I N G Clock Outputs 20% 20% tR Clock Outputs tF LVPECL Output Rise/Fall Time 20% 20% tR tF LVCMOS Output Rise/Fall Time Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 843001-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin. 3.3V VCC 0.01µF VCCA 0.01µF 10µF Figure 1. Power Supply Filtering FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 9 Rev A 4/6/15 843001-21 DATA SHEET Crystal Input Interface The 843001-21 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 19.44MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 22pF X1 18pF Parallel Crystal XTAL_OUT C2 22pF Figure 2. Crystal Input Interface LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VCC impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. VCC R1 Ro Rs 0.1µf 50Ω XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Figure 3. General Disgram for LVCMOS Driver to XTAL Input Interface Rev A 4/6/15 10 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 843001-21 DATA SHEET Recommendations for Unused Input and Output Pins Inputs: Outputs: Crystal Inputs: LVPECL Output: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Output: TEST_CLK Input: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the TEST_CLK to ground. LVCMOS Control Pins: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and FOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 3.3V Zo = 50Ω 125Ω FIN FOUT 125Ω Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω Figure 4A. 3.3V LVPECL Output Termination FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 84Ω Figure 4B. 3.3V LVPECL Output Termination 11 Rev A 4/6/15 843001-21 DATA SHEET Power Considerations This section provides information on power dissipation and junction temperature for the ICS843001.21. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 843001-21 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 170mA = 589.05mW • Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.3V, with all outputs switching) = 589.05mW + 30mW = 619.05mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 7below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.619W * 65°C/W = 110.2°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 7. Thermal Resitance JA for 24 Lead TSSOP, Forced Convection JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Rev A 4/6/15 0 1 2.5 70°C/W 65 62 12 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 843001-21 DATA SHEET 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. VCCO Q1 VOUT RL 50Ω VCCO - 2V Figure 5. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCCO - 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCOO_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - 0.9V)/50] * 0.9V = 19.8mW L L Pd_L = [(VOL_MAX (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - 1.7V)/50] * 1.7V = 10.2mW – L L Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 13 Rev A 4/6/15 843001-21 DATA SHEET Reliability Information Table 8. JA vs. Air Flow Table for a 24 Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 70°C/W 65 62 Transistor Count The transistor count for 843001-21 is: 4057 Package Outline and Package Dimension Package Outline - G Suffix for 24 Lead TSSOP Table 9. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 24 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75  0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 Rev A 4/6/15 14 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 843001-21 DATA SHEET Ordering Information Table 10. Ordering Information Part/Order Number 843001AG-21LF 843001AG-21LFT Marking ICS843001A21L ICS843001A21L Package “Lead-Free” 24 Lead TSSOP “Lead-Free” 24 Lead TSSOP Shipping Packaging Tube Tape & Reel Temperature 0C to 70C 0C to 70C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 15 Rev A 4/6/15 843001-21 DATA SHEET Revision History Sheet Rev A Table Page T10 1 14 Features Section - added Lead-Free bullet. Ordering Information table - added Lead-Free marking. T3C 3 10/26/05 T10 9 10 Programmable N Output Divider Function Table - corrected heading from M Divide Value to N Divide value. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free note. General Description - corrected crystal frequency from 25.5625MHz crystal to 26.5625MHz crystal. Added LVCMOS Output RiseFall Time Diagram. Added LVCMOS to XTAL Interface section. Updated format throughout the datasheet. 3/15/07 Ordering Information - removed leaded devices. Updated data sheet information. 4/6/15 A 1 A A 9 10 T10 15 Description of Change FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Date 16 2/8/05 Rev A 4/6/15 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. 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