FemtoClocks™ LVCMOS/Crystal-to-3.3V
LVPECL Frequency Synthesizer
843004
DATA SHEET
General Description
Features
The 843004 is a 4 output LVPECL synthesizer optimized to
generate Fibre Channel reference clock frequencies and is a
member of the HiPerClocksTM family of high performance clock
solutions from IDT. Using a 26.5625MHz 18pF parallel resonant
crystal, the following frequencies can be generated based on the 2
frequency select pins (F_SEL[1:0]): 212.5MHz, 187.5MHz,
159.375MHz, 156.25, 106.25MHz, and 53.125MHz. The 843004
uses IDT’s 3rd generation low phase noise VCO technology and
can achieve 1ps or lower typical rms phase jitter, easily meeting
Fibre Channel jitter requirements. The 843004 is packaged in a
small 24-pin TSSOP package.
•
•
Four 3.3Vdifferential LVPECL output pairs
•
Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, 53.125MHz
•
•
VCO range: 560MHz – 680MHz
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended clock input
RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637kHz – 10MHz): 0.72ps (typical)
Offset
Noise Power
100Hz ................ -95.0 dBc/Hz
1kHz .................. -114.3 dBc/Hz
10kHz ................ -123.8 dBc/Hz
100kHz .............. -124.6 dBc/Hz
•
•
•
Full 3.3V supply mode
-30°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Table 3A. Bank A Frequency Table
Inputs
Input Frequency (MHz)
F_SEL1
F_SEL0
M Div. Value
N Div. Value
M/N Div. Value
Output Frequency (MHz)
26.5625
0
0
24
3
8
212.5
26.5625
0
1
24
4
6
159.375
26.5625
1
0
24
6
4
106.25
26.5625
1
1
24
12
2
53.125
26.04166
0
1
24
4
6
156.25
23.4375
0
0
24
3
8
187.5
Block Diagram
Pin Assignment
2
F_SEL[1:0] Pulldown
nPLL_SEL Pulldown
TEST_CLK Pulldown
Q0
1
F_SEL[1:0]
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
1
26.5625MHz
XTAL_IN
OSC
XTAL_OUT
0
Phase
Detector
VCO
637.5MHz
(w/26.5625MHz
Reference)
nQ0
Q1
nQ1
0
Q2
nXTAL_SEL Pulldown
M = 24 (fixed)
843004 Rev C 5/26/15
1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
VCCO
Q3
nQ3
VEE
nc
nXTAL_SEL
TEST_CLK
VEE
XTAL_IN
XTAL_OUT
nQ2
ICS843004
Q3
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm
package body
G Package
Top View
nQ3
MR Pulldown
nQ1
Q1
VCCO
Q0
nQ0
MR
nPLL_SEL
nc
VCCA
F_SEL0
VCC
F_SEL1
©2015 Integrated Device Technology, Inc.
843004 DATA SHEET
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
nQ1, Q1
Output
Differential output pair. LVPECL interface levels.
3, 22
VCCO
Power
Output supply pins.
4, 5
Q0, nQ0
Output
Differential output pair. LVPECL interface levels.
6
MR
Input
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
7
nPLL_SEL
Input
Pulldown
Selects between the PLL and TEST_CLK as input to the dividers. When
LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
8, 18
nc
Unused
9
VCCA
Power
10, 12
F_SEL0.
F_SEL1
Input
11
VCC
Power
Core supply pin.
13,
14
XTAL_OUT,
XTAL_IN
Input
Parallel resonant crystal interface.
XTAL_OUT is the output, XTAL_IN is the input.
15, 19
VEE
Power
Negative supply pins.
16
TEST_CLK
Input
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
17
nXTAL_SEL
Input
Pulldown
Selects between the single-ended TEST_CLK or crystal interface as the PLL
reference source. When HIGH, selects TEST_CLK. When LOW, selects
XTAL. LVCMOS/LVTTL interface levels.
20, 21
nQ3, Q3
Output
Differential output pair. LVPECL interface levels.
23, 24
Q2, nQ2
Output
Differential output pair. LVPECL interface levels.
No connect.
Analog supply pin.
Pulldown
Frequency select pins. LVCMOS/LVTTL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
k
Rev C 5/26/15
Test Conditions
2
Minimum
Typical
Maximum
Units
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
843004 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, JA
70C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE =0V, TA = -30°C to 85°C
Symbol
Parameter
VCC
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
3.135
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
135
mA
ICCA
Analog Supply Current
15
mA
Included in IEE
Table 3B. LVCMOS/LVTTL DC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE =0V, TA = -30°C to 85°C
Symbol
Parameter
Test Conditions
VIH
Input High Voltage
VIL
Input
Low Voltage
Maximum
Units
2
VCC + 0.3
V
nPLL_SEL, nXTAL_SEL,
MR, F_SEL[0:1]
-0.3
0.8
V
TEST_CLK
-0.3
1.3
V
150
µA
IIH
Input
High Current
TEST_CLK,
MR, F_SEL[0:1],
nPLL_SEL, nXTAL_SEL
VCC = VIN = 3.465V
IIL
Input
Low Current
TEST_CLK,
MR, F_SEL[0:1],
nPLL_SEL, nXTAL_SEL
VCC = 3.465V, VIN = 0V
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
3
Minimum
-5
Typical
µA
Rev C 5/26/15
843004 DATA SHEET
Table 3C. LVPECL DC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE =0V, TA = -30°C to 85°C
Symbol
Parameter
VOH
Output High Current; NOTE 1
VOL
Output Low Current; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
Typical
Maximum
Units
VCCO – 1.4
VCCO – 0.9
µA
VCCO – 2.0
VCCO – 1.7
µA
0.6
1.0
V
NOTE 1: Outputs termination with 50 to VCCO – 2V.
Table 4. Crystal Characteristics
Parameter
Test Conditions
Minimum
Maximum
Units
28.33
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
Maximum
Units
226.66
MHz
Mode of Oscillation
Typical
Fundamental
Frequency
23.33
26.5625
NOTE: Characterized using an 18pF parallel resonant crystal.
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE =0V, TA = -30°C to 85°C
Parameter
fOUT
tsk(o)
tjit(Ø)
tR / tF
odc
Symbol
Test Conditions
Minimum
F_SEL[1:0] = 00
186.67
Output Frequency Range
Typical
F_SEL[1:0] = 01
140
170
MHz
F_SEL[1:0] = 10
93.33
113.33
MHz
F_SEL[1:0] = 11
46.67
56.66
MHz
30
ps
Output Skew; NOTE 1, 2
RMS Phase Jitter, (Random);
NOTE 3
212.5MHz,
(637kHz – 10MHz)
0.70
ps
159.375MHz,
(637kHz – 10MHz)
0.75
ps
156.25MHz,
(637kHz – 10MHz)
0.58
ps
106.25MHz, (637kHz – 10MHz)
0.81
ps
53.125MHz, (637kHz – 10MHz)
0.98
ps
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
300
600
ps
F_SEL[1:0] 00
49
51
%
F_SEL[1:0] = 00
45
55
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VCCO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plots.
Typical Phase Noise at 53.125MHz
Rev C 5/26/15
4
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY
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843004 DATA SHEET
0
-10
-20
53.125MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.98ps (typical)
Fibre Channel Filter
-30
-40
-50
-60
-80
-90
-100
-110
-120
Noise Power
dBc
Hz
-70
-130
Raw Phase Noise Data
-140
-150
-160
-170
-180
Phase Noise Result by adding a
Fibre Channel filter to raw data
-190
10
100
1k
10k
100k
1M
10M
100M
Offset Frequency (Hz)
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
5
Rev C 5/26/15
843004 DATA SHEET
Typical Phase Noise at 106.25MHz
0
106.25MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.81ps (typical)
-10
-20
Fibre Channel Filter
-30
-40
-50
-60
-80
-90
-100
-110
Noise Power
dBc
Hz
-70
-120
-130
Raw Phase Noise Data
-140
-150
-160
-170
Phase Noise Result by adding a
Fibre Channel filter to raw data
-180
-190
10
100
1k
10k
100k
1M
10M
100M
Offset Frequency (Hz)
Rev C 5/26/15
6
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY
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843004 DATA SHEET
Typical Phase Noise at 156.25MHz
0
-10
-20
156.25MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.58ps (typical)
Fibre Channel Filter
-30
-40
-50
-60
-80
-90
-100
-110
Noise Power
dBc
Hz
-70
-120
Raw Phase Noise Data
-130
-140
-150
-160
-170
Phase Noise Result by adding a
Fibre Channel filter to raw data
-180
-190
10
100
1k
10k
100k
1M
10M
100M
Offset Frequency (Hz)
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
7
Rev C 5/26/15
843004 DATA SHEET
Typical Phase Noise at 159.375MHz
0
-10
-20
159.375MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.75ps (typical)
Fibre Channel Filter
-30
-40
-50
-60
-80
-90
-100
-110
Noise Power
dBc
Hz
-70
-120
Raw Phase Noise Data
-130
-140
-150
-160
-170
Phase Noise Result by adding a
Fibre Channel filter to raw data
-180
-190
10
100
1k
10k
100k
1M
10M
100M
Offset Frequency (Hz)
Rev C 5/26/15
8
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
843004 DATA SHEET
Typical Phase Noise at 212.5MHz
0
-10
-20
212.5MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.70ps (typical)
Fibre Channel Filter
-30
-40
-50
-60
-80
-90
-100
-110
Noise Power
dBc
Hz
-70
-120
Raw Phase Noise Data
-130
-140
-150
-160
-170
Phase Noise Result by adding a
Fibre Channel filter to raw data
-180
-190
10
100
1k
10k
100k
1M
10M
100M
Offset Frequency (Hz)
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
9
Rev C 5/26/15
843004 DATA SHEET
Parameter Measurement Information
2V%
VCC,
VCCA,
VCCO
Qx
Noise Power
Phase Noise Plot
SCOPE
Phase Noise Mask
nQx
f1
VEE
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-
-1.3V ± 0.165
3.3V LVPECL Output Load AC Test Circuit
RMS Phase Jitter
nQx
Qx
80%
80%
VSW I N G
nQy
Clock
Outputs
Qy
Output Skew
20%
20%
tR
tF
Output Rise/Fall Time
nQ0:nQ3
Q0:Q3
Output Duty Cycle/Pulse Width/Period
Rev C 5/26/15
10
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
843004 DATA SHEET
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 843004 provides
separate power supplies to isolate any high switching noise from
the outputs to the internal PLL. VCC, VCCA and VCCO should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic VCC pin and also shows that VCCA
requires that an additional 10 resistor along with a 10F bypass
capacitor be connected to the VCCA pin.
3.3V
VCC
0.01µF
VCCA
0.01µF
10µF
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
Crystal Inputs
LVPECL Outputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied
from XTAL_IN to ground.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
TEST_CLK Input
For applications not requiring the use of the clock, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the TEST_CLK to ground.
LVCMOS Control Pins
All control pins have internal pull-downs; additional resistance is
not required but can be added for additional protection. A 1k
resistor can be used.
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
11
Rev C 5/26/15
843004 DATA SHEET
Crystal Input Interface
The 843004 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
determined using a 26.5625MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
XTAL_IN
C1
33pF
X1
18pF Parallel Crystal
XTAL_OUT
C2
27pF
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
VCC
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50 applications, R1
and R2 can be 100. This can also be accomplished by removing
R1 and making R2 50.
VCC
R1
Ro
Rs
0.1µf
50Ω
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
Rev C 5/26/15
12
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
843004 DATA SHEET
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
Figure 4A. 3.3V LVPECL Output Termination
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
R2
84
Figure 4B. 3.3V LVPECL Output Termination
13
Rev C 5/26/15
843004 DATA SHEET
Layout Guideline
Figure 4 shows a schematic example of the 843004. An example of
LVEPCL termination is shown in this schematic. Additional LVPECL
termination approaches are shown in the LVPECL Termination
Application Note. In this example, an 18 pF parallel resonant
26.5625MHz crystal is used. The C1= 27pF and
C2 = 33pF are recommended for frequency accuracy. For a different
board layout, the C1 and C2 may be slightly adjusted for optimizing
frequency accuracy.
Figure 4. 843004 Schematic Example
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY
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14
Rev C 5/26/15
843004 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 843004.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 843004 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 467.8mW
•
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 467.8mW + 120mW = 587.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate
air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 6below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.588W * 65°C/W = 123.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
0
1
2.5
70°C/W
65°C/W
62°C/W
15
Rev C 5/26/15
843004 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 5. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage
of VCCO – 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCOO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
Rev C 5/26/15
16
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
843004 DATA SHEET
Reliability Information
Table 7. JA vs. Air Flow Table for a 24 Lead TSSOP
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
70°C/W
65°C/W
62°C/W
Transistor Count
The transistor count for 843004 is: 2578
Package Outline and Package Dimension
Package Outline - G Suffix for 24 Lead TSSOP
Table 9. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
24
A
1.20
A1
0.5
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.90
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
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843004 DATA SHEET
Ordering Information
Table 9. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
843004AGLF
ICS843004AGL
“Lead-Free” 24 Lead TSSOP
Tube
-30C to 85C
843004AGLFT
ICS843004AGL
“Lead-Free” 24 Lead TSSOP
2500 Tape & Reel
-30C to 85C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Rev C 5/26/15
18
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
843004 DATA SHEET
Revision History Sheet
Rev
Table
Page
Description of Change
Date
A
1
Added 187.5MHz to the Frequency Selection Function Table.
8/26/04
A
10
Added Schematic Layout.
11/18/04
T9
1
15
Features Section - added Lead-Free bullet.
Ordering Information Table - added Lead-Free part number.
3/21/05
T5
4
AC Characteristics Table - deleted Propagation Delay row.
5/5/05
T3B
3
11
12
14
LVCMOS/LVTTL DC Characteristics Table - corrected IIL spec. from -150µA min. to
-5µA min.
Added Recommendations for Unused Input and Output Pins section.
Added LVCMOS to XTAL Interface section.
Corrected Figure 4, Schematic Example, Pin 18 from VCC to nc.
3/4/08
T5
1
4
20
Frequency Select Function Table - corrected F_SEL0 column, last 2 rows.
AC Characteristics Table - Added Thermal Note.
Contact Information - Updated
1/19/09
T9
18
Updated data sheet format.
Ordering Information - Removed leaded devices.
5/26/15
A
B
C
C
C
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
19
Rev C 5/26/15
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email: clocks@idt.com
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