843021AGI-01T

FemtoClock® Crystal-to-3.3V, 2.5V LVPECL Clock Generator 843021I-01 DATA SHEET General Description Features The 843021I-01 is a Gigabit Ethernet Clock Generator. The 843021I-01 uses a 25MHz crystal to synthesize 125MHz. The 843021I-01 has excellent phase jitter performance, over the 1.875MHz – 20MHz integration range. The 843021I-01 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • • One differential 3.3V or 2.5V LVPECL output • • • Output frequency range: 125MHz, using a 25MHz crystal • • • Full 3.3V or 2.5V operating supply Block Diagram Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal VCO range: 490MHz – 640MHz RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.41ps (typical) -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment OE Pullup 25MHz XTAL_IN OSC XTAL_OUT Phase Detector VCO ÷4 (fixed) Q nQ 1 2 3 4 8 7 6 5 Q nQ VCC OE 843021I-01 8 Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View ÷20 (fixed) 843021I-01 Rev A 9/25/15 VCC XTAL_OUT XTAL_IN VEE # ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Table 1. Pin Descriptions Number Name Type Description 1, 6 VCC Power Power supply pins. 2, 3 XTAL_OUT XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 4 VEE Power Negative supply pin. 5 OE Input 7, 8 nQ, Q Output Pullup Active high output enable. When logic HIGH, the outputs are enabled and active. When logic LOW, the outputs are disabled and are in a high impedance state. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC+ 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, JA 129.5C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VCC Positive Supply Voltage IEE Power Supply Current Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 64 mA Table 3B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VCC Positive Supply Voltage IEE Power Supply Current 843021I-01 Rev A 9/25/15 Test Conditions 2 Minimum Typical Maximum Units 2.375 2.5 2.625 V 62 mA ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Table 3C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum VIH Input High Voltage VCC = 3.3V VIL Input Low Voltage IIH Input High Current VCC = VIN = 3.465 or 2.625V IIL Input Low Current VCC = 3.465V or 2.625V, VIN = 0V Typical Maximum Units 2 VCC + 0.3 V VCC = 2.5V 1.7 VCC + 0.3 V VCC = 3.3V -0.3 0.8 V VCC = 2.5V -0.3 0.7 V 5 µA -150 µA Table 3D. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCC – 1.4 VCC – 0.9 V VCC – 2.0 VCC – 1.7 V 0.6 1.0 V Maximum Units NOTE 1: Outputs termination with 50 to VCC – 2V. Table 3E. LVPECL DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical VOH Output High Voltage; NOTE 1 VCC – 1.4 VCC – 0.9 V VOL Output Low Voltage; NOTE 1 VCC – 2.0 VCC – 1.5 V VSWING Peak-to-Peak Output Voltage Swing 0.4 1.0 V Maximum Units NOTE 1: Outputs termination with 50 to VCC – 2V. Table 4. Crystal Characteristics Parameter Test Conditions Minimum Typical Mode of Oscillation Fundamental Frequency; NOTE 1 25 MHz Equivalent Series Resistance (ESR) 90  Shunt Capacitance 7 pF 300 µW Drive Level 843021I-01 Rev A 9/25/15 3 ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR AC Electrical Characteristics Table 5A. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter, Random; NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical Maximum Units 122.5 125 160 MHz 125MHz, ( Integration Range: 1.875MHz – 20MHz) 20% to 80% 0.41 ps 250 600 ps 49 51 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions NOTE 1: Please refer to Phase Noise Plot. Table 5B. AC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter, Random; NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical Maximum Units 122.5 125 160 MHz 125MHz, ( Integration Range: 1.875MHz – 20MHz) 20% to 80% 0.42 ps 250 600 ps 49 51 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions NOTE 1: Please refer to Phase Noise Plot. 843021I-01 Rev A 9/25/15 4 ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR ➝ Typical Phase Noise at 125MHz (3.3V or 2.5V) Gigabit Ethernet Filter Raw Phase Noise Data ➝ ➝ Noise Power dBc Hz 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz (3.3V)= 0.41ps (typical) 1.875MHz to 20MHz (2.5V)= 0.42ps (typical) Phase Noise Result by adding a Gigabit Ethernet filter to raw data Offset Frequency (Hz) 843021I-01 Rev A 9/25/15 5 ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Parameter Measurement Information 2V 2V VCC SCOPE Qx VCC Qx SCOPE nQx nQx VEE VEE -0.5V ± 0.125V -1.3V ± 0.165V 3.3V LVPECL Output Load AC Test Circuit 2.5V LVPECL Output Load AC Test Circuit Phase Noise Plot Noise Power nQ Phase Noise Mask Q f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot Output Rise/Fall Time RMS Phase Jitter nQ Q Output Duty Cycle/Pulse Width/Period 843021I-01 Rev A 9/25/15 6 ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Applications Information Crystal Input Interface The 843021I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 27pF X1 18pF Parallel Crystal XTAL_OUT C2 27pF Figure 1. Crystal Input Interface Overdriving the XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 2A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. 3.3V 3.3V R1 100 Ro ~ 7 Ohm C1 Zo = 50 Ohm XTAL_IN RS 43 R2 100 Driv er_LVCMOS 0.1uF XTAL_OUT Cry stal Input Interf ace Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface VCC=3.3V C1 Zo = 50 Ohm XTAL_IN R1 50 Zo = 50 Ohm 0.1uF XTAL_OUT LVPECL Cry stal Input Interf ace R2 50 R3 50 Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface 843021I-01 Rev A 9/25/15 7 ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 R3 125 3.3V R4 125 3.3V 3.3V Zo = 50 + _ Input Zo = 50 R1 84 Figure 3A. 3.3V LVPECL Output Termination 843021I-01 Rev A 9/25/15 R2 84 Figure 3B. 3.3V LVPECL Output Termination 8 ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Termination for 2.5V LVPECL Outputs ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. Figure 4A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC – 2V. For VCC= 2.5V, the VCC– 2V is very close to 2.5V VCC = 2.5V 2.5V 2.5V VCC = 2.5V R1 250Ω R3 250Ω 50Ω + 50Ω + 50Ω – 50Ω 2.5V LVPECL Driver – R1 50Ω 2.5V LVPECL Driver R2 62.5Ω R2 50Ω R4 62.5Ω R3 18Ω Figure 4A. 2.5V LVPECL Driver Termination Example Figure 4B. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50Ω R2 50Ω Figure 4C. 2.5V LVPECL Driver Termination Example 843021I-01 Rev A 9/25/15 9 ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Schematic Example Figure 5 shows an example of 843021I-01 application schematic. In this example, the device is operated at VCC = 3.3V. The decoupling capacitor should be located as close as possible to the power pin. The input is driven by a 25MHz quartz crystal. For the LVPECL output drivers, only two termination examples are shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note. VCC = 3.3V 3.3V C2 27pF R3 133 U1 R5 133 Zo = 50 Ohm 1 2 3 4 X1 25MHz S) VCC XTAL_OUT XTAL_IN VEE Q nQ VCC OE 8 7 6 5 + OE Zo = 50 Ohm - 843021I-01 C1 27pF R4 82.5 R6 82.5 VCC C3 10uF C4 .1uF C5 .1uF Zo = 50 + Zo = 50 - R2 50 R1 50 R3 50 Optional Termination Figure 5. 843021I-01 Schematic Example Figure 5. 843021I-01 Schematic Example 843021I-01 Rev A 9/25/15 10 ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Power Considerations This section provides information on power dissipation and junction temperature for the 843021I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 843021I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 64mA = 221.76mW • Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 221.76mW + 30mW = 251.76mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 129.5°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.252W * 90.5°C/W = 117.6°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 843021I-01 Rev A 9/25/15 0 1 2.5 129.5°C/W 125.5°C/W 123.5°C/W 11 ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 6. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCC – 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (VCC_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V - (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = [(2V – 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 843021I-01 Rev A 9/25/15 12 ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Reliability Information Table 7. JA vs. Air Flow Table for a 8 Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 129.5°C/W 125.5°C/W 123.5°C/W Transistor Count The transistor count for 843021I-01 is: 1765 Package Outline and Package Dimensions Package Outline - G Suffix for 8 Lead TSSOP Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75  0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 843021I-01 Rev A 9/25/15 13 ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Ordering Information Table 9. Ordering Information Part/Order Number 843021AGI-01LF 843021AGI-01LFT Marking AI01L AI01L Package “Lead-Free” 8 Lead TSSOP “Lead-Free” 8 Lead TSSOP Shipping Packaging Tube Tape & Reel Temperature -40C to 85C -40C to 85C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. 843021I-01 Rev A 9/25/15 14 ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Revision History Sheet Rev Table Page A T9 14 Ordering Information Table - corrected “Temperature” column. 5/14/08 A T1 2 Pin Description Table - corrected typo in VCC row, pins 1, 6 instead of 1, 8. 11/10/08 T3D - T3E 3 LVPECL DC Characteristics Tables - corrected VOH/VOL parameters from “Current” to “Voltage” and units from “uA” to “V”. Updated “Overdriving the Crystal Interface” section. Updated header/footer. 10/15/10 Ordering Information - removed leaded devices. 9/25/15 A A 7 T9 843021I-01 Rev A 9/25/15 14 Description of Change Date 15 ©2015 Integrated Device Technology, Inc. Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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