8430I-61
500MHz, Crystal-to-3.3V, 2.5V Differential
LVPECL Frequeny Synthesizer
DATA SHEET
GENERAL DESCRIPTION
FEATURES
T h e 8 4 3 0 I - 6 1 i s a g e n e ra l p u r p o s e, d u a l o u t p u t
Crystal-to-3.3V, 2.5V Differential LVPECL High Frequency
Synthesizer . The 8430I-61 has a selectable TEST_CLK
or crystal inputs. The VCO operates at a frequency range
of 250MHz to 500MHz. The VCO frequency is programmed
in steps equal to the value of the input reference or
crystal frequency. The VCO and output frequency can be
programmed using the serial or parallel interfaces to the
configuration logic. Frequency steps as small as 1MHz can be
achieved using a 16MHz crystal or TEST_CLK.
• Dual differential 3.3V or 2.5V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
• Output frequency range: 20.83MHz to 500MHz
• Crystal input frequency range: 14MHz to 27MHz
• VCO range: 250MHz to 500MHz
• Parallel or serial interface for programming counter
and output dividers
• RMS period jitter: 6ps (maximum)
• Cycle-to-cycle jitter: 30ps (maximum)
• Supply voltage modes:
VCC/VCCA/VCCO
3.3/3.3/3.3
3.3/3.3/2.5
• -40°C to 85°C ambient operating temperature
• Available in lead-free RoHS compliant package
BLOCK DIAGRAM
PIN ASSIGNMENT
XTAL_IN
nP_LOAD
VCO_SEL
M0
M1
M2
M3
M4
32 31 30 29 28 27 26 25
M5
1
24
XTAL_OUT
M6
2
23
TEST_CLK
M7
3
22
XTAL_SEL
M8
4
21
VCCA
N0
5
20
S_LOAD
N1
6
19
S_DATA
N2
7
18
S_CLOCK
VEE
8
17
MR
ICS8430I-61
9 10 11 12 13 14 15 16
VEE
nFOUT0
FOUT0
VCCO
nFOUT1
FOUT1
VCC
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8430I-61 REVISION D 10/15/15
1
©2015 Integrated Device Technology, Inc.
8430I-61 DATA SHEET
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input
Frequency Characteristics, Table 5, NOTE 1.
will automatically occur during power-up. The TEST output is
LOW when operating in the parallel input mode. The relationship
between the VCO frequency, the crystal frequency and the M
divider is defined as follows: fVCO = fxtal x M
16
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
16MHz reference are defined as 250 ≤ M ≤ 500. The frequency
out is defined as follows: fout = fVCO = fxtal x M
N
N
16
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N
output divide values are latched on the HIGH-to-LOW transition
of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is
passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program
the M and N bits and test bits T1 and T0. The internal registers
T0 and T1 determine the state of the TEST output as follows:
The 8430I-61 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth.
A parallel-resonant, fundamental crystal is used as the input to
the on-chip oscillator. The output of the oscillator is divided by 16
prior to the phase detector. With a 16MHz crystal, this provides
a 1MHz reference frequency. The VCO of the PLL operates over
a range of 250MHz to 500MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output
of the VCO is scaled by a divider prior to being sent to each of
the LVPECL output buffers. The divider provides a 50% output
duty cycle.
The programmable features of the 8430I-61 support two input
modes and to program the M divider and N output divider. The
two input operational modes are parallel and serial. Figure 1
shows the timing diagram for each mode. In parallel mode, the
nP_LOAD input is initially LOW. The data on inputs M0 through
M8 and N0 through N2 is passed directly to the M divider and N
output divider. On the LOW-to-HIGH transition of the nP_LOAD
input, the data is latched and the M divider remains loaded until
the next LOW transition on nP_LOAD or until a serial event
occurs. As a result, the M and N bits can be hard-wired to set
the M divider and N output divider to a specific default state that
T1
T0
TEST Output
0
0
LOW
0
1
S_Data, Shift Register Input
1
0
Output of M divider
1
1
CMOS Fout
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
2
REVISION D 10/15/15
8430I-61 DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
28, 29, 30
31, 32, 1, 2
M0, M1, M2
M3, M4, M5, M6
Type
Description
Input
3, 4
M7, M8
Input
5, 7
N0, N2
Input
6
N1
Input
8, 16
VEE
Power
Negative supply pins.
9
TEST
Output
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS interface levels.
10
VCC
Power
Core supply pin.
11, 12
FOUT1, nFOUT1
Output
Differential output for the synthesizer. LVPECL interface levels.
13
VCCO
Power
Output supply pin for LVPECL outputs.
14, 15
FOUT0, nFOUT0
Output
Differential output for the synthesizer. LVPECL interface levels.
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_
LOAD input. LVCMOS / LVTTL interface levels.
Pullup
Pulldown Determines output divider value as defined in Table 3C,
Pullup Function Table. LVCMOS / LVTTL interface levels.
17
MR
Input
Pulldown
18
S_CLOCK
Input
Pulldown
19
S_DATA
Input
Pulldown
20
S_LOAD
Input
Pulldown
21
VCCA
Power
22
XTAL_SEL
Input
23
TEST_CLK
Input
24,
25
XTAL_OUT, XTAL_
IN
Input
26
nP_LOAD
Input
27
VCO_SEL
Input
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs FOUTx to go low and the inverted outputs nFOUTx to go high. When Logic LOW, the internal dividers and
the outputs are enabled. Assertion of MR does not affect loaded M, N,
and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register on
the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels.
Analog supply pin.
Pullup
Selects between crystal oscillator or test inputs as the PLL reference
source. Selects XTAL inputs when HIGH. Selects TEST_CLK when
LOW. LVCMOS / LVTTL interface levels.
Pulldown Test clock input. LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is loaded
Pulldown into M divider, and when data present at N2:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode. LVCMOS
Pullup
/ LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
REVISION D 10/15/15
Test Conditions
3
Minimum
Typical
Maximum
Units
pF
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
8430I-61 DATA SHEET
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR
nP_LOAD
M
N
S_LOAD
S_CLOCK
S_DATA
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
L
L
Data
Data
X
X
X
Data on M and N inputs passed directly to the M divider
and N output divider. TEST output forced LOW.
L
↑
Data
Data
L
X
X
L
H
X
X
L
↑
Data
L
H
X
X
↑
L
Data
L
H
X
X
↓
L
Data
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
L
H
X
X
L
X
X
L
H
X
X
H
↑
Data
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don’t care
↑ = Rising edge transition
↓ = Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
256
128
64
32
16
8
4
2
1
M8
M7
M6
M5
M4
M3
M2
M1
M0
250
0
1
1
1
1
1
0
1
0
251
0
1
1
1
1
1
0
1
1
252
252
0
1
1
1
1
1
1
0
0
253
253
0
1
1
1
1
1
1
0
1
•
•
•
•
•
•
•
•
•
•
•
VCO Frequency
(MHz)
M Divide
250
251
•
•
•
•
•
•
•
•
•
•
•
498
498
1
1
1
1
1
0
0
1
0
499
499
1
1
1
1
1
0
0
1
1
500
500
1
1
1
1
1
0
1
0
0
NOTE 1: These M divide values and the resulting frequencies correspond to a TEST_CLK or crystal frequency of 16MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
N Divider Value
Output Frequency (MHz)
N2
N1
N0
0
0
0
1
250
500
0
0
1
1.5
166.66
333.33
0
1
0
2
125
250
0
1
1
3
83.33
166.66
1
0
0
4
62.5
125
1
0
1
6
41.66
83.33
1
1
0
8
31.25
62.5
1
1
1
12
20.83
41.66
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
4
Minimum
Maximum
REVISION D 10/15/15
8430I-61 DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
47.9°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VCC
Core Supply Voltage
Test Conditions
VCCA
Analog Supply Voltage
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
3.135
3.3
VCC
V
3.135
3.3
3.465
V
2.375
2.5
2.625
V
VCCO
Output Supply Voltage
IEE
Power Supply Current
155
mA
ICCA
Analog Supply Current
15
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VIH
Input
High Voltage
VIL
IIH
IIL
Input
Low Voltage
Input
High Current
Input
Low Current
Test Conditions
Maximum Units
M0:M8, N0:N2, MR, S_LOAD,
S_DATA, S_CLOCK, nP_
LOAD, VCO_SEL, XTAL_SEL
2
VCC + 0.3
V
TEST_CLK
2
VCC + 0.3
V
M0:M8, N0:N2, MR, S_LOAD,
S_DATA, S_CLOCK, nP_
LOAD, VCO_SEL, XTAL_SEL
-0.3
0.8
V
TEST_CLK
-0.3
1.3
V
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK, S_
DATA, S_LOAD, nP_LOAD
VCC = VIN = 3.465V
150
µA
M5, XTAL_SEL, VCO_SEL
VCC = VIN = 3.465V
5
µA
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK, S_
DATA, S_LOAD, nP_LOAD
VCC = 3.465V,
VIN = 0V
-5
µA
M5, XTAL_SEL, VCO_SEL
VCC = 3.465V,
VIN = 0V
-150
µA
VCC = 3.465V
2.6
V
Output High
TEST; NOTE 1
Voltage
Output
TEST; NOTE 1
VOL
Low Voltage
NOTE 1: Outputs terminated with 50Ω to VCC/2.
VOH
REVISION D 10/15/15
Minimum Typical
0.5
5
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
V
8430I-61 DATA SHEET
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
All AC parameters guaranteed for VCC=VCCA=VCCO=3.3V ±5%.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. See “Parameter Measurement Information” section,
“3.3V Output Load Test Circuit” figure.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fIN
Input
Frequency
Test Conditions
Minimum
Typical
Maximum
Units
TEST_CLK; NOTE 1
14
27
MHz
XTAL_IN XTAL_OUT NOTE 1
14
27
MHz
50
MHz
S_CLOCK
NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within
the 250MHz to 500MHz range. Using the minimum input frequency of 14MHz, valid values of M are 286 ≤ M ≤ 511.
Using the maximum input frequency of 27MHz, valid values of M are 149 ≤ M ≤ 296.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
Frequency
14
27
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
6
REVISION D 10/15/15
8430I-61 DATA SHEET
TABLE 7A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
FOUT
Output Frequency
Test Conditions
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1, 2
tjit(per)
Period Jitter, RMS; NOTE 1
Output Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
tH
Setup Time
Hold Time
odc
Output Duty Cycle
tLOCK
PLL Lock Time
Typical
20.83
tsk(o)
tS
Minimum
Maximum
Units
500
MHz
N ≠ 1.5
30
ps
N = 1.5
100
ps
N ≠ 1.5
6
ps
15
ps
700
ps
20% to 80%
200
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
Even N divides
48
52
%
Odd N divides
45
55
%
1
ms
Maximum
Units
500
MHz
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
TABLE 7B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
FOUT
Output Frequency
Test Conditions
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1, 2
tjit(per)
Period Jitter, RMS; NOTE 1
Output Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
tH
Setup Time
Hold Time
odc
Output Duty Cycle
tLOCK
PLL Lock Time
Typical
20.83
tsk(o)
tS
Minimum
N ≠ 1.5
35
ps
N = 1.5
140
ps
N ≠ 1.5
6
ps
30
ps
700
ps
20% to 80%
200
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
Even N divides
47
53
%
Odd N divides
45
55
%
1
ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
REVISION D 10/15/15
7
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
8430I-61 DATA SHEET
PARAMETER MEASUREMENT INFORMATION
3.3V/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
PERIOD JITTER
CYCLE-TO-CYCLE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
8
REVISION D 10/15/15
8430I-61 DATA SHEET
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 8430I-61 provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and
VCCO should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin. The 10Ω resistor
can also be replaced by a ferrite bead.
3.3V or 2.5V
VCC
.01μF
10Ω
VCCA
.01μF
10 μF
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
These same capacitor values will tune any 18pF parallel resonant crystal over the frequency range and other parameters
specified in this data sheet. The optimum C1 and C2 values can
be slightly adjusted for different board layouts.
The 8430I-61 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown
in Figure 3 below were determined using an 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Cry stal
XTAL_OUT
C2
22p
ICS84332
ICS8430-61
Figure 3. CRYSTAL INPUt INTERFACE
REVISION D 10/15/15
9
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
8430I-61 DATA SHEET
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating. Though
not required, but for additional protection, a 1kΩ resistor can be
tied from XTAL_IN to ground.
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the TEST_CLK to ground.
TEST OUTPUT:
The unused TEST output can be left floating. There should be
no trace attached.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 4. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs,
it is recommended that the amplitude be reduced from full
swing to half swing in order to prevent signal interference with
the power rail and to reduce noise. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In
addition, matched termination at the crystal input will attenuate
the signal in half. This can be done in one of two ways. First, R1
and R2 in parallel should equal the transmission line impedance.
For most 50Ω applications, R1 and R2 can be 100Ω. This can
also be accomplished by removing R1 and making R2 50Ω.
VDD
VDD
R1
Ro
.1uf
Rs
Zo = 50
Zo = Ro + Rs
XTAL_IN
R2
XTAL_OUT
FIGURE 4. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
10
REVISION D 10/15/15
8430I-61 DATA SHEET
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. There are a few simple termination schemes. Figures
5A and 5B show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist and
it would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
REVISION D 10/15/15
11
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
8430I-61 DATA SHEET
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 6A and Figure 6B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to VCC - 2V. For VCCO = 2.5V, the VCCO - 2V is very close to
ground level. The R3 in Figure 6B can be eliminated and the
termination is shown in Figure 6C.
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
250
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
+
+
Zo = 50 Ohm
Zo = 50 Ohm
-
-
2,5V LVPECL
Driv er
2,5V LVPECL
Driv er
R2
62.5
R1
50
R4
62.5
R2
50
R3
18
FIGURE 6B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 6A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 6C. 2.5V LVPECL TERMINATION EXAMPLE
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
12
REVISION D 10/15/15
8430I-61 DATA SHEET
LAYOUT GUIDELINE
actual system will depend on the selected component types,
the density of the components, the density of the traces, and
the stack up of the P.C. board.
The schematic of the 8430I-61 layout example used in this layout
guideline is shown in Figure 7A. The 8430I-61 recommended
PCB board layout for this example is shown in Figure 7B. This
layout example is used as a general guideline. The layout in the
C1
C2
X1
U1
VCC=3.3V
M5
M6
M7
M8
N0
N1
N2
VEE
XTAL_OUT
REF_IN
nXTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
VCC
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
Logic Input Pin Examples
VCC
Set Logic
Input to '1'
VCC
R7
10
VCCA
C11
0.01u
C16
10u
TEST
VCC
FOUT1
nFOUT1
VCCO
FOUT0
nFOUT0
VEE
SP = Spare Pads
M4
M3
M2
M1
M0
VCO_SEL
nP_LOAD
XTAL_IN
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
ICS8430-61
Set Logic
Input to '0'
VCC
VCC
R1
125
R3
125
Zo = 50 Ohm
RU1
1K
RU2
SP
To Logic
Input
pins
RD1
SP
C14
0.1u
To Logic
Input
pins
C15
0.1u
+
Zo = 50 Ohm
-
RD2
1K
R2
84
R4
84
FIGURE 7A. SCHEMATIC OF RECOMMENDED LAYOUT
REVISION D 10/15/15
13
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
8430I-61 DATA SHEET
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
• The traces with 50Ω transmission lines TL1 and TL2
at FOUT and nFOUT should have equal delay and
run adjacent to each other. Avoid sharp angles on the
clock trace. Sharp angle turns cause the characteristic
impedance to change on the transmission lines.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15 as close as possible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and
the power pin generated by the via.
• Keep the clock trace on the same layer. Whenever possible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the
power (ground) plane and the component power (ground) pins.
• Make sure no other signal trace is routed between the
clock trace pair.
If VCCA shares the same power supply with VCC, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the VCCA pin as possible.
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible. Other
termination schemes can also be used but are not shown in
this example.
CLOCK TRACES AND TERMINATION
The component placements, locations and orientations should
be arranged to achieve the best clock signal quality. Poor clock
signal quality can degrade the system performance or cause
system failure. In the synchronous high-speed digital system,
the clock signal is less tolerable to poor signal quality than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The trace shape and the trace
delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior
to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
24 (XTAL_OUT) and 25 (XTAL_IN). The trace length between
the X1 and U1 should be kept to a minimum to avoid unwanted
parasitic inductance and capacitance. Other signal traces should
not be routed near the crystal traces.
FIGURE 7B. PCB BOARD LAYOUT FOR 8430I-61
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
14
REVISION D 10/15/15
8430I-61 DATA SHEET
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 8430I-61.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 8430I-61 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 155mA = 537.1mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 537.1mW + 60mW = 597.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming
a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.597W * 42.1°C/W = 110.1°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 8. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
REVISION D 10/15/15
15
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
8430I-61 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
FIGURE 8. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination
voltage of VCCO- 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX - VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
16
REVISION D 10/15/15
8430I-61 DATA SHEET
RELIABILITY INFORMATION
TABLE 9. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for 8430I-61 is: 4258
REVISION D 10/15/15
17
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
8430I-61 DATA SHEET
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 10. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
N
MAXIMUM
32
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
e
0.80 BASIC
L
0.45
0.60
θ
0°
--
7°
ccc
--
--
0.10
0.75
Reference Document: JEDEC Publication 95, MS-026
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
18
REVISION D 10/15/15
8430I-61 DATA SHEET
TABLE 11. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
8430AYI-61LF
ICS8430AI61L
32 Lead “Lead-Free” LQFP
tray
-40°C to 85°C
8430AYI-61LFT
ICS8430AI61L
32 Lead “Lead-Free” LQFP
tape & reel
-40°C to 85°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
REVISION D 10/15/15
19
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
8430I-61 DATA SHEET
REVISION HISTORY SHEET
Rev
A
B
Table
Page
T7
1
6
1
T4C
T5
T11
T1
T4A
8
9
17
1
3
5
T7A
T7B
7
7
B
T11
C
2
6
6
9
17
10
13
D
D
T11
T11
19
21
19
Description of Change
Features Section - changed Supply Voltage bullet.
AC Table - Added 3V Note.
Features Section - added Lead-Free bullet.
Supply voltage bullet added supply modes.
Updated Parallel & Serial Load Operations Diagram.
LVPECL DC Characteristics Table added “NOTE: All DC parameters...”.
Crystal Characteristics Table - added Drive Level.
Recommendations for Unused Input and Output Pins.
Ordering Information Table - added Lead-Free part number and note.
Updated Output Load AC Test Circuit diagram.
Updated Recommendations for Unused Input and Output Pins.
Ordering Information Table - added lead-free marking.
Pin Assignment - swapped pins 24 & 25.
Pin Description table - pin 24 now XTAL_OUT and pin 25 now XTAL_IN.
Power Supply table - changed VCCA from 3.465V max. to VCC max., and
changed ICCA from 55mA max. to 15mA max. Added 2.5V output.
3.3V AC Characteristics table - added test condition to Period Jitter.
Added 3.3V/2.5V AC Characteristics table.
Corrected 3.3V Output Load AC Test Circuit Diagram.
Added 3.3V/2.5V Output Load AC Test Circuit Diagram.
Added LVCMOS to XTAL Interface section.
Updated Schematic Layout.
Updated datasheet’s header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
Ordering Information - removed leaded devices.
Updated data sheet format.
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
20
Date
10/21/04
7/12/05
2/17/06
6/2/06
7/27/10
10/15/15
REVISION D 10/15/15
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