Crystal-to-LVPECL Clock Synthesizer
ICS843156
DATA SHEET
General Description
ICS
HiPerClockS™
Features
The ICS843156 is a high frequency clock generator.
The ICS843156 uses an external 25MHz crystal to
synthesize 156.25MHz clock. The ICS843156 has
excellent cycle-to-cycle and RMS period jitter
performance.
The ICS843156 operates at full 3.3V and 2.5V, or mixed 3.3V/2.5V
operating supplies and is available in a fully RoHS compliant 32-lead
VFQFN package.
•
•
Ten differential LVPECL outputs of 156.25MHz
•
•
Cycle-to-cycle jitter: 40ps (maximum)
•
•
•
•
Output Duty Cycle: 45% – 55%
Crystal oscillator interface designed for 18pF, 25MHz parallel
resonant crystal
RMS phase jitter at 156.25MHz (1.875MHz - 20MHz):
0.39ps (typical)
Full 3.3V and 2.5V, or mixed 3.3V/2.5V supply modes
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Output Frequency Table
Crystal Frequency (MHz)
Feedback Divider
VCO Frequency (MHz)
Output Divider
Output Frequency (MHz)
25
25
625
÷4
156.25
nQA0
VCCO
QA0
VCCA
BYPASS
VEE
VCC
TEST_CLK
Pin Assignment
32 31 30 29 28 27 26 25
XTAL_IN
1
24 QA1
XTAL_OUT
2
23 nQA1
VCC 3
22 QA2
ICS843156
nQC1 4
21 nQA2
QC1
5
20 QA3
nQC0
6
19 nQA3
QC0 7
18 QA4
VCCO 8
BYPASS Pulldown
QA5
VCCO
VEE
nQA5
QB1
QB0
nQB1
10 11 12 13 14 15 16
nQB0
Block Diagram
17 nQA4
9
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
TEST_CLK Pulldown
1
25MHz
6
XTAL_IN
OSC
XTAL_OUT
÷4
nQA[0:5]
VCO
Phase
Detector
625MHz
QA[0:5]
K Package
Top View
0
2
÷4
QB[0:1]
nQB[0:1]
÷25
2
÷4
QC[0:1]
nQC[0:1]
ICS843156AK REVISION A DECEMBER 17, 2009
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©2009 Integrated Device Technology, Inc.
ICS843156 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Table 1. Pin Descriptions
Number
Name
Type
Description
1,
2
XTAL_IN
XTAL_OUT
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
3, 32
VCC
Power
Core supply pins.
4, 5
nQC1/QC1
Output
Differential output pair. LVPECL interface levels.
6, 7
nQC0/QC0
Output
Differential output pair. LVPECL interface levels.
8, 16, 25
VCCO
Power
Output supply pins.
9, 10
nQB1/QB1
Output
Differential output pair. LVPECL interface levels.
11, 12
nQB0/QB0
Output
Differential output pair. LVPECL interface levels.
13, 30
VEE
Power
Negative supply pins.
14, 15
nQA5/QA5
Output
Differential output pair. LVPECL interface levels.
17, 18
nQA4/QA4
Output
Differential output pair. LVPECL interface levels.
19, 20
nQA3/QA3
Output
Differential output pair. LVPECL interface levels.
21, 22
nQA2/QA2
Output
Differential output pair. LVPECL interface levels.
23, 24
nQA1/QA1
Output
Differential output pair. LVPECL interface levels.
26, 27
nQA0/QA0
Output
Differential output pair. LVPECL interface levels.
28
VCCA
Power
Analog supply pin.
29
BYPASS
Input
Pulldown
A HIGH on BYPASS signal allows TEST_CLK to propagate to output dividers and
bypass the PLL. a LOW on BYPASS signal allows VCO frequency to propagate
to the output dividers. See Table 3. LVCMOS/LVTTL interface levels.
31
TEST_CLK
Input
Pulldown
Single-ended input test clock. LVCMOS interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
Function Table
Table 3. Bypass Function Table
Input
BYPASS
Device Configuration
0
PLL Mode
1
Bypass the PLL
ICS843156AK REVISION A DECEMBER 17, 2009
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©2009 Integrated Device Technology, Inc.
ICS843156 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
37°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VCC – 0.33
3.3
VCC
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
179
mA
ICCA
Analog Supply Current
33
mA
Table 4B. Power Supply DC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Test Conditions
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
Analog Supply Voltage
VCC – 0.23
2.5
VCC
V
VCCO
Output Supply Voltage
2.375
2.5
2.625
V
IEE
Power Supply Current
168
mA
ICCA
Analog Supply Current
23
mA
Table 4C. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VCCO = 2.5V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VCC – 0.33
3.3
VCC
V
VCCO
Output Supply Voltage
2.375
2.5
2.625
V
IEE
Power Supply Current
164
mA
ICCA
Analog Supply Current
33
mA
ICS843156AK REVISION A DECEMBER 17, 2009
Test Conditions
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©2009 Integrated Device Technology, Inc.
ICS843156 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Table 4D. LVCMOS/LVTTL DC Characteristics, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
VIH
Input High Voltage
VCC = 3.3V
VIL
Input Low Voltage
IIH
Input High Current
BYPASS,
TEST_CLK
VCC = VIN = 3.465V or 2.625V
IIL
Input Low Current
BYPASS,
TEST_CLK
VCC = 3.465V or 2.625V, VIN = 0V
Typical
Maximum
Units
2
VCC + 0.3
V
VCC = 2.5V
1.7
VCC + 0.3
V
VCC = 3.3V
-0.3
0.8
V
VCC = 2.5V
-0.3
0.7
V
150
µA
-5
µA
Table 4E. LVPECL DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
VOH
Output High Voltage
VOL
Output Low Voltage
VSWING
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
Typical
Maximum
Units
VCCO - 1.4
VCCO - 0.9
V
VCCO - 2.0
VCCO - 1.7
V
0.6
1.0
V
Table 4F. LVPECL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VCCO = 2.5V ± 5%,VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
VOH
Output High Voltage
VOL
Output Low Voltage
VSWING
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
Typical
Maximum
Units
VCC – 1.4
VCC – 0.9
V
VCC – 2.0
VCC – 1.5
V
0.4
1.0
V
Table 5. Crystal Characteristics
Parameter
Test Conditions
Mode of Oscillation
Minimum
Typical
Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
ICS843156AK REVISION A DECEMBER 17, 2009
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©2009 Integrated Device Technology, Inc.
ICS843156 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
AC Electrical Characteristics
Table 6A. AC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
fOUT
Output Frequency
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 2
tR / t F
Output Rise/Fall Time
odc
Output Duty Cycle
tLOCK
PLL Lock Time
Test Conditions
Minimum
Typical
Maximum
156.25
MHz
40
156.25MHz,
Integration Range: 1.875MHz - 20MHz
0.39
20% to 80%
Units
ps
ps
200
700
ps
45
55
%
100
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.
NOTE 2: Refer to phase noise plot.
Table 6B. AC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
fOUT
Output Frequency
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
tjit(Ø)
RMS Phase Jitter, (Random)
tR / t F
Output Rise/Fall Time
odc
Output Duty Cycle
tLOCK
PLL Lock Time
Test Conditions
Minimum
Typical
Maximum
156.25
MHz
35
156.25MHz,
Integration Range: 1.875MHz - 20MHz
20% to 80%
Units
0.49
ps
ps
200
700
ps
45
55
%
100
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.
Table 6C. AC Characteristics, VCC = 3.3V ± 5%, VCCO = 2.5V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
fOUT
Output Frequency
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
tjit(Ø)
RMS Phase Jitter, (Random)
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
tLOCK
PLL Lock Time
Test Conditions
Minimum
Typical
Maximum
156.25
MHz
40
156.25MHz,
Integration Range: 1.875MHz - 20MHz
20% to 80%
Units
0.40
ps
ps
200
700
ps
45
55
%
100
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.
ICS843156AK REVISION A DECEMBER 17, 2009
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©2009 Integrated Device Technology, Inc.
ICS843156 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Typical Phase Noise at 156.25MHz @ 3.3V
Noise Power
dBc
Hz
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.39ps (typical)
Offset Frequency (Hz)
ICS843156AK REVISION A DECEMBER 17, 2009
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©2009 Integrated Device Technology, Inc.
ICS843156 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Parameter Measurement Information
2.8V±0.04V
2V
2V
2V
VCC,
VCCO
2.8V±0.04V
Qx
SCOPE
VCC
VCCO
VCCA
VCCA
LVPECL
Qx
SCOPE
LVPECL
nQx
nQx
VEE
VEE
-1.3V±0.165V
-0.5V±0.125V
3.3V Core/ 2.5V LVPECL Output Load AC Test Circuit
3.3V Core/ 3.3V LVPECL Output Load AC Test Circuit
2V
Phase Noise Plot
VCC,
VCCO
Qx
Noise Power
2V
SCOPE
VCCA
LVPECL
nQx
f1
VEE
Offset Frequency
f2
RMS Jitter = Area Under Offset Frequency Markers
-0.5V±0.125V
RMS Phase Jitter
2.5V Core/ 2.5V LVPECL Output Load AC Test Circuit
nQAx,
nQBx,
nQCx
QAx, QBx, QCx
t PW
t
tcycle n
➤
➤
QAx,
QBx,
QCx
nQAx, nQBx, nQCx
➤
tcycle n+1
➤
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
odc =
t PW
x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
Cycle-to-Cycle Jitter
ICS843156AK REVISION A DECEMBER 17, 2009
PERIOD
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©2009 Integrated Device Technology, Inc.
ICS843156 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Parameter Measurement Information, continued
nQAx,
nQBx,
nQCx
80%
QAx,
QBx,
QCx
80%
VSW I N G
20%
20%
tR
tF
LVPECL Output Rise/Fall Time
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform ance,
power supply isolation is required. TheICS843156 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. VCC, VCCA and VCCO should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic VCC pin and also shows that VCCA requires that an
additional 10Ω resistor along with a 10µF bypass capacitor be
connected to the VCCA pin.
ICS843156AK REVISION A DECEMBER 17, 2009
3.3V
VCC
.01µF
10Ω
.01µF
10µF
VCCA
Figure 1. Power Supply Filtering
8
©2009 Integrated Device Technology, Inc.
ICS843156 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Crystal Input Interface
The ICS843156 has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 2 below
were determined using a 25MHz, 18pF parallel resonant crystal and
were chosen to minimize the ppm error. The optimum C1 and C2
values can be slightly adjusted for different board layouts.
XTAL_IN
C1
27pF
X1
18pF Parallel Crystal
XTAL_OUT
C2
27pF
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The input
edge rate can be as slow as 10ns. For LVCMOS signals, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
VCC
the transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done in
one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1 and R2
can be 100Ω. This can also be accomplished by removing R1 and
making R2 50Ω. By overdriving the crystal oscillator, the device will
be functional, but note, the device performance is guaranteed by
using a quartz crystal.
VCC
R1
Ro
Rs
0.1µf
50Ω
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
ICS843156AK REVISION A DECEMBER 17, 2009
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©2009 Integrated Device Technology, Inc.
ICS843156 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
TEST_CLK Input
LVPECL Outputs
For applications not requiring the use of the test clock, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the TEST_CLK to ground.
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied from
XTAL_IN to ground.
LVCMOS Control Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
R3
125Ω
3.3V
3.3V
Zo = 50Ω
3.3V
R4
125Ω
3.3V
3.3V
+
Zo = 50Ω
+
_
LVPECL
Input
Zo = 50Ω
R1
50Ω
_
LVPECL
R2
50Ω
R1
84Ω
VCC - 2V
RTT =
1
* Zo
((VOH + VOL) / (VCC – 2)) – 2
Input
Zo = 50Ω
R2
84Ω
RTT
Figure 4A. 3.3V LVPECL Output Termination
ICS843156AK REVISION A DECEMBER 17, 2009
Figure 4B. 3.3V LVPECL Output Termination
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©2009 Integrated Device Technology, Inc.
ICS843156 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Termination for 2.5V LVPECL Outputs
level. The R3 in Figure 5B can be eliminated and the termination is
shown in Figure 5C.
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50Ω
to VCC – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
R1
250
R3
250
50Ω
+
50Ω
+
50Ω
–
50Ω
2.5V LVPECL Driver
–
R1
50
2.5V LVPECL Driver
R2
62.5
R2
50
R4
62.5
R3
18
Figure 5A. 2.5V LVPECL Driver Termination Example
Figure 5B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50
R2
50
Figure 5C. 2.5V LVPECL Driver Termination Example
ICS843156AK REVISION A DECEMBER 17, 2009
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©2009 Integrated Device Technology, Inc.
ICS843156 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS843156.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS843156 is the sum of the core power plus the power dissipation in the load(s).
The following is the power dissipation for VCCO = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.
•
Power (core)MAX = VCCO_MAX * IEE_MAX = 3.465V * 179mA = 620.235mW
•
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 30mW = 300mW
Total Power_MAX (3.3V, with all outputs switching) = 620.235mW + 300mW = 920.235mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C. Limiting the internal transistor junction temperature, Tj, to
125°C ensures that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 37°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.920W * 37°C/W = 104°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection
θJA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
ICS843156AK REVISION A DECEMBER 17, 2009
0
1
2.5
37.0°C/W
32.4°C/W
29.0°C/W
12
©2009 Integrated Device Technology, Inc.
ICS843156 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
The LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50Ω
VCC - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of
VCCO – 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCC_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCC_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
ICS843156AK REVISION A DECEMBER 17, 2009
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©2009 Integrated Device Technology, Inc.
ICS843156 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Reliability Information
Table 8. θJA vs. Air Flow Table for a 32 Lead VFQFN
θJA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
37.0°C/W
32.4°C/W
29.0°C/W
Transistor Count
The transistor count for ICS843156 is: 3059
ICS843156AK REVISION A DECEMBER 17, 2009
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©2009 Integrated Device Technology, Inc.
ICS843156 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
A3
N
To p View
Anvil
Anvil
Singulation
Singula tion
or
OR
Sawn
Singulation
L
N
e (Ty p.)
2 If N & N
1
are Even
2
E2
(N -1)x e
(Re f.)
E2
2
b
A
(Ref.)
D
e
N &N
Odd
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
0. 08
Th er mal
Ba se
D2
2
C
D2
C
Bottom View w/Type A ID
Bottom View w/Type B ID
Bottom View w/Type C ID
BB
4
CHAMFER
4
N N-1
There are 3 methods of indicating pin 1 corner
at the back of the VFQFN package are:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type B: Dummy pad between pin 1 and N.
3. Type C: Mouse bite on the paddle (near pin 1)
2
1
2
1
CC
2
1
4
N N-1
DD
4
RADIUS
4
N N-1
AA
4
Table 9. Package Dimensions
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 9 below.
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.25
0.30
8
ND & NE
D&E
5.00 Basic
D2 & E2
3.0
3.3
e
0.50 Basic
L
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
ICS843156AK REVISION A DECEMBER 17, 2009
15
©2009 Integrated Device Technology, Inc.
ICS843156 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Ordering Information
Table 10. Ordering Information
Part/Order Number
843156AKLF
843156AKLFT
Marking
ICS843156AL
ICS843156AL
Package
“Lead-Free” 32 Lead VFQFN
“Lead-Free” 32 Lead VFQFN
Shipping Packaging
Tray
2500 Tape & Reel
Temperature
0°C to 70°C
0°C to 70°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product
for use in life support devices or critical medical instruments.
ICS843156AK REVISION A DECEMBER 17, 2009
16
©2009 Integrated Device Technology, Inc.
ICS843156 Data Sheet
6024 Silver Creek Valley Road
San Jose, California 95138
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Sales
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
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