FemtoClock® 680MHz Crystal-to-3.3V
Differential LVPECL Frequency Synthesizer
843202I
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
DATA SHEET
GENERAL DESCRIPTION
FEATURES
The 843202I is a 2 output LVPECL Synthesizer optimized to generate
Gigabit Ethernet and SONET reference clock frequencies and is
a member of the family of high performance clock solutions from
IDT. Using a 19.44MHz and 25MHz, 18pF parallel resonant crystal,
155.52MHz and 156.25MHz frequencies can be generated. The part
also allows the use of a recovered clock at QB output. The 843202I
uses IDT’s FemtoClockTM low phase noise VCO technology and can
achieve 1ps or lower typical RMS phase jitter. The 843202I is
packaged in a 32-pin LQFP package.
• Two 3.3V LVPECL outputs
• Selectable crystal oscillator interface or one differential recovered clock inputs
• Supports the following output frequencies: 155.52MHz and
156.25MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal
(12kHz – 1.3MHz): 0.86ps (typical)
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz –- 20MHz): 0.56ps (typical)
SELBX FUNCTION TABLE
• Full 3.3V supply mode
Control Inputs
Outputs
SEL[1:0]
nQB, QB
00
High, Low
01
REC_CLK
10
156.25MHz driven by XTAL_0
11
155.52MHz driven by XTAL_1
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• For functional replacement part use 8T49N242
BLOCK DIAGRAM
PIN ASSIGNMENT
00
REC_CLK Pulldown
01
nREC_CLK Pullup
QB
nQB
10
19.44MHz
VCO
622.08MHz
VEE
÷25
÷4
24
2
23
VCC
XTAL_IN1
3
22
VCCA
XTAL_OUT1
4
21
SEL0
nc
5
20
VEE
REC_CLK
6
19
OEB
nREC_CLK
7
18
VCC
VCCO_B
8
17
SEL1
OEA
9 10 11 12 13 14 15 16
VCCA
nc
nc
nc
nc
nQB
155.52MHz
1
nc
QB
11
XTAL_OUT1
32 31 30 29 28 27 26 25
VCCO_A
nc
Phase
Detector
nc
nQA
156.25MHz
OSC
XTAL_OUT0
÷4
XTAL_OUT0
XTAL_IN1
nc
625MHz
QA
QA
VCO
Phase
Detector
nc
OSC
nQA
25MHz
XTAL_IN0
XTAL_IN0
OEA Pullup
843202I
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y Package
Top View
÷32
SEL[1:0] Pullup
OEB Pullup
843202I REVISION A 5/26/16
1
©2016 Integrated Device Technology, Inc.
843202I DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
1
VCCO_A
Power
2, 5, 9, 12, 13,
14, 15, 26, 29, 32
nc
Unused
3,
4
XTAL_IN1, XTAL_
OUT1
Input
Description
Output supply pin for Bank A output.
No connect.
Parallel resonant crystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
6
REC_CLK
Input
7
nREC_CLK
Input
Pulldown Non-inverting differential recovered clock inputs.
8
VCCO_B
Power
10, 11
QB, nQB
Ouput
Differential output pair. LVPECL interface levels.
16, 22
VCCA
Power
Analog supply pins.
17, 21
SEL1, SEL0
Input
18, 23
VCC
Power
19
OEB
Input
20, 25
VEE
Power
24
OEA
Input
27, 28
XTAL_OUT0,
XTAL_IN0
Input
30, 31
nQA, QA
Output
Pullup
Inverting differential recovered clock inputs.
Output supply pin for Bank B output.
Pullup
Select pins. See SELx Function Table.
LVCMOS/LVTTL interface levels.
Core supply pins.
Pullup
Output enable pin. QB/nQB output is enabled.
LVCMOS/LVTTL interface levels.
Negative supply pins.
Pullup
Output enable pin. QA/nQA output is enabled.
LVCMOS/LVTTL interface levels.
Parallel resonant crystal interface. XTAL_OUT0 is the output,
XTAL_IN0 is the input.
Differential output pair. LVPECL interface levels.
NOTE: refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Pullup
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
FEMTOCLOCK® 680MHZ, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Test Conditions
2
Minimum
Typical
Maximum
Units
REVISION A 5/26/16
843202I DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
80.8°C/W (0 mps)
implied. Exposure to absolute maximum rating conditions for ex-
Storage Temperature, TSTG
-65°C to 150°C
tended periods may affect product reliability.
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±10%, TA = -40°C TO 85°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
VCCO_A,
VCCO_B
Test Conditions
Minimum
Typical
Maximum
Units
2.97
3.3
3.63
V
Analog Supply Voltage
VCC – 0.22
3.3
VCC
V
Output Supply Voltage
2.97
3.3
3.63
V
IEE
Power Supply Current
138
mA
ICCA
Analog Supply Current
22
mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±10%, TA = -40°C TO 85°C
Symbol
Parameter
VIH
VIL
Input High Voltage
Input
Low Voltage
IIH
Input High Current
IIL
Input Low Current
Test Conditions
OEA, OEB,
SEL0, SEL1
OEA, OEB,
SEL0, SEL1
Minimum
Maximum
Units
2
Typical
VCC + 0.3
V
-0.3
0.8
V
5
µA
VCC = VIN = 3.63V
-150
VCC = 3.63V, VIN = 0V
µA
TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±10%, TA = -40°C TO 85°C
Symbol
Parameter
Maximum
Units
REC_CLK
VCC = VIN = 3.465V
Test Conditions
150
µA
nREC_CLK
VCC = VIN = 3.465V
5
µA
REC_CLK
VCC = 3.63V, VIN = 0V
-5
µA
nREC_CLK
VCC = 3.63V, VIN = 0V
-150
µA
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
VCMR
Common Mode Input Voltage;
NOTE 1
Minimum
Typical
0.15
1.3
V
VEE + 0.5
VCC – 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
REVISION A 5/26/16
3
FEMTOCLOCK® 680MHZ, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
843202I DATA SHEET
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±10%, TA = -40°C TO 85°C
Symbol
Parameter
Maximum
Units
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
VCCO - 1.4
Typical
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
Maximum
Units
NOTE 1: Outputs terminated with 50Ω to VCCO_A, _B - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
19.44
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 5. AC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±10%, TA = -40°C TO 85°C
Symbol
fOUT
Parameter
Output Frequency
QB/nQB
Test Conditions
Minimum
Typical
Maximum
Units
PLL Mode
140
155.52
170
MHz
140
156.25
170
MHz
QA/nQA
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 1
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
155.52MHz, (12kHz - 1.3MHz)
0.86
ps
156.25MHz, (1.875MHz - 20MHz)
0.56
ps
PLL Mode, 20% to 80%
300
550
ps
PLL Mode
49
51
%
All parameters measured up to 170MHz unless otherwise specified.
NOTE 1: See Phase Noise plots.
FEMTOCLOCK® 680MHZ, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
4
REVISION A 5/26/16
843202I DATA SHEET
TYPICAL PHASE NOISE AT 155.52MHZ
➤
0
-10
-20
Filter
-30
-50
155.52MHz
-60
RMS Phase Jitter (Random)
12kHz to 1.3MHz = 0.86ps (typical)
-70
-80
-90
Raw Phase Noise Data
-100
➤
NOISE POWER dBc
Hz
-40
-110
-120
➤
-130
-140
-150
Phase Noise Result by adding
a Filter to raw data
-160
-170
-180
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 156.25MHZ
➤
0
-10
-20
Filter
-30
-40
-50
156.25MHz
-60
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.56ps (typical)
-80
-90
Raw Phase Noise Data
-100
➤
NOISE POWER dBc
Hz
-70
-110
-120
-130
-140
-150
➤
-160
-170
-180
Phase Noise Result by adding
a Filter to raw data
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
REVISION A 5/26/16
5
FEMTOCLOCK® 680MHZ, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
843202I DATA SHEET
PARAMETER MEASUREMENT INFORMATION
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
FEMTOCLOCK® 680MHZ, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
6
REVISION A 5/26/16
843202I DATA SHEET
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The 843202I provides separate power
supplies to isolate any high switching noise from the outputs to the
internal PLL. VCC, VCCA, and VCCO_x should be individually connected
to the power supply plane through vias, and bypass capacitors
should be used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how a 10Ω
resistor along with a 10µF and a .01μF bypass capacitor should be
connected to each VCCA.
3.3V
VCC
.01μF
10Ω
VCCA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The 843202I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2 below
were determined using an 18pF parallel resonant crystal and
were chosen to minimize the ppm error.
843
843202I
84
843
432
202
20
02I
02
FIGURE 2. CRYSTAL INPUt INTERFACE
REVISION A 5/26/16
7
FEMTOCLOCK® 680MHZ, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
843202I DATA SHEET
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it
is recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be done
in one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1 and
R2 can be 100Ω. This can also be accomplished by removing R1
and making R2 50Ω.
VDD
VDD
R1
Ro
Rs
.1uf
Zo = 50
Zo = Ro + Rs
XTAL_IN
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
INPUTS:
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
REC_CLK/nREC_CLK INPUT:
For applications not requiring the use of the differential input,
both REC_CLK and nREC_CLK can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from REC_CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
FEMTOCLOCK® 680MHZ, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
8
REVISION A 5/26/16
843202I DATA SHEET
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.
lines. Matched impedance techniques should be used to maximize
operating frequency and minimize signal distortion. Figures 4A
and 4B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it would
be recommended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component process
variations.
FOUT and nFOUT are low impedance follower outputs that generate
ECL/LVPECL compatible outputs. Therefore, terminating resistors
(DC current path to ground) or current sources must be used for
functionality. These outputs are designed to drive 50Ω transmission
FIGURE 4A. LVPECL OUTPUT TERMINATION
REVISION A 5/26/16
FIGURE 4B. LVPECL OUTPUT TERMINATION
9
FEMTOCLOCK® 680MHZ, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
843202I DATA SHEET
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 843202I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 843202I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 138mA = 500.9mW
•
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.63V, with all outputs switching) = 500.9mW + 60mW = 560.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 71.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.561W * 71.2°C/W = 124.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the
type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θJA by Velocity (Meter per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards
FEMTOCLOCK® 680MHZ, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
80.8°C/W
10
1
2.5
71.2°C/W
67.6°C/W
REVISION A 5/26/16
843202I DATA SHEET
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of VCCO- 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX - VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
REVISION A 5/26/16
11
FEMTOCLOCK® 680MHZ, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
843202I DATA SHEET
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA by Velocity (Meter per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards
80.8°C/W
1
2.5
71.2°C/W
67.6°C/W
TRANSISTOR COUNT
The transistor count for 843202I is: 3733
FEMTOCLOCK® 680MHZ, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
12
REVISION A 5/26/16
843202I DATA SHEET
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
N
MAXIMUM
32
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
e
0.80 BASIC
L
0.45
0.60
θ
0°
--
7°
ccc
--
--
0.10
0.75
Reference Document: JEDEC Publication 95, MS-026
REVISION A 5/26/16
13
FEMTOCLOCK® 680MHZ, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
843202I DATA SHEET
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS843202AYILF
ICS843202AIL
32 Lead “Lead-Free” LQFP
tray
-40°C to 85°C
ICS843202AYILFT
ICS843202AIL
32 Lead “Lead-Free” LQFP
tape & reel
-40°C to 85°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
FEMTOCLOCK® 680MHZ, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
14
REVISION A 5/26/16
843202I DATA SHEET
REVISION HISTORY SHEET
Rev
A
A
REVISION A 5/26/16
Table
Page
T9
14
Description of Change
Ordering Information - removed leaded devices.
Updated data sheet format.
Product Discontinuation Notice - Last time buy expires May 6, 2017.
PDN CQ-16-01
15
Date
10/15/15
5/26/16
FEMTOCLOCK® 680MHZ, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
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San Jose, California 95138
Sales
800-345-7015 or +408-284-8200
Fax: 408-284-2775
www.IDT.com
Technical Support
email: clocks@idt.com
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