843204AGI-01LFT

FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer 843204I-01 DATA SHEET GENERAL DESCRIPTION FEATURES The 843204I-01 is a 4 output LVPECL Synthe-sizer optimized to generate Gigabit Ethernet and SONET reference clock frequencies and is a member of the HiPerClocks TM family of high perfor mance clock solutions from IDT. Using a 19.44MHz and 25MHz, 18pF parallel resonant crystal, 155.52MHz and 156.25MHz frequencies can be generated. The 843204I-01 uses IDT’s FemtoClockTM low phase noise VCO technology and can achieve 1ps or lower typical RMS phase jitter. • Four 3.3V LVPECL outputs • Selectable crystal oscillator interface or clock inputs • Supports the following output frequencies: 155.52MHz and 156.25MHz • VCO range: 560MHz - 680MHz • RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal (12kHz - 13MHz): 0.6ps (typical) • RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.7ps (typical) • Full 3.3V supply mode • -40°C to 85°C ambient operating temperature • Available in lead-free (RoHS 6) package • For functional replacement part us 8T49N285 BLOCK DIAGRAM PIN ASSIGNMENT nPLL_BYPASS_A Pullup IN_SELA Pullup CLK0 Pulldown SELA0 OEA0 25MHz XTAL_IN0 OSC PLL ÷4 XTAL_OUT0 156.25MHz QA0 0 nQA0 1 SELA1 625MHz OEA1 nPLL_BYPASS_B Pullup IN_SELB Pullup CLK1 QA1 0 nQA1 1 Pulldown SELB0 nCLK1 Pullup/pulldown OEB0 19.44MHz QB0 0 XTAL_IN1 OSC PLL ÷4 XTAL_OUT1 155.52MHz 1 1 843204I-01 REVISION A 11/5/15 1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 IN_SELA CLK0 XTAL_IN0 XTAL_OUT0 nc VEE OEA0 OEA1 VCC VCCA nPLL_BYPASS_B nc SELB0 VEE OEB0 OEB1 VCC SELB1 VCCA nc nc nc nc nc 843204I-01 OEB1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 nQB0 SELB0 622.08MHz nQA1 QA1 nQA0 QA0 nc VCCO_A SELA1 SELA0 nPLL_BYPASS_A nc nc nc nc XTAL_IN1 XTAL_OUT1 CLK1 nCLK1 IN_SELB VCCO_B nc QB0 nQB0 QB1 nQB1 QB1 nQB1 48 Lead TSSOP 6.1mm x 12.5mm x 0.925mm package body G Package Top View ©2015 Integrated Device Technology, Inc. 843204I-01 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 nQA1, QA1 Output Type Description Differential output pair. LVPECL interface levels. Output Differential output pair. LVPECL interface levels. 3, 4 nQA0, QA0 5, 10, 11, 12, 13, 20, 25, 26, 27, 28, 29, 37, 44 nc 6 VCCO_A Power 7 SELA1 Input 8 SELA0 Input 9 nPLL_BYPASS_A Input 14, 15 XTAL_IN1, XTAL_ OUT1 Input 16 CLK1 Input 17 nCLK1 Input 18 IN_SELB Input 19 VCCO_B Power Output supply pin for Bank B outputs. 21, 22 QB0, nQB0 Ouput Differential output pair. LVPECL interface levels. 23, 24 QB1, nQB1 Ouput Differential output pair. LVPECL interface levels. 30, 39 VCCA Power Analog supply pins. 31 SELB1 Input 32, 40 VCC Power 33 OEB1 Input Pullup 34 OEB0 Input Pullup 35, 43 VEE Power 36 SELB0 Input Pullup Select pin. When HIGH, selects QB0/nQB0 at 155.52MHz. When LOW, selects QB0/nQB0 at 156.25MHz. LVCMOS/LVTTL interface levels. 38 nPLL_BYPASS_B Input Pullup When LOW, PLL is bypassed. When HIGH, PLL output is active. 41 OEA1 Input Pullup 42 OEA0 Input Pullup 45, 46 XTAL_OUT0, XTAL_IN0 Input 47 CLK0 Input 48 IN_SELA Input Unused No connect. Output supply pin for Bank A outputs. Select pin. When HIGH, selects QA1/nQA1 at 155.52MHz. When LOW, selects QA1/nQA1 at 156.25MHz. LVCMOS/LVTTL interface levels. Select pin. When HIGH, selects QA0/nQA0 at 155.52MHz. When LOW, Pulldown selects QA1/nQA1 at 156.25MHz. LVCMOS/LVTTL interface levels. Pulldown Pullup When LOW, PLL is bypassed. When HIGH, PLL output is active. Parallel resonant crystal interface. XTAL_OUT1 is the output, XTAL_IN1 is the input. Pulldown Non-inverting differential clock input. Pullup/ Inverting differential clock input. VDD/2 bias voltage when left floating. Pulldown Select pin. When HIGH, selects XTAL1 inputs. When LOW, selects CLK1, Pullup nCLK1 inputs. LVCMOS/LVTTL interface levels. Pullup Select pin. When HIGH, selects QB1/nQB1 at 155.52MHz. When LOW, selects QB1/nQB1 at 156.25MHz. LVCMOS/LVTTL interface levels. Core supply pins. Output enable pin. QB1/nQB1 outputs are enable. LVCMOS/LVTTL interface levels. Output enable pin. QB0/nQB0 outputs are enabled. LVCMOS/LVTTL interface levels. Negative supply pins. Output enable pin. QA1/nQA1 outpus are enabled. LVCMOS/LVTTL interface levels. Output enable pin. QA0/nQA0 outputs are enabled. LVCMOS/LVTTL interface levels. Parallel resonant crystal interface. XTAL_OUT0 is the output, XTAL_IN0 is the input. Pulldown LVCMOS/LVTTL clock input. Pullup Select pin. When HIGH, selects XTAL0 inputs. When LOW, selects CLK0 input. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 RPULLDOWN Input Pulldown Resistor 51 k RPULLUP Input Pullup Resistor 51 k FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER Test Conditions 2 Minimum Typical Maximum Units pF Ω Ω REVISION A 11/5/15 843204I-01 DATA SHEET ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 54.8°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±10%, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum VCC Core Supply Voltage VCCA Analog Supply Voltage VCCO_A, VCCO_B Output Supply Voltage 2.97 IEE ICCA Units 2.97 3.3 3.63 V VCC – 0.22 3.3 VCC V 3.3 3.63 V Power Supply Current 165 mA Analog Supply Current 22 mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±10%, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current REVISION A 11/5/15 Test Conditions Minimum 2 -0.3 Typical Maximum Units VCC + 0.3 V 0.8 V CLK0, SELA0, SELA1 VCC = VIN = 3.63V 150 µA nPLL_BYPASS_A, nPLL_BYPASS_B, IN_ SELA, IN_SELB, SELB1, SELB0, OEB0, OEB1, OEA0, OEA1 VCC = VIN = 3.63V 5 µA CLK0, SELA0, SELA1 VCC = 3.63V, VIN = 0V -5 µA nPLL_BYPASS_A, nPLL_BYPASS_B, IN_ SELA, IN_SELB, SELB1, SELB0, OEB0, OEB1, OEA0, OEA1 VCC = 3.63V, VIN = 0V -150 µA 3 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER 843204I-01 DATA SHEET TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±10%, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage; NOTE 1 Test Conditions CLK1, nCLK1 Minimum Typical Maximum VIN = VCC = 3.63V 150 Units µA nCLK1 VIN = 0V, VCC = 3.63V -150 µA CLK1 VIN = 0V, VCC = 3.63V -5 µA Common Mode Input Voltage; VCMR NOTE 1, 2 NOTE 1: VIL should not be less than -0.3V NOTE 2: Common mode voltage is defined as VIH. 0.15 1.3 V VEE + 0.5 VCC - 0.85 V Maximum Units TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±10%, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical VOH Output High Voltage; NOTE 1 VCCO - 1.4 VCCO - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Maximum Units NOTE 1: Outputs terminated with 50 to VCCO - 2V. Ω TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Frequency Typical Fundamental XTAL0 25 MHz XTAL1 19.44 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units NOTE: Characterized using an 18pF parallel resonant crystal. TABLE 5. AC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±10%, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency tsk(b) Bank Skew; NOTE 1, 2 tjit(Ø) RMS Phase Jitter (Random); NOTE 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical SELB0 = 1; OEB0 = 1 155.52 MHz SELA0 = 0; OEA0 = 1 156.25 MHz 60 ps 155.52MHz, (12kHz - 1.3MHz) 0.6 ps 156.25MHz, (1.875MHz - 20MHz) 0.7 ps 20% to 80% 250 600 ps 47 53 % NOTE 1: Defined as skew within a bank of outputs at the same supply voltags and with equal load conditions. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: See Phase Noise plot. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER 4 REVISION A 11/5/15 843204I-01 DATA SHEET PARAMETER MEASUREMENT INFORMATION 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL RMS PHASE JITTER BANK SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME REVISION A 11/5/15 5 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER 843204I-01 DATA SHEET APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 843204I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each VCCA. 3.3V VCC .01μF 10Ω VCCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The 843204I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 27pF X1 18pF Parallel Crystal XTAL_OUT C2 27pF FIGURE 2. CRYSTAL INPUt INTERFACE FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER 6 REVISION A 11/5/15 843204I-01 DATA SHEET LVCMOS TO XTAL INTERFACE The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. VDD VDD R1 Ro .1uf Rs Zo = 50 XTAL_IN R2 Zo = Ro + Rs XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 4 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/ R1 = 0.609. VCC R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 4. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT REVISION A 11/5/15 7 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER 843204I-01 DATA SHEET RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CLK INPUT For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. CLK/nCLK INPUTS For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission FIGURE 5A. LVPECL OUTPUT TERMINATION FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER FIGURE 5B. LVPECL OUTPUT TERMINATION 8 REVISION A 11/5/15 843204I-01 DATA SHEET POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 843204I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 843204I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 165mA = 598.95mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power_MAX (3.63V, with all outputs switching) = 598.95mW + 120mW = 718.95mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assumig no air flow and a multi-layer board, the appropriate value is 54.8°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.719W * 54.8°C/W = 124.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 48-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards REVISION A 11/5/15 0 54.8°C/W 9 1 51.0°C/W 2.5 49.1°C/W FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER 843204I-01 DATA SHEET 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO- 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER 10 REVISION A 11/5/15 843204I-01 DATA SHEET RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 48 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 54.8°C/W 1 51.0°C/W 2.5 49.1°C/W TRANSISTOR COUNT The transistor count for 843204I-01 is: 3974 PACKAGE OUTLINE - G SUFFIX FOR 48 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 48 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.17 0.27 c 0.09 0.20 D 12.40 E 12.60 8.10 BASIC E1 6.00 e 6.20 0.50 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 REVISION A 11/5/15 11 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER 843204I-01 DATA SHEET TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 843204AGI-01LF ICS843204AI01L 843204AGI-01LFT ICS843204AI01L 48 Lead “Lead-Free” TSSOP tube -40°C to 85°C 48 Lead “Lead-Free” TSSOP tape & reel -40°C to 85°C NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER 12 REVISION A 11/5/15 843204I-01 DATA SHEET REVISION HISTORY SHEET Rev Table Page 1 A REVISION A 11/5/15 T9 12 Description of Change Product Discontinuation Notice - Last time buy expires November 2, 2016. PDN# CQ-15-05. Ordering Information - Removed leaded devices and ICS from orderable part number. Updated data sheet format. 13 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER Date 11/5/15 Corporate Headquarters 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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