FemtoClock® Crystal-To-3.3V LVPECL
Frequency Synthesizers
843242
DATASHEET
General Description
Features
The 843242 is a two differential output LVPECL Synthesizer
designed to generate Ethernet reference clock frequencies. Using a
31.25MHz or 26.041666MHz, 18pF parallel resonant crystal, the
following frequencies can be generated based on the settings of 4
frequency select pins (SELA[1:0], SELB[1:0]): 625MHz, 312.5MHz,
156.25MHz, and 125MHz.
•
•
Two differential LVPECL output pairs
•
•
Crystal oscillator interface
•
•
•
Full 3.3V supply mode
The two banks have their own dedicated frequency select pins and
can be independently set for the frequencies mentioned above. The
843242 IDT’s 3rd generation low phase noise VCO technology and
can achieve 1ps or lower typical rms phase jitter, easily meeting
Ethernet jitter requirements. The 843242 is packaged in a small
16-pin TSSOP package.
Using a 31.25MHz or 26.041666MHz crystal, the two output
banks can be independently set for 625MHz, 312.5MHz,
156.25MHz or 125MHz
RMS Phase Jitter @ 625MHz, (1.875MHz – 20MHz) using a
25MHz crystal: 0.4ps (typical)
0°C to 70°C ambient operating temperature
Lead-free (RoHS 6) packaging
Pin Assignment
nQB
1
16
XTAL_IN
QB
2
15
VCCO_B
3
14
XTAL_OUT
VEE
SELB1
SELB0
VCCO_A
QA
nQA
4
13
5
12
6
11
7
10
8
9
SELA1
SELA0
VCC
VCCA
FB_SEL
843242
16-pin, 4.4mm x 5.0mm TSSOP Package (173 mil)
Block Diagram
SELA[1:0]
0 = Pullup
1 = Pulldown
XTAL_IN
OSC
XTAL_OUT
2
Phase
Detector
31.25MHz
or
26.041666MHz
FB_SEL
SELB[1:0]
843242 REVISION 1 1/30/15
VCO
625MHz
Feedback Divider
0 = ÷20 (default)
1 = ÷24
Pulldown
0 = Pulldown
1 = Pullup
00
01
10
11
÷1
÷2
÷4 (default)
÷5
00
01
10
11
÷1
÷2
÷4 (default)
÷5
QA
nQA
QB
nQB
2
1
©2015 Integrated Device Technology, Inc.
843242 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
Name
Type
Description
1
nQB
Output
Differential clock outputs. LVPECL interface levels.
2
QB
Output
Differential clock outputs. LVPECL interface levels.
3
VCCO_B
Power
Output supply pin for QB, nQB outputs.
4
SELB1
Input
Pullup
Division select pin for Bank B. Default = High.
LVCMOS/LVTTL interface levels.
5
SELB0
Input
Pulldown
Division select pins for Bank B. Default = Low.
LVCMOS/LVTTL interface levels.
6
VCCO_A
Power
Output supply pin for QA, nQA outputs.
7
QA
Output
Differential clock outputs. LVPECL interface levels.
8
nQA
Output
Differential clock outputs. LVPECL interface levels.
9
FB_SEL
Input
10
VCCA
Power
Analog supply pin.
11
VCC
Power
Core supply pin.
12
SELA0
Input
Pullup
Division select pin for Bank A. Default = High.
LVCMOS/LVTTL interface levels.
13
SELA1
Input
Pulldown
Division select pin for Bank A. Default = Low.
LVCMOS/LVTTL interface levels.
14
VEE
Power
Negative supply pin.
15
XTAL_OUT
Input
Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output.
16
XTAL_IN
Input
Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output.
Pulldown
Feedback divide select. When LOW (default), the feedback divider is set for
÷20. When HIGH, the feedback divider is set for ÷24. LVCMOS/LVTTL
interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
SELA[1:0], SELB[1:0], FB_SEL
Minimum
2
REVISION 1 1/30/15
ICS843242 DATA SHEET
Function Tables
Table 3A. Bank A Frequency Table
Inputs
Crystal Frequency
(MHz)
SELA1
SELA0
FB_SEL
Feedback
Divider
Bank A
Output Divider
M/N
Multiplication
Factor
QA, nQA
Output Frequency
(MHz)
31.25
0
0
0
20
1
20
625
31.25
0
1
0
20
2
10
312.5
31.25
1
0
0
20
4
5
156.25
31.25
1
1
0
20
5
4
125
26.041666
0
0
1
24
1
24
625
26.041666
0
1
1
24
2
12
312.5
26.041666
1
0
1
24
4
6
156.25
26.041666
1
1
1
24
5
4.8
125
Bank B
Output Divider
M/N
Multiplication
Factor
QB, nQB
Output Frequency
(MHz)
Table 3B. Bank B Frequency Table
Inputs
Crystal Frequency
(MHz)
SELB1
SELB0
FB_SEL
Feedback
Divider
31.25
0
0
0
20
1
20
625
31.25
0
1
0
20
2
10
312.5
31.25
1
0
0
20
4
5
156.25
31.25
1
1
0
20
5
4
125
26.041666
0
0
1
24
1
24
625
26.041666
0
1
1
24
2
12
312.5
26.041666
1
0
1
24
4
6
156.25
26.041666
1
1
1
24
5
4.8
125
Table 3C. Output Bank Configuration Select Function Table
Inputs
Outputs
Inputs
Outputs
SELA1
SELA0
QA
SELB1
SELB0
QB
0
0
÷1
0
0
÷1
0
1
÷2 (default)
0
1
÷2
1
0
÷4
1
0
÷4 (default)
1
1
÷5
1
1
÷5
Table 3D. Feedback Divider Configuration Select Function Table
Inputs
FB_DIV
Feedback Divide
0
÷20 (default)
1
÷24
REVISION 1 1/30/15
3
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
843242 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Junction Temperature, TJ
125C
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ±5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
VCC – 0.15
3.3
VCC
V
VCCO_A,
VCCO_B
Power Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
158
mA
ICCA
Analog Supply Current
15
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ±5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
Input High
Current
Input Low
Current
Test Conditions
Minimum
Typical
Maximum
Units
2
VCC + 0.3
V
-0.3
0.8
V
FB_SEL,
SELA1,
SELB0
VCC = VIN = 3.465V
150
µA
SELA0,
SELB1
VCC = VIN = 3.465V
5
µA
FB_SEL,
SELA1,
SELB0
VCC = 3.465V, VIN = 0V
-5
µA
SELA0,
SELB1
VCC = 3.465V, VIN = 0V
-150
µA
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
4
REVISION 1 1/30/15
ICS843242 DATA SHEET
Table 4C. LVPECL DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ±5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
Maximum
Units
VOH
Output High Voltage; NOTE 1
Test Conditions
VCCO_X – 1.4
Minimum
Typical
VCCO_X – 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO_X – 2.0
VCCO_X – 1.7
V
VSWING
Peak-to-Peak Output
Voltage Swing
0.6
1.0
V
NOTE 1: Output termination with 50 to VCCO_A, _B – 2V.
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Maximum
Units
31.25
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
18
pF
Maximum
Units
Mode of Oscillation
Typical
Fundamental
Frequency
26.04166
Load Capacitance
12
NOTE: Characterized using an 18pF parallel resonant crystal.
AC Electrical Characteristics
Table 6. AC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ±5%, VEE = 0V, TA = 0°C to 70°C
Symbol
fOUT
tsk(o)
tjit(Ø)
Parameter
Output
Frequency
Test Conditions
VCO =
625MHz
Output Skew; NOTE 1, 2
RMS Phase Jitter, (Random);
NOTE 3
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Minimum
Typical
Output Divider = ÷ 1
625
MHz
Output Divider = ÷ 2
312.5
MHz
Output Divider = ÷ 4
156.25
MHz
Output Divider = ÷ 5
125
MHz
Outputs @ Same Frequency
45
ps
625MHz, (1.875MHz – 20MHz)
0.4
ps
312.5MHz, (1.875MHz – 20MHz)
0.5
ps
156.25MHz, (1.875MHz – 20MHz)
0.5
ps
125MHz, (1.875MHz – 20MHz)
0.6
ps
20% to 80%
250
650
ps
SELx[1:0] = 00
40
60
%
SELx[1:0] 00
45
55
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential
crosspoint.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plots.
REVISION 1 1/30/15
5
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
843242 DATA SHEET
Typical Phase Noise at 625MHz
625MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.36ps (typical)
Noise Power (dBc/Hz)
Ethernet Filter
Raw Phase Noise Data
Phase Noise Result by adding
an Ethernet filter to raw data
Offset Frequency (Hz)
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
6
REVISION 1 1/30/15
ICS843242 DATA SHEET
Parameter Measurement Information
2V
2V
nQA, nQB
VCC,
VCCO_A,
VCCO_B V
CCA
QA, QB
-1.3V± 0.165V
3.3V LVPECL Output Load AC Test Circuit
Output Rise/Fall Time
nQA, nQB
nQx
QA, QB
Qx
nQy
Qy
Output Skew
REVISION 1 1/30/15
Output Duty Cycle/Pulse Width/Period
7
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
843242 DATA SHEET
Application Information
Recommendations for Unused Input Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVPECL Outputs
All control pins have internal pullups and pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
Figure 5A. 3.3V LVPECL Output Termination
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
R2
84
Figure 5B. 3.3V LVPECL Output Termination
8
REVISION 1 1/30/15
ICS843242 DATA SHEET
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by one
side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 3A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
VCC
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 3B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
XTAL_OUT
R1
100
Rs
Ro
C1
Zo = 50 ohms
XTAL_IN
R2
100
Zo = Ro + Rs
.1uf
LVCMOS Driver
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_IN
.1uf
Zo = 50 ohms
LVPECL Driver
R1
50
R2
50
R3
50
Figure 3B. General Diagram for LVPECL Driver to XTAL
Input Interface
REVISION 1 1/30/15
9
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
843242 DATA SHEET
Schematic Example
Figure 6 (next page) shows an example 843242 application
schematic in which the device is operated at VCC = 3.3V.
ground plane used by the 843242. Then calculate the parasitic
capacity to the ground and determine if it is large enough to preclude
tuning the oscillator. If the coupling is excessive, particularly if the first
layer under the crystal is a ground plane, a layout option is to void the
ground plane and all deeper layers until the next ground plane is
reached. The ground connection of the tuning capacitors should first
be made between the capacitors on the top layer, then a single
ground via is dropped to connect the tuning cap ground to the ground
plane as close to the 843242 as possible as shown in the schematic.
This example focuses on functional connections and is not
configuration specific, particularly in the selection of 31.25MHz
crystals instead of 26.041666MHz. Refer to the pin description and
functional tables in the datasheet to ensure that the logic control
inputs are properly set for the application.
The 12pF parallel resonant Fox FX325BS 31.25MHz crystal is used
with tuning capacitors C1 = 15pF and C2 = 21pF, which are
recommended for frequency accuracy. Depending on the parasitic of
the printed circuit board layout, these values might require a slight
adjustment to optimize the frequency accuracy. Crystals with other
load capacitance specifications can be used. This will require
adjusting C1 and C2. For this device, the crystal tuning capacitors are
required for proper operation. As an alternate choice, a CL= 18pF
HC-49/U crystal is shown with the appropriate tuning capacitors.
These values may also require a slight adjustment depending on the
parasitic capacity of the layout.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 843242 provides separate
power supplies to isolate any high switching noise from coupling into
the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
10 VCCA resistor and the 0.1µF capacitors in each power pin filter
should be placed on the device side. The other components can be
on the opposite side of the PCB. Pull up and pull down resistors to
set configuration pins can all be placed on the PCB side opposite to
the device side to free up device side area if necessary.
Crystal layout is very important to minimize capacitive coupling
between the crystal pads and leads and other metal in the circuit
board. Capacitive coupling to other conductors has two adverse
effects; it reduces the oscillator frequency leaving less tuning margin
and noise coupling from power planes and logic transitions on signal
traces can pull the phase of the crystal resonance, inducing jitter.
Routing I2C under the crystal is a very common layout error, based
on the assumption that it is a low frequency signal and will not affect
the crystal oscillation. In fact, I2C transition times are short enough to
capacitively couple into the crystal if they are routed close enough to
the crystal traces.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
In layout, all capacitive coupling to the crystal from any signal trace is
to be minimized, that is to the XTAL_IN and XTAL_OUT pins, traces
to the crystal pads, the crystal pads and the tuning capacitors. Using
a crystal on the top layer as an example, void all signal and power
layers under the crystal connections between the top layer and the
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
For additional layout recommendations and guidelines, contact
clocks@idt.com.
10
REVISION 1 1/30/15
ICS843242 DATA SHEET
3.3V
F B1
2
R 1 10
VCC
V CCA
1
BLM 18B B 221S N 1
C3
10uF
C4
0. 1uF
10
C6
0. 1uF
3.3V
6
VC C O _A
Set Logic
Input to '1'
F B2
2
V CCO
Logic Control Input Examples
VC C
10uF
VC C A
U1
V CC
C5
0. 1uF
11
C7
C8
0.1uF
1
BLM18B B 221S N 1
C 10
0. 1uF
C9
10uF
Set Logic
Input to '0'
VC C
3
VC C O _B
R U1
1k
RU2
N ot I ns t all
To Logic
Input
pins
R D1
N ot I ns t all
C 11
0.1uF
To Logic
Input
pins
Z o = 50 O hm
7
QA
QA
RD2
1k
Pl ace 0. 1uF byp ass ca ps dire ctly
ad jacent to the corre spondin g VCC,
VC CA or VCCO_x pin.
+
Z o = 50 O hm
8
nQA
nQ A
SE LA1
SE LA0
13
12
SE LB0
SE LB1
5
4
FB _SE L
9
Fo x 325BS crysta l
XTA L_I N
4
1
X1
3
R2
50
SE LA1
SE LA0
SE LB0
SE LB1
R3
50
+3. 3V LV PE C L R ec eiv er
R4
68
FB _SE L
16
XTAL_I N
Zo = 50 Ohm
3 1.25MHz
( 12pF)
XTAL_OU T
-
15
QB
2
QB
+
XTAL_OU T
R5
100
2
C1
1
C2
21 pF
nQB
nQ B
Zo = 50 Ohm
V EE
15 pF
-
14
+3. 3V LV PE C L R ec eiv er
R6
140
XTAL_I N
R7
140
31. 25MHz ( 18pF)
XTAL_OU T
X2
C 12
27 pF
C 13
33 pF
Al ternat e HC-49 /U crys tal
Figure 6. 843242 Schematic Example
REVISION 1 1/30/15
11
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
843242 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 843242.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 843242 is the sum of the core power plus the power dissipated due to the load.
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated due to the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 158mA = 547.47mW
•
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 547.47mW + 60mW = 607.47mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 81.2°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.60747W * 81.2°C/W = 119.3°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 16-Lead TSSOP, Forced Convection
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
0
1
2.5
81.2°C/W
73.9°C/W
70.2°C/W
12
REVISION 1 1/30/15
ICS843242 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 8. LVPECL Driver Circuit and Termination
To calculate power dissipation due to the load, use the following equations which assume a 50 load, and a termination voltage of VCCO – 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
REVISION 1 1/30/15
13
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
843242 DATA SHEET
Reliability Information
Table 8. JA vs. Air Flow Table for a 16-Lead TSSOP
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
81.2°C/W
73.9°C/W
70.2°C/W
Transistor Count
The transistor count for 843242 is: 3767
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
14
REVISION 1 1/30/15
ICS843242 DATA SHEET
Package Outline and Package Dimensions
Package Outline - G Suffix for 16-Lead TSSOP
Table 9. Package Dimensions for 16-Lead TSSOP
All Dimensions in Millimeters
Symbol
aaa C
9
A
SID
0.08 C
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
E
NX L2
E1
4.30
REVISION 1 1/30/15
4.50
0.65 Basic
L
0.45
0.75
0°
8°
aaa
bbb
5.10
6.40 Basic
e
0.10
Reference Document: JEDEC Publication 95, MO-153
NX b2
7
Maximum
16
A
ccc C
8
Minimum
N
C A B
15
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
843242 DATA SHEET
Ordering Information
Table 10. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
843242AGLF
843242AL
16-Lead TSSOP, Lead-Free
Tube
0C to 70C
843242AGLFT
843242AL
16-Lead TSSOP, Lead-Free
Tape & Reel
0C to 70C
NOTE: Parts that are ordered with an “G” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
16
REVISION 1 1/30/15
ICS843242 DATA SHEET
Revision History Sheet
Rev
Table
Page
1
T10
1
16
REVISION 1 1/30/15
Description of Change
Date
Block Diagram - added output clock lables.
Ordering Information table - added note.
Deleted “ICS” prefix from part number throughout the datasheet.
Updated datasheet header/footer.
17
1/30/15
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
Corporate Headquarters
Sales
Tech Support
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
email: clocks@idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected
names, logos and designs, are the property of IDT or their respective third party owners.
Copyright ©2015 Integrated Device Technology, Inc.. All rights reserved.
