843251AG-04LF

FemtoClock® Crystal-to-3.3V LVPECL Clock Generator 843251-04 DATA SHEET General Description Features The 843251-04 is a 10Gb/12Gb Ethernet Clock Generator. The 843251-04 can synthesize 10 Gigabit Ethernet and 12 Gigabit Ethernet with a 25MHz crystal. It can also generate SATA and 10Gb Fibre Channel reference clock frequencies with the appropriate choice of crystals. The 843251-04 has excellent phase jitter performance and is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • • One differential 3.3V LVPECL output • • • • Crystal input frequency range: 19.33MHz – 30MHz • • • Full 3.3V supply mode Crystal oscillator interface designed for 18pF parallel resonant crystal Output frequency range: 145MHz – 187.5MHz VCO range: 580MHz – 750MHz RMS phase jitter @ 156.25MHz, (1.875MHz – 20MHz): 0.39ps (typical) 0°C to 70°C ambient operating temperature Available in lead-free (RoHS 6) package Configuration Table with 25MHz Crystal Inputs Crystal Frequency (MHz)) Feedback Divide VCO Frequency (MHz) N Output Divide Output Frequency (MHz) 25 30 750 4 187.5 12 Gigabit Ethernet 25 25 625 4 156.25 10 Gigabit Ethernet Application Configuration Table with Selectable Crystals Inputs Crystal Frequency (MHz)) Feedback Divide VCO Frequency (MHz) N Output Divide Output Frequency (MHz) 20 30 600 4 150 21.25 30 637.5 4 159.375 24 25 600 4 150 25.5 25 637.5 4 159.375 10 Gigabit Fibre Channel 30 25 750 4 187.5 12 Gigabit Fibre Channel OSC XTAL_OUT Phase Detector VCO 580MHz-750MHz DIV. N ÷4 0 = ÷25 (default) 1 = ÷30 10 Gigabit Fibre Channel SATA nQ Q VCCA VEE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VCC Q nQ FREQ_SEL 843251-04 8 Lead TSSOP 4.40mm x 3.0mm package body FREQ_SEL 843251-04 REVISION B 10/26/15 SATA Pin Assignment Block Diagram XTAL_IN Application 1 ©2015 Integrated Device Technology, Inc. 843251-04 DATA SHEET Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1 VCCA Unused 2 VEE Power Negative supply pin. 3, 4 XTAL_OUT XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 5 FREQ_SEL Input 6, 7 nQ, Q Output Differential output pair. LVPECL interface levels. 8 VCC Power Core supply pin. Analog supply pin. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 k Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC+ 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 129.5C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter VCC Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage VCC – 0.13 3.3 VCC V IEE Power Supply Current 70 mA iCCA Analog Supply Current 13 mA FEMTOCLOCK® CRYSTALl-TO-3.3V LVPECL CLOCK GENERATOR 2 REVISION B 10/26/15 843251-04 DATA SHEET Table 3B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH Input High Current VCC = VIN = 3.465V IIL Input Low Current VCC = 3.465V, VIN = 0V Minimum Typical Maximum Units 2 VCC + 0.3 V -0.3 0.8 V 150 µA -5 µA Table 3C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter Test Conditions VOH Output High Current; NOTE 1 VOL Output Low Current; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum Typical Maximum Units VCC – 1.4 VCC – 0.9 µA VCC – 2.0 VCC – 1.7 µA 0.6 1.0 V Maximum Units 30 MHz Equivalent Series Resistance (ESR) 50  Shunt Capacitance 7 pF NOTE 1: Outputs termination with 50 to VCC – 2V. Table 4. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental Frequency 19.33 AC Electrical Characteristics Table 5. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter, Random; NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 145 Maximum Units 187.5 MHz 156.25MHz, (Integration Range: 1.875MHz – 20MHz) 0.39 ps 187.5MHz, (Integration Range: 1.875MHz – 20MHz) 0.40 ps 20% to 80% 285 415 ps 48 52 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Please refer to Phase Noise Plots. REVISION B 10/26/15 3 FEMTOCLOCK® CRYSTALL-TO-3.3V LVPECL CLOCK GENERATOR 843251-04 DATA SHEET Typical Phase Noise at 187.5MHz ➝ 187.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.40ps (typical) Raw Phase Noise Data ➝ ➝ Noise Power dBc Hz 12Gb Ethernet Filter Phase Noise Result by adding a 12Gb Ethernet filter to raw data Offset Frequency (Hz) FEMTOCLOCK® CRYSTALl-TO-3.3V LVPECL CLOCK GENERATOR 4 REVISION B 10/26/15 843251-04 DATA SHEET ➝ Typical Phase Noise at 156.25MHz 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.39ps (typical) Noise Power dBc Hz 10Gb Ethernet Filter ➝ ➝ Raw Phase Noise Data Phase Noise Result by adding a 10Gb Ethernet filter to raw data Offset Frequency (Hz) REVISION B 10/26/15 5 FEMTOCLOCK® CRYSTALL-TO-3.3V LVPECL CLOCK GENERATOR 843251-04 DATA SHEET Parameter Measurement Information 2V 2V Noise Power Phase Noise Plot VCC VCCA Phase Noise Mask f1 3.3V LVPECL Output Load AC Test Circuit f2 RMS Jitter = Area Under the Masked Phase Noise Plot - -1.3V ± 0.165V Offset Frequency RMS Phase Jitter nQ nQ Q Q Output Duty Cycle/Pulse Width/Period FEMTOCLOCK® CRYSTALl-TO-3.3V LVPECL CLOCK GENERATOR Output Rise/Fall Time 6 REVISION B 10/26/15 843251-04 DATA SHEET Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 843251-04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VCCA pin. 3.3V VCC 0.01µF VCCA 0.01µF 10µF Figure 1. Power Supply Filtering Crystal Input Interface The 843251-04 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 33pF X1 18pF Parallel Crystal XTAL_OUT C2 27pF Figure 2. Crystal Input Interface REVISION B 10/26/15 7 FEMTOCLOCK® CRYSTALL-TO-3.3V LVPECL CLOCK GENERATOR 843251-04 DATA SHEET Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 3A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two VDD ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 3B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. XTAL_OUT R1 100 Ro Zo = 50 ohms C1 Rs XTAL_IN R2 100 Zo = Ro + Rs .1uf LVCMOS Driver Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface XTAL_OUT C2 Zo = 50 ohms XTAL_IN .1uf Zo = 50 ohms LVPECL Driver R1 50 R2 50 R3 50 Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface FEMTOCLOCK® CRYSTALl-TO-3.3V LVPECL CLOCK GENERATOR 8 REVISION B 10/26/15 843251-04 DATA SHEET Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 R3 125 3.3V R4 125 3.3V 3.3V Zo = 50 + _ Input Zo = 50 R1 84 Figure 4A. 3.3V LVPECL Output Termination REVISION B 10/26/15 R2 84 Figure 4B. 3.3V LVPECL Output Termination 9 FEMTOCLOCK® CRYSTALL-TO-3.3V LVPECL CLOCK GENERATOR 843251-04 DATA SHEET Schematic Example board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Two examples of LVPECL termination are shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note. Figure 5 shows an example of 843251-04 application schematic. In this example, the device is operated at VCC = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1 = 33pF and C2 = 27pF are recommended for frequency accuracy. For different VCC R1 VCC VC C VCC A 10 VC C C4 0. 1u C5 1 0u U1 1 2 3 4 X1 C3 0 .1 uF VCC A VEE XTAL_ OU T XTAL_ IN VCC Q nQ FREQ _SEL 8 7 6 5 R2 1 33 R3 13 3 Zo = 5 0 Oh m + FR EQ_ SEL 25 MH z F p 8 1 C2 27 pF 3 .3V Zo = 5 0 Oh m - ICS8 43 25 1I -0 4 C1 3 3p F R4 8 2. 5 R5 82 .5 V C C=3 . 3V Logic Control Input Ex amples Set Logic Input to '1' VCC Set Logic Input to '0 ' VCC Zo = 5 0 Oh m RU 1 1k RU 2 No t Ins ta ll To Log ic Inp ut pin s RD 1 No t In st all + Zo = 5 0 Oh m To Log ic Inpu t pins - RD 2 1k R6 50 Optional Y-Termination R7 50 R8 50   Figure 5. 843251-04 Schematic Example FEMTOCLOCK® CRYSTALl-TO-3.3V LVPECL CLOCK GENERATOR 10 REVISION B 10/26/15 843251-04 DATA SHEET Power Considerations This section provides information on power dissipation and junction temperature for the 843251-04. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 843251-04 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 70mA = 242.55mW • Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.3V, with all outputs switching) = 242.55mW + 30mW = 272.55mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 129.5°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.273W * 129.5°C/W = 105.4°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards REVISION B 10/26/15 0 1 2.5 129.5°C/W 125.5°C/W 123.5°C/W 11 FEMTOCLOCK® CRYSTALL-TO-3.3V LVPECL CLOCK GENERATOR 843251-04 DATA SHEET 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 6. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCC – 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (VCC_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = [(2V – 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW FEMTOCLOCK® CRYSTALl-TO-3.3V LVPECL CLOCK GENERATOR 12 REVISION B 10/26/15 843251-04 DATA SHEET Reliability Information Table 7. JA vs. Air Flow Table for a 8 Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 129.5°C/W 125.5°C/W 123.5°C/W Transistor Count The transistor count for 843251-04 is: 1891 Package Outline and Package Dimensions Package Outline - G Suffix for 8 Lead TSSOP Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75  0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 REVISION B 10/26/15 13 FEMTOCLOCK® CRYSTALL-TO-3.3V LVPECL CLOCK GENERATOR 843251-04 DATA SHEET Ordering Information Table 9. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 843251AG-04LF 1A04L 8 Lead TSSOP, Lead-Free Tube 0C to 70C 843251AG-04LFT 1A04L 8 Lead TSSOP, Lead-Free Tape & Reel 0C to 70C FEMTOCLOCK® CRYSTALl-TO-3.3V LVPECL CLOCK GENERATOR 14 REVISION B 10/26/15 843251-04 DATA SHEET Revision History Sheet Rev Table B T10 REVISION B 10/26/15 Page 11 7 8 9 10 14 Description of Change Date Updated header/footer throughout the datasheet. Deleted IDT prefix from part number. Deleted HiperClocks reference throughout the datasheet. Application Information, updated: Overdriving the XTAL Interface, Termination for 3.3V LVPECL Outputs Figure 5, Schematic Example Ordering Information Table - deleted: leaded part rows, Tape & Reel Count, and table note. 15 10/26/15 FEMTOCLOCK® CRYSTALL-TO-3.3V LVPECL CLOCK GENERATOR Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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