PRELIMINARY
ICS843252-04
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS843252-04 is a 10Gb/12Gb Ethernet Clock
ICS
Generator and a member of the HiPerClocks TM
HiPerClockS™
family of high performance devices from IDT. The
ICS843252-04 can synthesize 10 Gigabit Ethernet
and 12 Gigabit Ethernet with a 25MHz crystal. It
can also generate SATA and 10Gb Fibre Channel reference
clock frequencies with the appropriate choice of crystals. The
ICS843252-04 has excellent phase jitter performance and is
packaged in a small 16-pin TSSOP, making it ideal for use in
systems with limited board space.
• Two differential 3.3V LVPECL output
• Crystal oscillator interface designed for
18pF parallel resonant crystals
• Crystal input frequency range: 19.33MHz - 30MHz
• Output frequency range: 145MHz - 187.5MHz
• VCO frequency range: 580MHz - 750MHz
• RMS phase jitter at 156.25MHz (1.875MHz - 20MHz):
0.39ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS5) and lead-free (RoHS 6)
packages
CONFIGURATION TABLE WITH 25MHZ CRYSTAL
Crystal Frequency
(MHz)
25
Feedback
Divide
30
25
25
Inputs
VCO Frequency
(MHz)
750
N Output Divide
Output Frequency
(MHz)
Application
4
187.5
12 Gigabit Ethernet
4
156.25
10 Gigabit Ethernet
625
CONFIGURATION TABLE WITH SELECTABLE CRYSTALS
Crystal Frequency
(MHz)
20
Inputs
Feedback VCO Frequency
Divide
(MHz)
30
600
21.25
30
N Output Divide
Output Frequency
(MHz)
4
150
637.5
4
159.375
24
25
600
4
150
25.5
25
637.5
4
159.375
30
25
750
4
187.5
BLOCK DIAGRAM
OE
Pulldown
REF_CLK
Pulldown
D
Q
LE
1
XTAL_IN
OSC
0
1
DIV. N
÷4
VCO
Phase
Detector
580MHz-750MHz
Q1
nQ1
SATA
10 Gigabit Fibre Channel
12 Gigabit Ethernet
nQ1
Q1
VCCO
OE
nPLL_SEL
VCCO
Q0
nQ0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XTAL_IN
XTAL_OUT
V EE
REF_CLK
CLK_SEL
VCC
VCCA
FREQ_SEL
ICS843252-04
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
Pulldown
0 = ÷25 (default)
1 = ÷30
FREQ_SEL
Q0
nQ0
0
XTAL_OUT
CLK_SEL
SATA
10 Gigabit Fibre Channel
PIN ASSIGNMENT
Pullup
nPLL_SEL
Application
Pulldown
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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843252AG-04 REV. A JANUARY 9, 2009
ICS843252-04
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 2
nQ1, Q1
Output
Type
Description
3, 6
VCCO
Power
4
OE
Input
5
nPLL_SEL
Input
7, 8
Q0, nQ0
Output
9
FREQ_SEL
Input
10
VCCA
Power
Analog supply pin.
11
VCC
Power
Core supply pin.
12
CLK_SEL
Input
13
REF_CLK
Input
Differential clock outputs. LVPECL interface levels.
Output supply pins.
Output enable. When HIGH, clock outputs follow clock input.
When LOW, Qx outputs are forced low, nQx outputs are forced high.
Pullup
LVCMOS/LVTTL interface levels.
Selects between the PLL and reference clock as input to the divider.
Pulldown When Low, selects PLL. When High, selects reference clock.
LVCMOS/LVTTL interface levels.
Differential clock outputs. LVPECL interface levels.
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Clock select input. When Low, selects crystal inputs. When High,
selects REF_CLK. LVCMOS/LVTTL interface levels.
Pulldown Reference clock input. LVCMOS/LVTTL interface levels.
Pulldown
14
VEE
Power
Negative supply pin.
XTAL_OUT,
Crystal oscillator interface. XTAL_IN is the input,
15, 16
Input
XTAL_OUT is the output.
XTAL_IN
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characterristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
IDT ™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
Test Conditions
Minimum
2
Typical
Maximum
Units
843252AG-04 REV. A JANUARY 9, 2009
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, θJA 92.4°C/W (0 mps)
-65°C to 150°C
Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
Test Conditions
3.135
3.3
3.465
V
3.135
3.3
3.465
VCCA
Analog Supply Voltage
ICC
Power Supply Current
60
mA
ICCA
Analog Supply Current
11
mA
IEE
Power Supply Current
80
mA
V
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
Input High Current
Input Low Current
Test Conditions
REF_CLK,
C LK _S E L,
FREQ_SEL,
nPLL_SEL
OE
REF_CLK,
C LK _S E L,
FREQ_SEL,
nPLL_SEL
OE
Minimum
Typical
Maximum
Units
2
VCC + 0.3
V
-0.3
0.8
V
VCC = VIN = 3.465V
150
µA
VCC = VIN = 3.465V
5
µA
VCC = 3.465V, VIN = 0V
-5
µA
VCC = 3.465V, VIN = 0V
-150
µA
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
Typical
Maximum
Units
VCCO - 1.4
VCCO - 0.9
V
VCCO - 2.0
VCCO - 1.7
V
0.6
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
IDT ™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Maximum
Units
30
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
Mode of Oscillation
Typical
Fundamental
Frequency
19.33
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fOUT
Output Frequency
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 1
tsk(o)
Output Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
Test Conditions
Minimum
Typical
145
156.25MHz @ Integration Range:
1.875MHz - 20MHz
159.375MHz @ Integration Range:
1.875MHz - 20MHz
187.5MHz @ Integration Range:
1.875MHz - 20MHz
Maximum
Units
187.5
MHz
0.39
ps
0.38
ps
0.38
ps
ps
20% to 80%
400
ps
odc
Output Duty Cycle
50
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Please refer to the Phase Noise Plots following this section.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VCCO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
IDT ™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
TYPICAL PHASE NOISE
PRELIMINARY
AT
156.25MHZ
➤
0
-10
-20
Gb Ethernet Filter
-30
-40
156.25MHz
RMS Phase Noise Jitter
1.875MHz to 20MHz = 0.39ps (typical)
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
➤
NOISE POWER dBc
Hz
-50
-120
-130
-140
-150
➤
-160
-170
-180
Phase Noise Result by adding a
Gb Ethernet Filter Filter to raw data
-190
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
IDT ™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V
Phase Noise Plot
Qx
SCOPE
Noise Power
VCC,
VCCA,
VCCO
LVPECL
Phase Noise Mask
nQx
VEE
f1
-1.3V ± 0.165V
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQx
nQ0, nQ1
80%
Qx
80%
VSW I N G
nQy
Q0, Q1
20%
20%
Qy
tR
tF
tsk(o)
OUTPUT RISE/FALL TIME
OUTPUT SKEW
nQ0, nQ1
Q0, Q1
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
IDT ™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS843252-04
provides separate power supplies to isolate any high switching
noise from the outputs to the inter nal PLL. V CC , V CCA,
and VCCO should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be
used for each pin. Figure 1 illustrates this for a generic VCC pin
and also shows that VCCA requires that an additional10Ω resistor
along with a 10µF bypass capacitor be connected to the VCCA pin.
3.3V
VCC
.01μF
V CCA
.01μF
10Ω
10μF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating. Though
not required, but for additional protection, a 1kΩ resistor can be
tied from XTAL_IN to ground.
LVPECL OUTPUTS
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
REF_CLK INPUT
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT ™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
CRYSTAL INPUT INTERFACE
The ICS843252-04 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
XTAL_OUT
C1
22p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
FIGURE 2. CRYSTAL INPUT INTERFACE
LVCMOS TO XTAL INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs)
equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half.
This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50Ω
applications, R1 and R2 can be 100Ω. This can also be
accomplished by removing R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
VDD
VDD
R1
Ro
.1uf
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
IDT ™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which
are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
FOUT
FIN
125Ω
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
1
RTT =
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
IDT ™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
84Ω
FIGURE 4B. LVPECL OUTPUT TERMINATION
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843252-04.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843252-04 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 80mA = 277.2mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 277.2mW + 60mW = 337.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 92.4°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.337W * 92.4°C/W = 101.1°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 16 LEAD TSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
IDT ™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
0
1
2.5
92.4°C/W
88.0°C/W
85.9°C/W
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
– 2V.
CCO
•
For logic high, VOUT = V
OH_MAX
(V
CCO_MAX
•
–V
– 0.9V
) = 0.9V
OL_MAX
CCO_MAX
CCO_MAX
OH_MAX
For logic low, VOUT = V
(V
=V
–V
OL_MAX
=V
CCO_MAX
– 1.7V
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
– 2V))/R ] * (V
CCO_MAX
L
–V
OH_MAX
) = [(2V – (V
CCO_MAX
–V
OH_MAX
))/R ] * (V
CCO_MAX
L
–V
OH_MAX
)=
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
– 2V))/R ] * (V
L
CCO_MAX
–V
OL_MAX
) = [(2V – (V
CCO_MAX
–V
OL_MAX
))/R ] * (V
L
CCO_MAX
–V
OL_MAX
)=
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT ™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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PRELIMINARY
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
92.4°C/W
88.0°C/W
85.9°C/W
TRANSISTOR COUNT
The transistor count for ICS843252-04 is: 2210
IDT ™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
N
Maximum
16
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
E
E1
5.10
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
α
0°
8°
aaa
--
0.10
0.75
Reference Document: JEDEC Publication 95, MO-153
IDT ™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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PRELIMINARY
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
843252AG-04
43252A04
16 Lead TSSOP
tube
0°C to 70°C
843252AG-04T
43252A04
16 Lead TSSOP
2500 tape & reel
0°C to 70°C
843252AG-04LF
3252A04L
16 Lead "Lead-Free" TSSOP
tube
0°C to 70°C
843252AG-04LFT
3252A04L
16 Lead "Lead-Free" TSSOP
2500 tape & reel
0°C to 70°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents
or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications
such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications
without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT ™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
Corporate Headquarters
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
www.IDT.com/go/contact IDT
netcom@idt.com
+480-763-2056
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are
trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and
marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
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