ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
General Description
Features
The ICS84329B is a general purpose, single output
high frequency synthesizer and a member of the
HiPerClockS™
HiPerClockS™family of High Performance Clock
Solutions from IDT. The VCO operates at a
frequency range of 250MHz to 700MHz. The VCO
frequency is programmed in steps equal to the value of the crystal
frequency divided by 16. The VCO and output frequency can be
programmed using the serial or parallel interfaces to the
configuration logic. The output can be configured to divide the
VCO frequency by 1, 2, 4, and 8. Output frequency steps as small
as 125kHz to 1MHz can be achieved using a 16MHz crystal
depending on the output dividers.
•
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•
•
•
•
Fully integrated PLL, no external loop filter requirements
•
•
•
•
•
•
Serial 3 wire interface
ICS
One differential 3.3V LVPECL output
Parallel resonant crystal oscillator interface
Output frequency range: 31.25MHz – 700MHz
VCO range: 250MHz – 700MHz
Parallel interface for programming counter and output dividers
during power-up
RMS period jitter: 5.5ps (maximum)
Cycle-to-cycle jitter: 35ps (maximum)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
VEE
TEST
VEE
VCC
FOUT
nFOUT
VCC
Pin Assignments
25 24 23 22 21 20 19
S_CLOCK
26
S_DATA
27
S_LOAD
28
M6
M5
12
M4
M3
VEE
M2
10 11
TEST
9
VCC
VCC
8
32 31 30 29 28 27 26 25
N1
S_LOAD
3
22
N0
VCCA
4
21
M8
VCCA
5
20
M7
nc
6
19
M6
nc
7
18
M5
XTAL_IN
8
17
M4
M0:M8
N0:N1
1
10 11 12 13 14 15 16
nc
9
M3
TEST
ICS84329B
32 Lead LQFP
7mm x 7mm x 1.4mm
package body
Y Package
Top View
M2
CONFIGURATION
INTERFACE
LOGIC
23
M0
0
nc
2
M1
FOUT
nFOUT
24
S_DATA
nP_LOAD
1
VCO
÷1
÷2
÷4
÷8
1
OE
PHASE DETECTOR
S_CLOCK
XTAL_OUT
PLL
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
7
M0
OSC
XTAL_OUT
FOUT
XTAL_OUT
6
M1
4
VCC
XTAL_IN
VEE
3
XTAL_IN
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M8
13
2
nc
5
÷M
N0
16
14
nc
÷ 16
17
M7
OE
OE
N1
Top View
nP_LOAD
Block Diagram
18
11.5mm x 11.5mm x 3.9mm
15
1
package body
nFOUT
VCCA
ICS84329B
28 Lead PLCC
V Package
ICS84329BV REV. B OCTOBER 23, 2008
ICS84329B700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Functional Description
NOTE: The functional description that follows describes operation
using a 16MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 6, NOTE 1.
passed directly to the M divider and N output divider. On the
LOW-to-HIGH transition of the nP_LOAD input, the data is latched
and the M divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. The TEST output is Mode
000 (shift register out) when operating in the parallel input mode.
The relationship between the VCO frequency, the crystal
frequency and the M divider is defined as follows:
fVCO = fXTAL x M
16
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock are defined as 250 ≤
M ≤ 511. The frequency out is defined as follows:
fout = fVCO = fXTAL x M
N
16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider when S_LOAD transitions from
LOW-to-HIGH. The M divide and N output divide values are
latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is
held HIGH, data at the S_DATA input is passed directly to the M
divider on each rising edge of S_CLOCK. The serial mode can be
used to program the M and N bits and test bits T2:T0. The internal
registers T2:T0 determine the state of the TEST output as follows:
The ICS84329B features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A
series-resonant, fundamental crystal is used as the input to the
on-chip oscillator. The output of the oscillator is divided by 16 prior
to the phase detector. With a 16MHz crystal, this provides a 1MHz
reference frequency. The VCO of the PLL operates over a range of
250MHz to 700MHz. The output of the M divider is also applied to
the phase detector.
The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the
LVPECL output buffers. The divider provides a 50% output duty
cycle.
The programmable features of the ICS84329B support two input
modes to program the M divider and N output divider. The two input
operational modes are parallel and serial. Figure 1 shows the
timing diagram for each mode. In parallel mode the nP_LOAD input
is LOW. The data on inputs M0 through M8 and N0 through N1 is
T2
0
0
0
0
1
1
1
1
T1
0
0
1
1
0
0
1
1
T0
0
1
0
1
0
1
0
1
TEST Output
Shift Register Out
HIGH
PLL Reference XTAL ÷16
(VCO ÷ M) (non 50% Duty Cycle M Divider)
fOUT, LVCMOS Output Frequency < 200MHz
LOW
S_CLOCK ÷ M (non 50% Duty Cycle M Divider)
fOUT ÷ 4
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
S_CLOCK ÷ N Divider
fOUT
SERIAL LOADING
S_CLOCK
T2
S_DATA
t
S_LOAD
S
t
T1
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
H
t
nP_LOAD
S
PARALLEL LOADING
M0:M8, N0:N1
M, N
nP_LOAD
t
S
t
H
nP_LOAD
Time
Figure 1. Parallel & Serial Load Operations
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
2
ICS84329BV REV. B OCTOBER 23, 2008
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Name
Type
Description
M0, M1, M2, M3, M4,
M5, M6, M7, M8
Input
Pullup
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.
LVCMOS/LVTTL interface levels.
N0, N1
Input
Pullup
Determines N output divider value as defined in Table 3C, Function Table.
LVCMOS/LVTTL interface levels.
VEE
Power
Negative supply pins.
TEST
Output
Test output which is used in the serial mode of operation.
Single-ended LVPECL interface levels.
VCC
Power
Core supply pins.
FOUT, nFOUT
Output
Differential output pair for the synthesizer. LVPECL interface levels.
OE
Input
nc
Unused
S_CLOCK
Input
Pulldown
Clocks the serial data present at S_DATA input into the shift register on the rising edge
of S_CLOCK. LVCMOS/LVTTL interface levels.
S_DATA
Input
Pulldown
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS/LVTTL interface levels.
S_LOAD
Input
Pulldown
Controls transition of data from shift register into the M divider.
LVCMOS/LVTTL interface levels.
VCCA
Power
Analog supply pin.
XTAL_IN
XTAL_OUT
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
nP_LOAD
Input
Pullup
Output enable. When logic HIGH, the outputs are enabled (default). When logic LOW,
the outputs are disabled and drive differential low: FOUT = LOW, nFOUT = HIGH.
LVCMOS / LVTTL interface levels.
No connect.
Pullup
Parallel load input. Determines when data present at M8:M0 is loaded into M divider,
and when data present at N1:N0 sets the N output divider value. LVCMOS/LVTTL
interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
3
ICS84329BV REV. B OCTOBER 23, 2008
ICS84329B700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs
nP_LOAD
M
N
S_LOAD
S_CLOCK
S_DATA
X
X
X
X
X
X
Conditions
Reset. M and N bits are all set HIGH.
L
Data
Data
X
X
X
Data on M and N inputs passed directly to the M divider and
N output divider. TEST mode 000.
↑
Data
Data
L
X
X
Data is latched into input registers and remains loaded until
next LOW transition or until a serial event occurs.
H
X
X
L
↑
Data
Serial input mode. Shift register is loaded with data on S_DATA
on each rising edge of S_CLOCK.
H
X
X
↑
L
Data
Contents of the shift register are passed to the M divider and
N output divider.
H
X
X
↓
L
Data
M divider and N output divider values are latched.
H
X
X
L
X
X
Parallel or serial input do not affect shift registers.
NOTE: L = LOW
H = HIGH
X = Don’t care
↑ = Rising edge transition
↓ = Falling edge transition
Table 3B. Programmable VCO Frequency Function Table
VCO Frequency
(MHz)
256
128
64
32
16
8
4
2
1
M Divide
M8
M7
M6
M5
M4
M3
M2
M1
M0
250
250
0
1
1
1
1
1
0
1
0
251
251
0
1
1
1
1
1
0
1
1
252
252
0
1
1
1
1
1
1
0
0
253
253
0
1
1
1
1
1
1
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
509
509
1
1
1
1
1
1
1
0
1
510
510
1
1
1
1
1
1
1
1
0
511
511
1
1
1
1
1
1
1
1
1
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.
Table 3C. Programmable Output DividerFunction Table
Inputs
Output Frequency (MHz)
N1
N0
N Divider Value
Minimum
Maximum
0
0
1
250
700
0
1
2
125
350
1
0
4
62.5
175
1
1
8
31.25
87.5
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
4
ICS84329BV REV. B OCTOBER 23, 2008
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC+ 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
28 Lead PLCC
32 Lead LQFP
37.8°C/W (0 lfpm)
47.9°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCA = 3.3V±5%, TA = 0°C to 70°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
Test Conditions
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
ICC
Power Supply Current
125
mA
ICCA
Analog Supply Current
15
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCA = 3.3V±5%, TA = 0°C to 70°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
Input
High Current
Input
Low Current
Test Conditions
Minimum
Maximum
Units
2
Typical
VCC + 0.3
V
-0.3
0.8
V
S_CLOCK,
S_DATA, S_LOAD
VCC = VIN = 3.465V
150
µA
nP_LOAD, OE
M0:M8, N0, N1
VCC = VIN = 3.465V
5
µA
S_CLOCK,
S_DATA, S_LOAD
VCC = 3.465V, VIN = 0V
-5
µA
nP_LOAD, OE
M0:M8, N0, N1
VCC = 3.465V, VIN = 0V
-150
µA
2.6
V
VOH
Output High Voltage
TEST; NOTE 1
VOL
Output Low Voltage
TEST; NOTE 1
0.5
V
NOTE 1: Outputs terminated with 50Ω to VCC/2. See Parameter Measurement Information section. Load Test Circuit diagrams.
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
5
ICS84329BV REV. B OCTOBER 23, 2008
ICS84329B700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 4C. LVPECL DC Characteristics, VCC = VCCA = 3.3V±5%, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Current; NOTE 1
VCC – 1.4
VCC – 0.9
µA
VOL
Output Low Current; NOTE 1
VCC – 2.0
VCC – 1.7
µA
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
Maximum
Units
25
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
Maximum
Units
NOTE 1: Outputs terminated with 50Ω to VCC – 2V.
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Fundamental
Frequency
10
Table 6. Input Frequency Characteristics, VCC = VCCA = 3.3V±5%, TA = 0°C to 70°C
Symbol
Parameter
fIN
Input Frequency
Test Conditions
XTAL; NOTE 1
Minimum
Typical
10
S_CLOCK
25
MHz
50
MHz
NOTE 1: For the crystal frequency range, the M value must be set to achieve the minimum or maximum VCO frequency range of 250MHz
or 700MHz. Using the minimum input frequency of 10MHz, valid values of M are 400 ≤ M ≤ 511. Using the maximum input frequency of
25MHz, valid values of M are 160 ≤ M ≤ 448.
AC Electrical Characteristics
Table 7. AC Characteristics, VCC = VCCA = 3.3V±5%, TA = 0°C to 70°C
Parameter Symbol
fOUT
Output Frequency
tjit(per)
Period Jitter, RMS; NOTE 1, 2
Test Conditions
Minimum
Typical
Maximum
Units
700
MHz
fOUT ≥ 65MHz
5.5
ps
fOUT < 65MHz
12
ps
fOUT ≥ 50MHz
35
ps
fOUT < 50MHz
50
ps
800
ps
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1, 2
tR / tF
Output Rise/Fall Time
tS
Setup Time
5
ns
tH
Hold Time
5
ns
odc
Output Duty Cycle
45
tLOCK
PLL Lock Time
20% to 80%
300
50
55
%
10
ms
See Parameter Measurement Information section.
Characterized using 16MHz XTAL.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: See Applications Section.
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
6
ICS84329BV REV. B OCTOBER 23, 2008
ICS84329B700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Parameter Measurement Information
2V
VOH
VREF
VCC,
VCCA
Qx
SCOPE
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
LVPECL
nQx
Histogram
Reference Point
Mean Period
(Trigger Edge)
VEE
(First edge after trigger)
-1.3V±0.165V
3.3/3.3V LVPECL Output Load AC Test Circuit
Period Jitter
nFOUT
nFOUT
FOUT
FOUT
➤
tcycle n
➤
t PW
tcycle n+1
➤
t
➤
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
odc =
PERIOD
t PW
x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
Cycle-to-Cycle Jitter
S_DATA
80%
80%
SL_CLOCK
VSW I N G
Clock
Outputs
20%
20%
tR
t SET-UP
t HOLD
S_LOAD
tF
t SET-UP
M0:M8
N0:N1
Output Rise/Fall Time
t HOLD
nP_LOAD
t SET-UP
Setup and Hold Time
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
7
ICS84329BV REV. B OCTOBER 23, 2008
ICS84329B700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The ICS84329B
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC and VCCA should
be individually connected to the power supply plane through vias,
and 0.01µF bypass capacitors should be used for each pin. Figure
2 illustrates how a 10Ω resistor along with a 10µF and a 0.01µF
bypass capacitor should be connected to each VCCA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
3.3V
VCC
.01µF
10Ω
.01µF
10µF
VCCA
Figure 2. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
TEST Output
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
The unused TEST output can be left floating. There should be no
trace attached.
LVPECL Output
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
8
ICS84329BV REV. B OCTOBER 23, 2008
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Crystal Input Interface
The ICS84329B has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 3 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
Figure 3. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 4. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
VCC
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
VCC
R1
Ro
Rs
0.1µf
50Ω
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 4. General Diagram for LVCMOS Driver to XTAL Input Interface
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
9
ICS84329BV REV. B OCTOBER 23, 2008
ICS84329B700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
14
12
Time (pS)
10
8
6
4
2
0
25
50
75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525
Output Frequency (MHz)
Figure 5A. RMS Jitter vs. fOUT (using a 16MHz crystal)
60
50
Time (pS)
40
30
20
10
0
25
50
75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525
Output Frequency (MHz)
Figure 5B. Cycle-to-Cycle Jitter vs. fOUT (using a 16MHz crystal)
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
10
ICS84329BV REV. B OCTOBER 23, 2008
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 6A and 6B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Zo = 50Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
125Ω
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
Zo = 50Ω
VCC - 2V
RTT
84Ω
Figure 6A. 3.3V LVPECL Output Termination
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
84Ω
Figure 6B. 3.3V LVPECL Output Termination
11
ICS84329BV REV. B OCTOBER 23, 2008
ICS84329B700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Layout Guideline
layout in the actual system will depend on the selected component
types, the density of the components, the density of the traces, and
the stack up of the P.C. board.
M3
M2
M1
M0
nPLOAD
OE
The schematic of the ICS84329B layout example used in this
layout guideline is shown in Figure 7A. The ICS84329B
recommended PCB board layout for this example is shown in
Figure 7B. This layout example is used as a general guideline. The
11
10
9
8
7
6
5
M4
M5
M6
M7
M8
N2
N1
M [8:0]= 110010000 (400)
N[1:0] =01 (Divide by 2)
12
13
14
15
16
17
18
M4
M5
M6
M7
M8
N0
N1
84329BV
RD0
1K
RD1
1K
RD7
SP
RD8
SP
RU10
1K
RD9
1K
RU11
SP
RD10
SP
RU12
1K
C2
0.1u
OE
nPLoad
N0
RU9
SP
N1
RU8
1K
M8
RU7
1K
M7
M1
M0
RU1
SP
VCC
VCC
RU0
SP
XTALIN
nc
nc
VCCA
S_LOAD
S_DATA
S_CLOCK
19
20
21
22
23
24
25
U1
M3
M2
M1
M0
nP_LOAD
OE
XTALOUT
SP = Space (i .e. not i ntstal l ed)
RD6
1K
4
3
2
1
28
27
26
C4
22p
R7
10
VCCA
C11
0.01u
C16
10u
C1
0.1uF
Zo = 50 Ohm
Fout = 200 M Hz
Zo = 50 Ohm
R2
50
RD12
SP
VCC
X1
VEE
TEST
VCC
VEE
nFOUT
FOUT
VCC
VCC=3.3V
C3
22p
16MHz,18pF
R1
50
R3
50
Figure 7A. ICS84329B Schematic of Recommended Layout for 28 Lead PLCC
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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The following component footprints are used in this layout
example:
• The differential 50Ω output traces should have the same
length.
All the resistors and capacitors are size 0603.
Power and Grounding
• Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
Place the decoupling capacitors C1, C2 and C3, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This can
reduce unwanted inductance between the decoupling capacitor
and the power pin caused by the via.
• Keep the clock traces on the same layer. Whenever
possible, avoid placing vias on the clock traces. Placement of
vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace widths
between the differential clock trace and the other signal trace.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power and
ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed as
close to the VCCA pin as possible.
• Make sure no other signal traces are routed between the
clock trace pair.
Clock Traces and Termination
• The matching termination resistors should be located as
close to the receiver input pins as possible.
Poor signal integrity can degrade the system performance or cause
system failure. In synchronous high-speed digital systems, the
clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
Crystal
The crystal X1 should be located as close as possible to the pins
4 (XTAL_IN) and 5 (XTAL_OUT). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
X1
C3
C4
U1
GND
VCC
PIN 2
C11
PIN 1
C16
VCCA
VCCA
R7
VIA
Signals
Traces
C1
C2
50 Ohm
Traces
Figure 7B. ICS84329B PCB Board Layout for ICS84329B 28 Lead PLCC
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS84329B.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS84329B is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485mW
Total Power_MAX (3.3V, with all outputs switching) = 485mW + 30mW = 515mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate
air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W per Table 8A below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.515W * 31.1°C/W = 86°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 8A. Thermal Resistance θJA for 28 Lead PLCC, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
37.8°C/W
31.1°C/W
28.3°C/W
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
Table 8B. Thermal Resistance θJA for 32 Lead LQFP, Forced Convection
θJA by Velocity
Linear Feet per Minute
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCC
Q1
VOUT
RL
50Ω
VCC - 2V
Figure 8. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage
of VCC – 2V.
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V
(VCC_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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Reliability Information
Table 9A. θJA vs. Air Flow Table for a 28 Lead PLCC
θJA vs. Air Flow
Linear Feet per Minute
0
200
500
37.8°C/W
31.1°C/W
28.3°C/W
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
Table 9B. θJA vs. Air Flow Table for a 32 Lead LQFP
θJA vs. Air Flow
Linear Feet per Minute
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS84329B is: 4408
Pin compatible with the MC12429
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Package Outline and Package Dimension
Package Outline - V Suffix for 28 Lead PLCC
Table 10A. Package Dimensions for 28 Lead PLCC
JEDEC: 300 MIL
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
28
A
4.19
4.57
A1
2.29
3.05
A2
1.57
2.11
b
0.33
0.53
c
0.19
0.32
D/E
12.32
12.57
D1/E1
11.43
11.58
D2/E2
4.85
5.56
Reference Document: JEDEC Publication 95, MS-018
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Package Outline - Y Suffix for 32 Lead LQFP
Reference Document: JEDEC Publication 95, MS-018
Table 10B. Package Dimensions for 32 Lead LQFP
JEDEC Variation: BBC - HD
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
1.60
A1
0.05
0.10
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
0.20
D&E
9.00 Basic
D1 & E1
7.00 Basic
D2 & E2
5.60 Ref.
e
0.80 Basic
L
0.45
0.60
0.75
θ
0°
7°
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
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Ordering Information
Table 11. Ordering Information
Part/Order Number
84329BV
84329BVT
84329BVLF
84329BVLFT
84329BY
84329BYT
84329BYLF
84329BYLFT
Marking
ICS84329BV
ICS84329BV
ICS84329BVLF
ICS84329BVLF
ICS84329BY
ICS84329BY
ICS84329BYLF
ICS84329BYLF
Package
28 Lead PLCC
28 Lead PLCC
“Lead-Free” 28 Lead PLCC
“Lead-Free” 28 Lead PLCC
32 Lead LQFP
32 Lead LQFP
“Lead-Free” 32 Lead LQFP
“Lead-Free” 32 Lead LQFP
Shipping Packaging
Tube
500 Tape & Reel
Tube
1000 Tape & Reel
Tube
1000 Tape & Reel
Tube
1000 Tape & Reel
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev
Table
A
Description of Change
Date
1
Features Section - added ""Parallel resonant"" to crystal bullet.
12/15/04
1
6/10/05
T5
T11
2
6
17
Features Section - corrected Output frequency range from 25MHz to 31.25MHz.
Added Lead-Free bullet.
Updated Parallel & Serial Load Operations.
Crystal Table - added Drive Level.
Ordering Information Table - added Lead-Free part numbers and note.
Power Supply Filtering Techniques - added ferrite bead sentence.
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added Lead-Free marking.
1/18/06
T11
8
8
18
9
Added LVCMOS to XTAL Interface section.
Updated format throughout the datasheet.
12/21/07
B
B
B
Page
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