700MHz, Low Jitter, Crystal-to-3.3V
Differential LVPECL Frequency Synthesizer
84330-02
Data Sheet
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
GENERAL DESCRIPTION
FEATURES
The 84330-02 is a general purpose, single
output high frequency synthesizer. The VCO operates
at a frequency range of 250MHz to 700MHz. The VCO
and output frequency can be programmed using the
serial or parallel interfaces to the configuration logic.
The output can be configured to divide the VCO
frequency by 1, 2, 4, and8. Output frequency steps
from 250kHz to 2MHz canbe achiev-ed using a 16MHz
crystal depending on the output divider setting.
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BLOCK DIAGRAM
PIN ASSIGNMENT
©2016 Integrated Device Technology, Inc
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1
Fully integrated PLL, no external loop filter requirements
1 differential 3.3V LVPECL output
Crystal oscillator interface: 10MHz to 25MHz
Output frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
Parallel or serial interface for programming M and N dividers during power-up
RMS Period jitter: 5ps (maximum)
Cycle-to-cycle jitter: 40ps (maximum)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Lead-Free package fully RoHS compliant
Industrial temperature information available upon request
For functional replacement part use 8T49N242
Revision B May 26, 2016
84330-02 Data Sheet
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input
Frequency Characteristics, Table 6, NOTE 1.
the LOW-to-HIGH transition of the nP_LOAD input, the data is
latched and the M divider remains loaded until the next LOW
transition on nP_LOAD or until a serial event occurs. The TEST
output is Mode 000 (shift register out) when operating in the parallel input mode. The relationship between the VCO frequency,
the crystal frequency and the M divider is defined as follows:
fxtal x
fVCO =
2M
16
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock are defined as 125 ≤ M ≤ 350. The frequency out is defined as follows:
fout = fVCO = fxtal x 2M
N
N
16
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider when S_LOAD transitions
from LOW-to-HIGH. The M divide and N output divide values are
latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD
is held HIGH, data at the S_DATA input is passed directly to the
M divider on each rising edge of S_CLOCK. The serial mode
can be used to program the M and N bits and test bits T2:T0.
The internal registers T2:T0 determine the state of the TEST
output as follows:
The 84330-02 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
A quartz crystal is used as the input to the on-chip oscillator.
The output of the oscillator is divided by 16 prior to the phase
detector. With a 16MHz crystal this provides a 1MHz reference
frequency. The VCO of the PLL operates over a range of 250MHz
to 700MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output
of the VCO is scaled by a divider prior to being sent to each of
the LVPECL output buffers. The divider provides a 50% output
duty cycle.
The programmable features of the 84330-02 support two input
modes to program the M divider and N output divider. The two
input operational modes are parallel and serial. Figure 1 shows
the timing diagram for each mode. In parallel mode the nP_LOAD
input is LOW. The data on inputs M0 through M8 and N0 through
N1 is passed directly to the M divider and N output divider. On
T2
0
0
0
0
1
1
1
1
T1
0
0
1
1
0
0
1
1
T0
0
1
0
1
0
1
0
1
TEST Output
Shift Register Out
High
PLL Reference Xtal ÷ 16
(VCO ÷ M) /2 (non 50% Duty Cycle M divider)
fOUT
LVCMOS Output Frequency < 200MHz
Low
(S_CLOCK ÷ M) /2 (non 50% Duty Cycle M divider)
fOUT ÷ 4
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
S_CLOCK ÷ N divider
fOUT
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
NOTE: nP_LOAD is designed to eliminate runt pulses when changing M and N bits.
©2016 Integrated Device Technology, Inc
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Revision B May 26, 2016
84330-02 Data Sheet
TABLE 1. PIN DESCRIPTIONS
Name
Type
VCCA
Power
Description
Analog supply pin.
XTAL_IN,
XTALOUT
Crystal oscillator interface. XTAL_IN is an oscillator input.
XTAL_OUT is an oscillator output.
Selects between the crystal oscillator or FREF_EXT inputs as the PLL reference
source. Selects XTAL inputs when HIGH. Selects FREF_EXT when LOW.
LVCMOS / LVTTL interface levels.
XTAL_SEL
Input
Pullup
OE
Input
Pullup
Output enable. LVCMOS / LVTTL interface levels.
nP_LOAD
Input
Pullup
Parallel load input. Determines when data present at M8:M0 is loaded into
M divider, and when data present at N1:N0 sets the N output divide value.
LVCMOS / LVTTL interface levels.
M0, M1, M2
M3, M4, M5
M6, M7, M8
Input
Pullup
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS / LVTTL interface levels.
N0, N1
Input
Pullup
Determines N output divider value as defined in Table 3C Function Table.
LVCMOS / LVTTL interface levels.
VEE
Power
Negative supply pins.
TEST
Output
Test output which is used in the serial mode of operation.
LVCMOS / LVTTL interface levels.
VCC
Power
Core supply pins.
nFOUT, FOUT
Output
Differential output for the synthesizer. 3.3V LVPECL interface levels.
nc
Unused
Do not connect.
FREF_EXT
Input
S_CLOCK
Input
S_DATA
Input
S_LOAD
Input
Pulldown PLL reference input. LVCMOS / LVTTL interface levels.
Clocks the serial data present at S_DATA input into the shift register on the
Pulldown
rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
Pulldown
LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the M divider.
Pulldown
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
RPULLUP
RPULLDOWN
Test Conditions
Minimum
Typical
Maximum
Units
4
pF
Input Pullup Resistor
51
kΩ
Input Pulldown Resistor
51
kΩ
©2016 Integrated Device Technology, Inc
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84330-02 Data Sheet
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
nP_LOAD
M
N
S_LOAD
S_CLOCK
S_DATA
L
Data
Data
X
X
X
↑
Data
Data
L
X
X
H
X
X
L
↑
Data
H
X
X
↑
L
Data
H
X
X
↓
L
Data
M divide and N output divide values are latched.
X
X
Parallel or serial input do not affect shift registers.
H
X
X
L
H
X
X
H
Data
Data on M and N inputs passed directly to M divider and N
output divider. TEST mode 000.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider
and N output divider.
S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don’t care
↑ = Rising edge transition
↓ = Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
128
64
32
16
8
4
2
1
M8
M7
M6
M5
M4
M3
M2
M1
M0
0
0
1
1
1
1
1
0
1
126
0
0
1
1
1
1
1
1
0
254
127
0
0
1
1
1
1
1
1
1
256
128
0
1
0
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
696
348
1
0
1
0
1
1
1
0
0
698
349
1
0
1
0
1
1
1
0
1
700
350
1
0
1
0
1
1
1
1
0
VCO Frequency
(MHz)
M Divide
250
125
252
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
N Divider Value
Output Frequency (MHz)
N1
N0
0
0
2
0
1
4
62.5
175
1
0
8
31.25
87.5
1
1
1
250
700
©2016 Integrated Device Technology, Inc
Minimum
Maximum
125
350
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Revision B May 26, 2016
84330-02 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC + 0.5 V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
37.8°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. DC POWER SUPPLY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VCC
VCCA
ICC
ICCA
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
3.135
3.3
3.465
V
Analog Supply Voltage
3.135
3.3
3.465
V
Power Supply Current
130
mA
Analog Supply Current
15
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
VOH
M0-M8, N0, N1,
OE, nP_LOAD, XTAL_
SEL
Input High Current
S_LOAD, S_CLOCK
FREF_EXT, S_DATA
M0-M8, N0, N1,
OE, nP_LOAD, XTAL_
SEL
Input Low Current
S_LOAD, S_CLOCK
FREF_EXT, S_DATA
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
IIH
IIL
Test Conditions
Minimum
Typical
Maximum
Units
2
VCC + 0.3
V
-0.3
0.8
V
VCC = VIN = 3.465V
5
µA
VCC = VIN = 3.465V
150
µA
VCC = 3.465V, VIN = 0V
-150
µA
VCC = 3.465V, VIN = 0V
-5
µA
2.6
V
0.5
V
Maximum
Units
V
NOTE 1: Outputs terminated with 50Ω to VCC/2.
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VOH
Output High Voltage; NOTE 1
VCC - 1.4
VCC - 0.9
VOL
Output Low Voltage; NOTE 1
VCC - 2.0
VCC - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
©2016 Integrated Device Technology, Inc
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Revision B May 26, 2016
84330-02 Data Sheet
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
10
70
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
XTAL; NOTE 1
fIN
Input Frequency
Minimum
Typical
10
S_CLOCK
FREF_EXT; NOTE 2
10
Maximum
Units
25
MHz
50
MHz
25
MHz
NOTE 1: For the crystal frequency range the M value must be set to achieve the minimum or maximum VCO frequency range
of 250MHz to 700MHz. Using the minimum frequency of 10MHz, valid values of M are 200 ≤ M ≤ 511.
Using the maximum frequency of 25MHz, valid values of M are 80 ≤ M ≤ 224.
NOTE 2: Maximum frequency on FREF_EXT is dependent on the internal M counter limitations. See Application Information
Section for recommendations on optimizing the performance using the FREF_EXT input.
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
FOUT
Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
700
MHz
tjit(per)
Period Jitter, RMS; NOTE 1, 2
5
ps
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1, 2
40
ps
tR / tF
Output Rise/Fall Time
20% to 80%
600
ps
tnP_LOAD
Input
Rise Time
20% to 80%
50
ns
tS
Setup Time
tH
Hold Time
tL
PLL Lock Time
odc
Parallel Data Load Time
200
S_DATA to S_CLOCK
20
ns
S_CLOCK to S_LOAD
20
ns
M, N to nP_LOAD
20
ns
S_DATA to S_CLOCK
20
ns
M, N to nP_LOAD
20
ns
Output Duty Cycle
10
ms
N≠1
45
55
%
N = 1, fOUT ≤ 250MHz
45
55
%
N = 1,
250MHz < fOUT ≤ 500MHz
40
60
%
See Parameter Measurement Information section.
Characterized using a XTAL input.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65
NOTE 2: See Applications section.
©2016 Integrated Device Technology, Inc
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Revision B May 26, 2016
84330-02 Data Sheet
PARAMETER MEASUREMENT INFORMATION
3.3V OUTPUT LOAD AC TEST CIRCUIT
PERIOD JITTER
CYCLE-TO-CYCLE JITTER
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
©2016 Integrated Device Technology, Inc
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Revision B May 26, 2016
84330-02 Data Sheet
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The 84330-02 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC and VCCA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
10Ω
.01μF
10μF
VCCA
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
FIGURE 3A. LVPECL OUTPUT TERMINATION
©2016 Integrated Device Technology, Inc
FIGURE 3B. LVPECL OUTPUT TERMINATION
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Revision B May 26, 2016
84330-02 Data Sheet
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept single ended LVCMOS signal
through an AC couple capacitor. A general interface diagram
is shown in Figure 4. The XTAL_OUT input can be left floating.
The edge rate can be as slow as 10ns. If the incoming signal
has sharp edge rate and the signal path is a long trace, proper
termination for the driver and controlled characteristic imped-
ance trace may be required. The input can function with half
swing amplitude. Reducing amplitude from full swing of 3.3V
to half swing of about 1.65V can prevent signal interfere with
power rail and may reduce noise. Please refer to the LVCMOS
driver data sheet and application note for amplitude reduction
and termination approach.
3.3V
C1
XTAL_IN
0.1uF
LVCMOS_Driv er
XTAL_OUT
Cry stal Interf ace
Figure 4. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
FIGURE 5. CYCLE-TO-CYCLE JITTER VS. fOUT (using a 16MHz XTAL)
©2016 Integrated Device Technology, Inc
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Revision B May 26, 2016
84330-02 Data Sheet
LAYOUT GUIDELINE
The schematic of the 84330-02 layout example used in
this layout guideline is shown in Figure 6A. The 84330-02
recommended PCB board layout for this example is shown
in Figure 6B. This layout example is used as a general
guideline. The layout in the actual system will depend on the
selected component types, the density of the components, the
density of the traces, and the stack up of the P.C. board.
SP
C1
X1
C2
16MHz, 18pF
M3
M2
M1
M0
nPLOAD
OE
SP
M[8:0]= 110010000 (400)
N[1:0] =00 (Divide by 2)
M4
M5
M6
M7
M8
N0
N1
U1
ICS84330-02
4
3
2
1
28
27
26
R7
10
VCCA
C11
0.01u
C16
10u
C3
VCC
VCC
X_IN
XTAL_SEL
FREF_EXT
VCCA
S_LOAD
S_DATA
S_CLOCK
VEE
TEST
VCC
VEE
nFOUT
FOUT
VCC
SP = Space (i.e. not intstalled)
12
13
14
15
16
17
18
19
20
21
22
23
24
25
M4
M5
M6
M7
M8
N2
N1
VCC=3.3V
M3
M2
M1
M0
nP_LOAD
OE
X_OUT
11
10
9
8
7
6
5
VCC
0.1uF
Zo = 50 Ohm
RD0
1K
RD1
1K
RD7
SP
RD8
SP
RU10
1K
RD9
1K
RU11
SP
RD10
SP
RU12
1K
Fout = 200 MHz
C4
0.1u
+
Zo = 50 Ohm
OE
N1
N0
RU9
SP
nPLoad
RU8
1K
M8
RU7
1K
M7
RU1
SP
M1
M0
RU0
SP
RD6
1K
-
RD12
SP
R2
50
R1
50
R3
50
FIGURE 6A. SCHEMATIC OF RECOMMENDED LAYOUT
©2016 Integrated Device Technology, Inc
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Revision B May 26, 2016
84330-02 Data Sheet
The following component footprints are used in this layout
example:
• The differential 50Ω output traces should have the
same length.
All the resistors and capacitors are size 0603.
• Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
POWER AND GROUNDING
Place the decoupling capacitors C3 and C4, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
• Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces
in parallel with the clock traces. If running parallel traces
is unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VCCA pin as possible.
• Make sure no other signal traces are routed between
the clock trace pair.
CLOCK TRACES AND TERMINATION
• The matching termination resistors should be located as
close to the receiver input pins as possible.
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity
than other signals. Any ringing on the rising or falling edge or
excessive ring back can cause system failure. The shape of the
trace and the trace delay might be restricted by the available
space on the board and the component location. While routing
the traces, the clock signal traces should be routed first and
should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the
pins 4 (XTAL_IN) and 5 (XTAL_OUT). The trace length between
the X1 and U1 should be kept to a minimum to avoid unwanted
parasitic inductance and capacitance. Other signal traces should
not be routed near the crystal traces.
FIGURE 6B. PCB BOARD LAYOUT FOR 84330-02
©2016 Integrated Device Technology, Inc
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Revision B May 26, 2016
84330-02 Data Sheet
JITTER REDUCTION FOR FREF_EXT SINGLE END INPUT
If the FREF_EXT input is driven by a 3.3V LVCMOS driver, the
jitter performance can be improved by reducing the amplitude
swing and slowing down the edge rate. Figure 7A shows an
amplitude reduction approach for a long trace. The swing will
be approximately 0.85V for logic low and 2.5V for logic high
(instead of 0V to 3.3V). Figure 7B shows amplitude reduction
approach for a short trace. The circuit shown in Figure 7C
reduces amplitude swing and also slows down the edge rate
by increasing the resistor value.
VDD
VDD
Ro ~ 7 Ohm
RS
Zo = 50 Ohm
Td
R1
100
VDD
43
GND
TEST_CLK
R2
100
Driver_LVCMOS
FREF_EXT
FIGURE 7A. AMPLITUDE REDUCTION FOR A LONG TRACE
VDD
VDD
R1
200
Ro ~ 7 Ohm
RS
VDD
100
GND
TEST_CLK
R2
200
Driver_LVCMOS
FREF_EXT
FIGURE 7B. AMPLITUDE REDUCTION FOR A SHORT TRACE
VDD
VDD
R1
400
Ro ~ 7 Ohm
RS
VDD
200
GND
R2
400
Driver_LVCMOS
TEST_CLK
FREF_EXT
FIGURE 7C. EDGE RATE REDUCTION BY INCREASING THE RESISTOR VALUE
©2016 Integrated Device Technology, Inc
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84330-02 Data Sheet
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 84330-02.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 84330-02 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 145mA = 502.4mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 502.4mW + 30mW = 532.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming
a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W per Table 9 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.532W * 31.1°C/W = 86.6°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 9. THERMAL RESISTANCE θJA FOR 28-PIN PLCC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
37.8°C/W
31.1°C/W
28.3°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
©2016 Integrated Device Technology, Inc
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84330-02 Data Sheet
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in the Figure 8.
FIGURE 8. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination voltage of VCC- 2V.
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX - VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V
(VCC_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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84330-02 Data Sheet
RELIABILITY INFORMATION
TABLE 10. θJAVS. AIR FLOW PLCC TABLE FOR 28 LEAD PLCC
θJA by Velocity (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
37.8°C/W
31.1°C/W
28.3°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for 84330-02 is: 4442
©2016 Integrated Device Technology, Inc
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84330-02 Data Sheet
PACKAGE OUTLINE - V SUFFIX FOR 28 LEAD PLCC
TABLE 11. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
N
MAXIMUM
28
A
4.19
4.57
A1
2.29
3.05
A2
1.57
2.11
b
0.33
0.53
c
0.19
0.32
D
12.32
12.57
D1
11.43
11.58
D2
4.85
5.56
E
12.32
12.57
E1
11.43
11.58
E2
4.85
5.56
Reference Document: JEDEC Publication 95, MS-018
©2016 Integrated Device Technology, Inc
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84330-02 Data Sheet
TABLE 12. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
84330AV-02LF
ICS84330AV02L
28 Lead “Lead-Free” PLCC
tube
0°C to 70°C
84330AV-02LFT
ICS84330AV02L
28 Lead “Lead-Free” PLCC
tape & reel
0°C to 70°C
©2016 Integrated Device Technology, Inc
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Revision B May 26, 2016
84330-02 Data Sheet
REVISION HISTORY SHEET
Rev
Table
Page
B
T12
17
19
T12
17
B
B
Description of Change
Date
Updated datasheet’s header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
Remove ICS from the part number where needed.
Ordering Information - removed leaded part numbers, 500 from tape and reel
and the note below the table.
Updated headers and footers.
Product Discontinuation Notice - Last time buy expires May 6, 2017.
PDN CQ-16-01
©2016 Integrated Device Technology, Inc
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7/25/10
1/14/16
5/26/16
Revision B May 26, 2016
84330-02 Data Sheet
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