ICS84330
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS84330 is a general purpose, single output
high frequency synthesizer and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO and
output frequency can be programmed using the serial or parallel
interfaces to the configuration logic. The output can be configured to divide the VCO frequency by 1, 2, 4, and 8. Output frequency steps from 250kHz to 2MHz can be achieved using a
16MHz crystal depending on the output divider setting.
• Fully integrated PLL, no external loop filter requirements
ICS
• One differential 3.3V LVPECL output
• Crystal oscillator interface: 10MHz to 25MHz
• Output frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• Parallel or serial interface for programming M and N
dividers during power-up
• RMS Period jitter: 5ps (maximum)
• Cycle-to-cycle jitter: 40ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
• Industrial temperature information available upon request
VEE
TEST
VCC
OSC
S_CLOCK
26
S_DATA
27
S_LOAD
1
XTAL_OUT
0
VCCA
÷ 16
FREF_EXT
XTAL_SEL
XTAL_SEL
XTAL_IN
PLL
PHASE DETECTOR
1
17
N0
28
16
28-Lead PLCC
V Package
15
11.6mm x 11.4mm x 4.1mm
2
14
body package
3
13
Top View
M8
1
M7
12
M4
ICS84330
4
5
M5
M3
M2
VEE
TEST
VCC
S_CLOCK
1
32 31 30 29 28 27 26 25
24
n/c
S_DATA
2
23
N1
S_LOAD
3
22
N0
VCCA
4
21
M8
VCCA
5
20
M7
FREF_EXT
6
19
M6
XTAL_SEL
7
18
M5
XTAL_IN
8
17
9 10 11 12 13 14 15 16
M4
ICS84330
32-Lead LQFP
Y package
7mm x 7mm x 1.4mm
body package
Top View
nc
M3
M2
M1
M0
nP_LOAD
OE
XTAL_OUT
www.icst.com/products/hiperclocks.html
1
M6
9 10 11
VCC
N0:N1
8
VEE
M0:M8
nFOUT
VCC
TEST
FOUT
CONFIGURATION
INTERFACE
LOGIC
7
M1
0
6
M0
FOUT
nFOUT
nP_LOAD
÷2
N1
OE
÷M
÷2
÷4
÷8
÷1
18
XTAL_OUT
VCO
84330BV
VEE
XTAL_IN
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
nFOUT
VCC
25 24 23 22 21 20 19
OE
FREF_EXT
FOUT
PIN ASSIGNMENT
BLOCK DIAGRAM
REV. C MAY 16, 2006
ICS84330
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 6, NOTE 1.
the LOW-to-HIGH transition of the nP_LOAD input, the data is
latched and the M divider remains loaded until the next LOW
transition on nP_LOAD or until a serial event occurs. The TEST
output is Mode 000 (shift register out) when operating in the
parallel input mode. The relationship between the VCO frequency,
the crystal frequency and the M divider is defined as follows:
fxtal x
fVCO =
2M
16
The ICS84330 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A quartz crystal is used as the input to the on-chip
oscillator. The output of the oscillator is divided by 16 prior to
the phase detector. With a 16MHz crystal this provides a 1MHz
reference frequency. The VCO of the PLL operates over a
range of 250MHz to 700MHz. The output of the M divider is
also applied to the phase detector.
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock are
defined as 125 ≤ M ≤ 350. The frequency out is defined as
follows: fout = fVCO = fxtal x 2M
N
N
16
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD.
If S_LOAD is held HIGH, data at the S_DATA input is passed
directly to the M divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and
test bits T2:T0. The internal registers T2:T0 determine the state
of the TEST output as follows:
The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the
LVPECL output buffers. The divider provides a 50% output duty
cycle.
The programmable features of the ICS84330 support two input
modes to program the M divider and N output divider. The two
input operational modes are parallel and serial. Figure 1 shows
the timing diagram for each mode. In parallel mode the nP_LOAD
input is LOW. The data on inputs M0 through M8 and N0 through
N1 is passed directly to the M divider and N output divider. On
T2
0
0
0
0
1
T1
0
0
1
1
0
T0
0
1
0
1
0
1
1
1
0
1
1
1
0
1
TEST Output
Shift Register Out
High
PLL Reference Xtal ÷ 16
(VCO ÷ M) /2 (non 50% Duty Cycle M divider)
fOUT
LVCMOS Output Frequency < 200MHz
Low
(S_CLOCK ÷ M) /2 (non 50% Duty Cycle M divider)
fOUT ÷ 4
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
S_CLOCK ÷ N divider
fOUT
SERIAL LOADING
S_CLOCK
S_DATA
T2
t
S_LOAD
S
T1
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
H
t
nP_LOAD
S
PARALLEL LOADING
M0:M8, N0:N1
M, N
nP_LOAD
t
S
t
H
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
84330BV
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2
REV. C MAY 16, 2006
ICS84330
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Name
Type
VCCA
XTAL_IN,
XTAL_OUT
Power
XTAL_SEL
Input
Pullup
OE
Input
Pullup
nP_LOAD
Input
Pullup
M0, M1, M2
M3, M4, M5
M6, M7, M8
Input
Pullup
N0, N1
Input
Pullup
VEE
Power
TEST
Output
VCC
Power
nFOUT, FOUT
nc
FREF_EXT
Output
Unused
Input
Description
Analog supply pin.
Crystal oscillator interface. XTAL_IN is an oscillator input.
XTAL_OUT is an oscillator output.
Selects between the crystal oscillator or FREF_EXT inputs as the PLL reference
source. Selects XTAL inputs when HIGH. Selects FREF_EXT when LOW.
LVCMOS / LVTTL interface levels.
Output enable. LVCMOS / LVTTL interface levels.
Parallel load input. Determines when data present at M8:M0 is loaded into
M divider, and when data present at N1:N0 sets the N output divide value.
LVCMOS / LVTTL interface levels.
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.
LVCMOS / LVTTL interface levels.
Determines N output divider value as defined in Table 3C Function Table.
LVCMOS / LVTTL interface levels.
Negative supply pins.
Test output which is used in the serial mode of operation.
LVCMOS / LVTTL interface levels.
Core supply pins.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Do not connect.
Pulldown PLL reference input. LVCMOS / LVTTL interface levels.
Clocks the serial data present at S_DATA input into the shift register on the
S_CLOCK
Input
Pulldown
rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
S_DATA
Input
Pulldown
LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the M divider.
S_LOAD
Input
Pulldown
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
Minimum
Typical
4
Maximum
Units
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
84330BV
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3
REV. C MAY 16, 2006
ICS84330
Integrated
Circuit
Systems, Inc.
TABLE 3A. PARALLEL
AND
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
SERIAL MODE FUNCTION TABLE
Inputs
nP_LOAD
M
N
S_LOAD
S_CLOCK
S_DATA
X
X
X
X
X
X
L
Data
Data
X
X
X
↑
Data
Data
L
X
X
H
X
X
L
↑
Data
H
X
X
↑
L
Data
H
X
X
↓
L
Data
H
X
X
L
X
X
H
X
X
H
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
↑
Data
Conditions
Reset. M and N bits are all set HIGH.
Data on M and N inputs passed directly to M divider and
N output divider. TEST mode 000.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider
and N output divider.
M divide and N output divide values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
VCO Frequency
(MHz)
M Divide
256
128
64
32
16
8
4
2
1
M8
M7
M6
M5
M4
M3
M2
M1
M0
250
125
0
0
1
1
1
1
1
0
1
252
126
0
0
1
1
1
1
1
1
0
254
127
0
0
1
1
1
1
1
1
1
256
128
0
1
0
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
696
348
1
0
1
0
1
1
1
0
0
698
349
1
0
1
0
1
1
1
0
1
700
350
1
0
1
0
1
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
N Divider Value
Output Frequency (MHz)
N1
N0
0
0
2
0
1
4
62.5
175
1
0
8
31.25
87.5
1
1
1
250
700
84330BV
Minimum
Maximum
125
350
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4
REV. C MAY 16, 2006
ICS84330
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC + 0.5 V
NOTE: Stresses beyond those listed under Absolute
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
device. These ratings are stress specifications only. Functional
Package Thermal Impedance, θJA
32 Lead LQFP
28 Lead PLCC
47.9°C/W (0 lfpm)
37.8°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
Maximum Ratings may cause permanent damage to the
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. DC POWER SUPPLY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
Test Conditions
3.135
3. 3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
ICC
Power Supply Current
130
mA
ICCA
Analog Supply Current
15
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Maximum
Units
VIH
Input High Voltage
Test Conditions
2
VCC + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
VCC = VIN = 3.465V
5
µA
VCC = VIN = 3.465V
150
µA
VOH
M0-M8, N0, N1,
OE, nP_LOAD,
XTAL_SEL
Input High Current
S_LOAD, S_CLOCK
FREF_EXT, S_DATA
M0-M8, N0, N1,
OE, nP_LOAD,
XTAL_SEL
Input Low Current
S_LOAD, S_CLOCK
FREF_EXT, S_DATA
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
IIH
IIL
Minimum Typical
VCC = 3.465V, VIN = 0V
-150
µA
VCC = 3.465V, VIN = 0V
-5
µA
2.6
V
0.5
V
NOTE 1: Outputs terminated with 50Ω to VCC/2.
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Maximum
Units
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
VCC - 1.4
Typical
VCC - 1.0
V
V OL
Output Low Voltage; NOTE 1
VCC - 2.0
VCC - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
84330BV
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5
REV. C MAY 16, 2006
ICS84330
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
Frequency
10
25
MHz
Equivalent Series Resistance (ESR)
70
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
fIN
Input Frequency
Minimum
XTAL; NOTE 1
Typical
10
S_CLOCK
Maximum
Units
25
MHz
50
MHz
FREF_EXT; NOTE 2
10
MHz
NOTE 1: For the cr ystal frequency range the M value must be set to achieve the minimum or maximum VCO frequency
range of 250MHz to 700MHz. Using the minimum frequency of 10MHz, valid values of M are 200 ≤ M ≤ 511.
Using the maximum frequency of 25MHz, valid values of M are 80 ≤ M ≤ 224.
NOTE 2: Maximum frequency on FREF_EXT is dependent on the internal M counter limitations. See Application
Information Section for recommendations on optimizing the performance using the FREF_EXT input.
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
FOUT
Output Frequency
Minimum
Typical
Maximum
Units
700
MHz
tjit(per)
Period Jitter, RMS; NOTE 1, 2
5
ps
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1, 2
40
ps
tR / tF
Output Rise/Fall Time
600
ps
tS
Setup Time
200
20
ns
S_CLOCK to S_LOAD
20
ns
M, N to nP_LOAD
20
ns
S_DATA to S_CLOCK
20
ns
M, N to nP_LOAD
20
tH
Hold Time
tL
PLL Lock Time
odc
20% to 80%
S_DATA to S_CLOCK
Output Duty Cycle
ns
10
ms
N≠1
45
55
%
N = 1, fOUT ≤ 250MHz
N = 1,
250MHz < fOUT ≤ 500MHz
45
55
%
40
60
%
See Parameter Measurement Information section.
Characterized using a XTAL input.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65
NOTE 2: See Applications section.
84330BV
www.icst.com/products/hiperclocks.html
6
REV. C MAY 16, 2006
ICS84330
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
VOH
VCC,
VCCA
Qx
SCOPE
VREF
nQx
VEE
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
LVPECL
Histogram
Reference Point
Mean Period
(Trigger Edge)
(First edge after trigger)
-1.3V ± 0.165V
PERIOD JITTER
3.3V OUTPUT LOAD AC TEST CIRCUIT
nFOUT
80%
80%
V
FOUT
SW I N G
tcycle n+1
➤
➤
tcycle n
20%
20%
➤
Clock Outputs
➤
t
R
t
F
t jit(cc) = tcycle n –tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
OUTPUT RISE/FALL TIME
nFOUT
FOUT
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
84330BV
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7
REV. C MAY 16, 2006
ICS84330
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84330 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V CC and V CCA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin. The 10Ω
resistor can also be replaced by a ferrit bead.
3.3V
VCC
.01μF
10Ω
.01μF
10μF
VCCA
FIGURE 2. POWER SUPPLY FILTERING
LVCMOS TO XTAL INTERFACE
acteristic impedance trace may be required. The input can
function with half swing amplitude. Reducing amplitude from
full swing of 3.3V to half swing of about 1.65V can prevent
signal interfere with power rail and may reduce noise. Please
refer to the LVCMOS driver data sheet and application note
for amplitude reduction and termination approach.
The XTAL_IN input can accept single ended LVCMOS signal
through an AC couple capacitor. A general interface diagram
is shown in Figure 3. The XTAL_OUT input can be left
floating. The edge rate can be as slow as 10ns. If the incoming signal has sharp edge rate and the signal path is a long
trace, proper termination for the driver and controlled char-
3.3V
C1
XTAL_IN
0.1uF
LVCMOS_Driv er
XTAL_OUT
Cry stal Interf ace
Figure 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT PINS
INPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
84330BV
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8
REV. C MAY 16, 2006
ICS84330
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
JITTER REDUCTION FOR FREF_EXT SINGLE END INPUT
If the FREF_EXT input is driven by a 3.3V LVCMOS driver, the
jitter performance can be improved by reducing the amplitude
swing and slowing down the edge rate. Figure 4A shows an
amplitude reduction approach for a long trace. The swing will
be approximately 0.85V for logic low and 2.5V for logic high
(instead of 0V to 3.3V). Figure 4B shows amplitude reduction
approach for a short trace. The circuit shown in Figure 4C
reduces amplitude swing and also slows down the edge rate
by increasing the resistor value.
VDD
VDD
Ro ~ 7 Ohm
RS
Zo = 50 Ohm
Td
R1
100
VDD
GND
43
R2
100
Driver_LVCMOS
TEST_CLK
FREF_EXT
FIGURE 4A. AMPLITUDE REDUCTION FOR A LONG TRACE
VDD
VDD
R1
200
Ro ~ 7 Ohm
VDD
RS
GND
100
R2
200
Driver_LVCMOS
TEST_CLK
FREF_EXT
FIGURE 4B. AMPLITUDE REDUCTION FOR A SHORT TRACE
VDD
VDD
R1
400
Ro ~ 7 Ohm
VDD
RS
GND
200
R2
400
Driver_LVCMOS
TEST_CLK
FREF_EXT
FIGURE 4C. EDGE RATE REDUCTION BY INCREASING THE RESISTOR VALUE
84330BV
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9
REV. C MAY 16, 2006
ICS84330
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Cycle-to-Cycle Jitter (ps)
50
40
30
Spec Limit
N=1
20
10
0
200
300
400
500
600
700
Output Frequency (MHz)
FIGURE 5. CYCLE-TO-CYCLE JITTER VS. fOUT (using a 16MHz XTAL)
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 6A and
6B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched imped-
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
VCC - 2V
Zo = 50Ω
RTT
84Ω
FIGURE 6A. LVPECL OUTPUT TERMINATION
84330BV
FIN
50Ω
84Ω
FIGURE 6B. LVPECL OUTPUT TERMINATION
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10
REV. C MAY 16, 2006
ICS84330
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
The schematic of the ICS84330 layout example used in
this layout guideline is shown in Figure 7A. The ICS84330
recommended PCB board layout for this example is shown
in Figure 7B. This layout example is used as a general guide-
line. The layout in the actual system will depend on the selected component types, the density of the components, the
density of the traces, and the stack up of the P.C. board.
SP
C1
X1
C2
16MHz, 18pF
M3
M2
M1
M0
nPLOAD
OE
SP
V CC=3 .3 V
S P = S p a ce (i .e . n o t i n tsta l l e d )
M [8 :0 ]= 0 1 1 0 0 1 0 0 0 (2 0 0 )
N[1 :0 ] =0 0 (Di vi d e b y 2 )
12
13
14
15
16
17
18
M4
M5
M6
M7
M8
N0
N1
19
20
21
22
23
24
25
U1
ICS84330
X_IN
XTAL_SEL
FREF_EXT
VCCA
S_LOAD
S_DATA
S_CLOCK
VCC
VCC
4
3
2
1
28
27
26
VEE
TEST
VCC
VEE
nFOUT
FOUT
VCC
M4
M5
M6
M7
M8
N2
N1
M3
M2
M1
M0
nP_LOAD
OE
X_OUT
11
10
9
8
7
6
5
VCC
R7
10
VCCA
C11
0.01u
C16
10u
C3
0.1uF
Zo = 50 Ohm
RD0
1K
RD1
1K
RD7
SP
RD8
1K
RU10
1K
RD9
1K
RU11
SP
nPLoad
RD10
SP
RU12
1K
Fo u t = 2 0 0 M Hz
C4
0.1u
+
Zo = 50 Ohm
OE
N0
RU9
SP
N1
RU8
SP
M8
RU7
1K
M7
RU1
SP
M1
M0
RU0
SP
RD6
1K
-
RD12
SP
R2
50
R1
50
R3
50
FIGURE 7A. SCHEMATIC OF RECOMMENDED LAYOUT
84330BV
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11
REV. C MAY 16, 2006
ICS84330
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
The following component footprints are used in this layout
example:
• The differential 50Ω output traces should have the
same length.
All the resistors and capacitors are size 0603.
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
POWER
AND
GROUNDING
Place the decoupling capacitors C3 and C4, as close as possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
• Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VCCA pin as possible.
• Make sure no other signal traces are routed between the
clock trace pair.
CLOCK TRACES
• The matching termination resistors should be located as
close to the receiver input pins as possible.
AND
TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the
pins 4 (XTAL_IN) and 5 (XTAL_OUT). The trace length between the X1 and U1 should be kept to a minimum to avoid
unwanted parasitic inductance and capacitance. Other signal
traces should not be routed near the crystal traces.
X1
C1
C2
U1
GND
VCC
PIN 2
C11
C16
VCCA
PIN 1
VCCA
R7
VIA
Signals
Traces
C3
C4
50 Ohm
Traces
FIGURE 7B. PCB BOARD LAYOUT FOR ICS84330
84330BV
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REV. C MAY 16, 2006
ICS84330
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84330.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84330 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 145mA = 502.4mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 1 * 30.2mW = 30.2mW
Total Power_MAX (3.465V, with all outputs switching) = 502.4 + 30.2mW = 532.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W per Table 9A below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.533W * 31.1°C/W = 86.6°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 9A. THERMAL RESISTANCE θJA
FOR
28-PIN PLCC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
37.8°C/W
31.1°C/W
28.3°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 9B. THERMAL RESISTANCE θJA
FOR
32-PIN LQFP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
84330BV
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13
REV. C MAY 16, 2006
ICS84330
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in the Figure 8.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 8. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
For logic high, VOUT = V
OH_MAX
(V
CC_MAX
•
-V
OH_MAX
OL_MAX
CC_MAX
CC_MAX
– 1.0V
) = 1.0V
For logic low, VOUT = V
(V
=V
=V
CC_MAX
– 1.7V
) = 1.7V
-V
OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
- 2V))/R ] * (V
CC_MAX
L
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
CC_MAX
L
-V
OH_MAX
)=
[(2V - 1V)/50Ω] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
84330BV
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14
REV. C MAY 16, 2006
ICS84330
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 10A. θJAVS. AIR FLOW PLCC TABLE FOR 28 LEAD PLCC
θJA by Velocity (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
37.8°C/W
31.1°C/W
28.3°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 10B. θJAVS. AIR FLOW LQFP TABLE FOR 32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84330 is: 4442
Pin compatible with the MC12430
84330BV
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15
REV. C MAY 16, 2006
ICS84330
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - V SUFFIX FOR 28 LEAD PLCC
TABLE 11A. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
28
N
A
4.19
4.57
A1
2.29
3.05
A2
1.57
2.11
b
0.33
0.53
c
0.19
0.32
D
12.32
12.57
D1
11.43
11.58
D2
4.85
5.56
E
12.32
12.57
E1
11.43
11.58
E2
4.85
5.56
Reference Document: JEDEC Publication 95, MS-018
84330BV
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16
REV. C MAY 16, 2006
ICS84330
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 11B. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
0.80 BASIC
e
0.60
0.75
L
0.45
θ
0°
--
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
84330BV
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17
REV. C MAY 16, 2006
ICS84330
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 12. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS84330BV
ICS84330BV
28 Lead PLCC
Tube
0°C to 70°C
ICS84330BVT
ICS84330BV
28 Lead PLCC
500 Tape & Reel
0°C to 70°C
ICS84330BVLF
TB D
28 Lead "Lead-Free" PLCC
Tube
0°C to 70°C
ICS84330BVLFT
TBD
28 Lead "Lead-Free" PLCC
500 Tape & Reel
0°C to 70°C
ICS84330BY
ICS84330BY
32 Lead LQFP
Tray
0°C to 70°C
ICS84330BYT
ICS84330BY
32 Lead LQFP
1000 Tape & Reel
0°C to 70°C
ICS84330BYLN
ICS84330BYLN
32 Lead "Lead Free/Annealed" LQFP
Tray
0°C to 70°C
32 Lead "Lead Free/Annealed" LQFP 1000 Tape & Reel
0°C to 70°C
ICS84330BYLNT
ICS84330BYLN
NOTE: Par ts that are ordered with an "LF" or "LN" suffix to the par t number are the Pb-Free configuration and are RoHS
compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
84330BV
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18
REV. C MAY 16, 2006
Integrated
Circuit
Systems, Inc.
ICS84330
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET
Rev
Table
T4A
A
Page
2
5
9
1
8
10
1
Figure 7A Schematic Layout - revised, changed N[1:0]-01 to N[1:0}=00.
Added C1 value (18p) and C2 value (22p).
Block Diagram, replaced N with values.
Deleted Cr ystal Input Interface section; external tune up capacitor not required.
Revised Figure 6A, Schematic of Recommended Layout diagram.
General Description & Features - changed VCO min. from 200MHz to 250MHz
and replaced throughout the datasheet in (Functional Description pg2,
T3C Program. Output Divider Func. Table pg4, and T6 Input Freq Charac. pg6).
T2
3
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
T3B
4
Prog. VCO Freq. Func. Table - replaced VCO Frequency 200MHz to 206MHz
with 250MHz to 256MHz. Replaced M Divide 100 to 103 to 125 to 128.
Adjusted Logic High and Logic Low data.
5
Absolute Maximum Rating - changed Outputs VO and rating to IO with Continous
and Surge ratings.
Ordering Information Table - added "Lead Free/Annealed" par t number.
Updated format throughout data sheet.
Features section - corrected Output frequency range bullet from 25MHz to
31.25MHz.
Updated Figure 1.
Cr ystal Table - added Drive Level.
Ordering Information table - added Lead-Free note.
Changed XTAL1/2 naming convention to XTAL_IN/XTAL_OUT throughout the
datasheet.
Added Recommendations for Unused Input Pins.
Updated schematic layout.
Ordering Information Table - added Lead-Free p/n for PLCC.
10
A
B
B
T12
18
1
C
T5
T12
2
6
18
T12
8
11
18
C
84330BV
Description of Change
Switched S_DATA and S_CLOCK labels in Figure 1, CLK_EN Timing Diagram.
DC Power Supply table - changed ICC Parameter to read Power.. from Core...
Added "LVCMOS to XTAL Interface" section.
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19
Date
1/23/03
3/24/03
5/5/03
7/26/04
6/10/05
5/16/06
REV. C MAY 16, 2006
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