FemtoClock® NG Crystal-to-3.3V
LVPECL Frequency Synthesizer
843N252-45
Data Sheet
General Description
Features
The 843N252-45 is a 1 LVPECL and 1 LVCMOS output Synthesizer
optimized to generate Ethernet reference clock frequencies. The
device uses IDT’s fourth generation FemtoClock ® NG technology for
an optimum of high clock frequency and low phase noise
performance, combined with a low power consumption and high
power supply noise rejection. Using a 25MHz parallel resonant
crystal, the following frequencies can be generated: 156.25MHz and
125MHz. With a very low phase noise VCO it is targeted to achieve
0.4ps or lower typical rms phase jitter, easily meeting Ethernet jitter
requirements. The 843N252-45 is packaged in a small 16-pin
TSSOP package.
•
•
Fourth generation FemtoClock® Next Generation (NG) technology
•
Crystal oscillator interface designed for a 25MHz parallel resonant
crystal
•
A 25MHz crystal generates output frequencies of: 156.25MHz and
125MHz
•
•
VCO frequency: 625MHz
•
RMS Phase Jitter @ 125MHz, (12kHz – 20MHz) using a 25MHz
crystal: 0.39ps (typical)
•
•
•
•
Power supply noise rejection PSNR: -60dB (typical)
One differential 3.3V LVPECL output and one LVCMOS/LVTTL
output
RMS Phase Jitter @ 156.25MHz, (12kHz – 20MHz) using a
25MHz crystal: 0.33ps (typical)
Full 3.3V supply mode
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
Block Diagram
CLK_ENA
XTAL_IN
Pullup
25MHz
OSC
XTAL_OUT
PFD
&
LPF
FemtoClock®NG
VCO
QA
÷5
625MHz
QB
÷4
nQB
Feedback Divider
÷25
CLK_ENB
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLK_ENB
VEE
QB
nQB
VCC
XTAL_IN
XTAL_OUT
VEE
843N252-45
Pullup
©2016 Integrated Device Technology, Inc
CLK_ENA
VEE
QA
VCCOA
nc
nc
VCCA
VCC
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
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Revision A April 20, 2016
843N252-45 Data Sheet
Table 1. Pin Descriptions
Number
Name
1
CLK_ENA
Input
Type
Description
2, 9, 15
VEE
Power
Negative supply pins.
3
QA
Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
Pullup
Clock enable pin. LVCMOS/LVTTL interface levels. See Table 3A.
4
VCCOA
Power
5, 6
nc
Unused
7
VCCA
Power
Analog supply pin.
8, 12
VCC
Power
Power supply pin.
10
11
XTAL_OUT
XTAL_IN
Input
Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output.
13, 14
nQB, QB
Output
16
CLK_ENB
Input
Output supply pin for QA output.
No connect.
Differential output pair. LVPECL interface levels.
Pullup
Clock enable pin. LVCMOS/LVTTL interface levels. See Table 3B.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
RPULLUP
Input Pullup Resistor
ROUT
Output Impedance
QA
Minimum
VCC = VCCO_A = 3.465V
VCCO_A = 3.465V
Typical
Maximum
Units
4
pF
7
pF
51
k
15
Function Tables
Table 3A. CLK_ENA Function Table
Table 3B. CLK_ENB Function Table
Input
Outputs
Input
CLK_ENA
QA
CLK_ENB
QB
nQB
0
High-Impedance
0
HIGH
LOW
1
Active
1
Active
Active
©2016 Integrated Device Technology, Inc
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Outputs
Revision A April 20, 2016
843N252-45 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
3.63V
Inputs, VI
XTAL_IN
Other Inputs
0V to VCC
-0.5V to VCC + 0.5V
Outputs, VO (LVCMOS)
-0.5V to VCCOA + 0.5V
Outputs, IO (LVPECL)
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, JA
94.8C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCOA = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
VCC
Test Conditions
Minimum
Typical
Maximum
Units
Power Supply Voltage
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
VCC – 0.14
3.3
VCC
V
VCCOA
Power Supply Voltage
3.135
3.3
3.465
V
ICCA
Analog Supply Current
14
mA
IEE
Power Supply Current
124
mA
Maximum
Units
No Load
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCOA = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VIH
Input High Voltage
2
VCC + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input High Current
CLK_ENA,
CLK_ENB
VCC = VIN = 3.465V
5
µA
IIL
Input Low Current
CLK_ENA,
CLK_ENB
VCC = 3.465V, VIN = 0V
-150
µA
VOH
Output High Voltage; NOTE 1
VCCOA = 3.3V ± 5%
2.3
V
VOL
Output Low Voltage; NOTE 1
VCCOA = 3.3V ± 5%
0.5
V
NOTE 1: Outputs terminated with 50 to VCCOA/2. See Parameter Measurement Information section. Load Test Circuit diagrams.
©2016 Integrated Device Technology, Inc
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843N252-45 Data Sheet
Table 4C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Minimum
Typical
Maximum
Units
VCC – 1.4
VCC – 0.75
V
VCC – 2.0
VCC – 1.5
V
0.55
1.05
V
NOTE 1: Output termination with 50 to VCC – 2V.
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
AC Electrical Characteristics
Table 6. AC Characteristics, VCC = VCCOA = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
fOUT
Output Frequency
tjit(Ø)
RMS Phase Jitter
(Random); NOTE 1
Test Conditions
Minimum
QA
QB, nQB
PSNR
Power Supply Noise Reduction
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Maximum
Units
125
MHz
156.25
MHz
125MHz, Integration Range:
12kHz – 20MHz
0.39
ps
156.25MHz, Integration Range:
12kHz – 20MHz
0.33
ps
From DC to 10MHz
-60
dB
QB, nQB
QA
Typical
QA
20% to 80%
250
500
ps
QB, nQB
20% to 80%
150
300
ps
QA
47
53
%
QB, nQB
48
52
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Using a 25MHz, 12pF quartz crystal.
NOTE 1: Please refer to the Phase Noise plots.
©2016 Integrated Device Technology, Inc
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Revision A April 20, 2016
843N252-45 Data Sheet
Typical Phase Noise at 125MHz
Noise Power dBc
Hz
125MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.39ps (typical)
Offset Frequency (Hz)
Typical Phase Noise at 156.25MHz
Noise Power dBc
Hz
156.25MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.33ps (typical)
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc
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Revision A April 20, 2016
843N252-45 Data Sheet
Parameter Measurement Information
2V
1.65V±5%
1.65V±5%
2V
SCOPE
VCC,
VCC
VCCOA
VCCA
VCCA
Qx
GND
-1.3V± 0.165V
-1.65V±5%
3.3V LVPECL Output Load AC Test Circuit
3.3V LVCMOS Output Load AC Test Circuit
nQB
QB
RMS Phase Jitter
LVPECL Output Duty Cycle/Pulse Width/Period
nQB
QA
80%
t PW
t
80%
VSW I N G
PERIOD
20%
20%
QA, QB
odc =
t PW
tR
tF
x 100%
t PERIOD
Output Rise/Fall Time
LVCMOS Output Duty Cycle/Pulse Width/Period
©2016 Integrated Device Technology, Inc
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843N252-45 Data Sheet
Applications Information
Recommendations for Unused Input Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVPECL Outputs
All control pins have internal pull-ups; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
The unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS Outputs
The unused LVCMOS output can be left floating. There should be no
trace attached.
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 1A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100. This can also be
accomplished by removing R1 and making R2 50. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
3.3V
3.3V
R1
100
Ro ~ 7 Ohm
C1
Zo = 50 Ohm
XTAL_IN
RS
43
R2
100
Driv er_LVCMOS
0.1uF
XTAL_OUT
Cry stal Input Interf ace
Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface
VCC=3.3V
C1
Zo = 50 Ohm
XTAL_IN
R1
50
Zo = 50 Ohm
0.1uF
XTAL_OUT
LVPECL
Cry stal Input Interf ace
R2
50
R3
50
Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface
©2016 Integrated Device Technology, Inc
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Revision A April 20, 2016
843N252-45 Data Sheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 2A and 2B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
Figure 2A. 3.3V LVPECL Output Termination
R2
84
Figure 2B. 3.3V LVPECL Output Termination
Schematic Example
Figure 3 shows an example of 843N252-45 application schematic. In
this example, the device is operated at VCC = VCCA = VCCOA = 3.3V.
If the12pF parallel resonant 25MHz crystal is used; the load
capacitance C1 = 5pF and C2 = 5pF are recommended for frequency
accuracy. If the 18pF parallel resonant 25MHz crystal is used; the
load capacitance C1 = 15pF and C2 = 15pF are recommended.
Depending on the parasitics of the printed circuit board layout, these
values might require a slight adjustment to optimize the frequency
accuracy. Crystals with other load capacitance specifications can be
used. This will require adjusting C1 and C2. For this device, the
crystal load capacitors are required for proper operation.
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The 843N252-45 provides separate
power supplies to isolate from coupling into the internal PLL.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
©2016 Integrated Device Technology, Inc
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Revision A April 20, 2016
843N252-45 Data Sheet
R1
33
Zo = 50 Ohm
QA
LVCMOS
3.3V
U1
R2
133
CLK_EN_B
CLK_EN_A
VCCO
0.1u
C6
1
2
3
4
5
6
7
8
CLK_EN_A
VEE
QA
VCCOA
nc
nc
VCCA
VCC
VCC
16
15
14
13
12
11
10
9
CLK_EN_B
VEE
QB
nQB
VCC
XTAL_IN
XTAL_OUT
VEE
Zo = 50 Ohm
R3
133
QB
+
VCC
Zo = 50 Ohm
nQB
0.1u
-
C7
R4
VCC
VCCA
10
C4
0.1u
C3
0.1u
R5
82.5
VCC=3.3V
C5
10u
C1
R6
82.5
VCCOA=3.3V
5pF
3.3V
Logic Input Pin Examples
Set Logic
Input to
'1'
VCC
RU1
1K
1
Set Logic
Input to
'0'
VCC
X1 25MHz
12pF
BLM18BB221SN2
2
Zo = 50 Ohm
VCC
QB
Ferrite Bead C10
C9
0.1uF
5pF
10uF
RU2
Not Install
RD1
Not Install
To Logic
Input
pins
RD2
1K
Zo = 50 Ohm
nQB
3.3V
To Logic
Input
pins
+
C2
-
BLM18BB221SN2
1
2
R7
50
VCCO
Optional
LVPECL
Y-Termination
Ferrite Bead C15
C14
0.1uF
R8
50
10uF
R9
50
Figure 3. 843N252-45 Schematic Example
©2016 Integrated Device Technology, Inc
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Revision A April 20, 2016
843N252-45 Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 843N252-45.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 843N252-45 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Core and LVPECL Output Power Dissipation
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 124mA = 429.66mW
•
Power (LVPECL) = 33.75mW/Loaded Output pair
LVCMOS Output Power Dissipation
•
Output Impedance ROUT Power Dissipation due to Loading 50 to VCCOA/2
Output Current IOUT = VCCOA_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 15)] = 26.65mA
•
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 15 * (26.65mA)2 = 10.65mW per output
•
Dynamic Power Dissipation at 125MHz
Power (125MHz) = CPD * Frequency * (VCCOA)2 = 7pF * 125MHz * (3.465V)2 = 10.51mW
Total Power Dissipation
•
Total Power
= Power (core) + Power (LVPECL) + Power (ROUT) + Power (125MHz)
= 429.66mW + 33.75mW + 10.65mW + 10.51mW
= 484.57mW
©2016 Integrated Device Technology, Inc
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Revision A April 20, 2016
843N252-45 Data Sheet
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 94.8°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.485W * 94.8°C/W = 116°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 16 Lead TSSOP Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
©2016 Integrated Device Technology, Inc
0
1
2.5
94.8°C/W
90.4°C/W
88.3°C/W
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Revision A April 20, 2016
843N252-45 Data Sheet
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50Ω
VCC - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCC – 2V.
•
For logic high, VOUT = VOH_MAX = VCC_MAX –0.75V
(VCC_MAX – VOH_MAX) = 0.75V
•
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.5V
(VCC_MAX – VOL_MAX) = 1.5V
•
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX)
= [(2V – 0.75V)/50] * 0.75V = 18.75mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX)
= [(2V – 1.5V)/50] * 1.5V = 15mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 33.75mW
©2016 Integrated Device Technology, Inc
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843N252-45 Data Sheet
Reliability Information
Table 8. JA vs. Air Flow Table for a 16 Lead TSSOP
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
94.8°C/W
90.4°C/W
88.3°C/W
Transistor Count
The transistor count for 843N252-45 is: 2039
Package Outline and Package Dimensions
Package Outline - G Suffix for 16-Lead TSSOP
Table 9. Package Dimensions for 16 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
16
A
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
5.10
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
©2016 Integrated Device Technology, Inc
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Revision A April 20, 2016
843N252-45 Data Sheet
Ordering Information
Table 10. Ordering Information
Part/Order Number
843N252GG-45LF
843N252GG-45LFT
Marking
N252G45L
N252G45L
©2016 Integrated Device Technology, Inc
Package
“Lead-Free” 16 Lead TSSOP
“Lead-Free” 16 Lead TSSOP
14
Shipping Packaging
Tube
Tape & Reel
Temperature
0C to 70C
0C to 70C
Revision A April 20, 2016
843N252-45 Data Sheet
Revision History Sheet
Rev
A
A
Table
Page
3
Description of Change
Date
Supply Voltage, VCC. Rating changed from 4.5V min. to 3.63V per Errata NEN-11-03.
6/10/11
Removed ICS from the part number where needed.
Ordering information - Removed quantity from tape and reel. Deleted LF note below table.
Updated data sheet header and footer.
4/20/16
©2016 Integrated Device Technology, Inc
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Revision A April 20, 2016
843N252-45 Data Sheet
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Tech Support
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