843S1066CGLF

ICS843S1066 CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER General Description Features The ICS843S1066 is a high frequency clock generator and is a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS843S1066 uses an external 20MHz crystal to synthesize either 1066.67MHz or 1600MHz. The ICS843S1066 has excellent cycle-to-cycle and RMS period jitter performance. • • One differential LVPECL output • • • • • • Cycle-to-Cycle Jitter: 25ps (maximum) ICS The ICS843S1066 operates at 3.3V operating supply and is available in a fully RoHS compliant 8-lead TSSOP package. Crystal oscillator interface designed for 18pF, 20MHz parallel resonant crystal Period Jitter, RMS: 1.9ps (maximum) Output Duty Cycle: 48 – 52% Full 3.3V supply mode 0°C to 70°C ambient operating temperature Available in lead-free (RoHS 6) package Table 1. Frequency Table F_SEL Crystal Frequency (MHz) Multiplier Value Output Frequency (MHz) 0 20 53.3 1066.67 (default) 1 20 80 1600 Pin Assignment Block Diagram F_SEL Pulldown VCCA VEE XTAL_OUT XTAL_IN 20MHz XTAL_IN Q OSC PLL Multiplier 8 7 6 5 VCC Q nQ F_SEL ICS843S1066 8 Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View nQ XTAL_OUT IDT™ / ICS™ 3.3V LVPECL CLOCK SYNTHESIZER 1 2 3 4 1 ICS843S1066CG REV. A AUGUST 27, 2008 ICS843S1066 CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER Table 2. Pin Descriptions Number Name Type Description 1 VCCA Power Analog supply pin. 2 VEE Power Negative supply pin. 3, 4 XTAL_OUT XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 5 F_SEL Input 6, 7 nQ, Q Output Differential output pair. LVPECL interface levels. 8 VCC Power Core supply pin. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 3. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC+ 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 115.2°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter VCC Core Supply Voltage VCCA Analog Supply Voltage IEE ICCA Minimum Typical Maximum Units 3.135 3.3 3.465 V VCC – 0.18 3.3 VCC V Power Supply Current 53 mA Analog Supply Current 18 mA IDT™ / ICS™ 3.3V LVPECL CLOCK SYNTHESIZER Test Conditions 2 ICS843S1066CG REV. A AUGUST 27, 2008 ICS843S1066 CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum VIH Input High Voltage VIL Input Low Voltage IIH Input High Current VCC = VIN = 3.465V IIL Input Low Current VCC = 3.465V, VIN = 0V Typical Maximum Units 2 VCC + 0.3 V -0.3 0.8 V 150 µA -10 µA Table 4C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter VOH Output High Current; NOTE 1 VOL Output Low Current; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCC – 1.3 VCC – 0.8 V VCC – 2.0 VCC – 1.6 V 0.6 1.0 V Maximum Units NOTE 1: Outputs terminated with 50Ω to VCC – 2V. Table 5. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental Frequency 20 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF AC Electrical Characteristics Table 6. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Parameter Symbol fOUT Output Frequency tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 tjit(per) Period Jitter; NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical Maximum Units F_SEL = 0 1066.67 MHz F_SEL = 1 1600 MHz 25 20% to 80% ps 1.9 ps 100 200 ps 48 52 % NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. IDT™ / ICS™ 3.3V LVPECL CLOCK SYNTHESIZER 3 ICS843S1066CG REV. A AUGUST 27, 2008 ICS843S1066 CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER Parameter Measurement Information 2V nQ Qx Q VCCA tcycle n ➤ VCC SCOPE ➤ tcycle n+1 ➤ ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles LVPECL nQx VEE -1.3V±0.165V 3.3V LVPECL Output Load AC Test Circuit Cycle-to-Cycle Jitter VOH VREF nQ 80% 80% VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements VSW I N G 20% 20% Q tR tF Histogram Reference Point Mean Period (Trigger Edge) (First edge after trigger) Period Jitter Output Rise/Fall Time nQ Q t PW t odc = PERIOD t PW x 100% t PERIOD Output Duty Cycle/Pulse Width/Period IDT™ / ICS™ 3.3V LVPECL CLOCK SYNTHESIZER 4 ICS843S1066CG REV. A AUGUST 27, 2008 ICS843S1066 CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. TheICS843S1066 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. 3.3V VCC .01µF 10Ω .01µF 10µF VCCA Figure 1. Power Supply Filtering Crystal Input Interface The ICS843S1066 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 20MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 14p X1 18pF Parallel Crystal XTAL_OUT C2 14p Figure 2. Crystal Input Interface IDT™ / ICS™ 3.3V LVPECL CLOCK SYNTHESIZER 5 ICS843S1066CG REV. A AUGUST 27, 2008 ICS843S1066 CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VCC impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. VCC R1 Ro 0.1µf 50Ω Rs XTAL_IN R2 Zo = Ro + Rs XTAL_OUT Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω 3.3V Zo = 50Ω 125Ω FIN FOUT 125Ω Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω Figure 4A. 3.3V LVPECL Output Termination IDT™ / ICS™ 3.3V LVPECL CLOCK SYNTHESIZER 84Ω Figure 4B. 3.3V LVPECL Output Termination 6 ICS843S1066CG REV. A AUGUST 27, 2008 ICS843S1066 CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER Schematic Example Figure 5 shows an example of the ICS843S1066 application schematic. In this example, the device is operated at VCC = 3.3V. The 18pF parallel resonant 20MHz crystal is used. The C1 = 14pF and C2 = 14pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Two examples of LVPECL termination are shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note. VCC VCC VCCA R1 10 C4 10uF VCC C5 0.01u U1 XTAL_OUT XTAL_IN 1 2 3 4 VCCA VEE XTAL_OUT XTAL_IN VCC Q nQ F_SEL 8 7 6 5 3.3V C3 0.01u Zo = 50 Ohm Q F_SEL + Zo = 50 Ohm - R4 82.5 VCC=3.3V R5 82.5 F p 8 1 20MHz C2 14pF R3 133 nQ ICS843S1066 X1 R2 133 C1 14pF Zo = 50 Ohm Logic Control Input Examples + Set Logic Input to '1' VCC RU1 1K Set Logic Input to '0' VCC Zo = 50 Ohm - RU2 Not Install To Logic Input pins RD1 Not Install R6 50 To Logic Input pins Optional Y-Termination RD2 1K R7 50 R8 50 Figure 5. ICS843S1066 Schematic Example IDT™ / ICS™ 3.3V LVPECL CLOCK SYNTHESIZER 7 ICS843S1066CG REV. A AUGUST 27, 2008 ICS843S1066 CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER Power Considerations This section provides information on power dissipation and junction temperature for the ICS843S1066. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843S1066 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 53mA = 183.6mW • Power (outputs)MAX = 32mW/Loaded Output pair Total Power_MAX (3.3V, with all outputs switching) = 183.65mW + 32mW = 215.6mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 115.2°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.216W * 115.2°C/W = 94.9°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board. Table 7. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT™ / ICS™ 3.3V LVPECL CLOCK SYNTHESIZER 0 1 2.5 115.2°C/W 110.9 108.8 8 ICS843S1066CG REV. A AUGUST 27, 2008 ICS843S1066 CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 6. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCC – 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.8V (VCC_MAX – VOH_MAX) = 0.8V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.6V (VCC_MAX – VOL_MAX) = 1.6V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 0.8V)/50Ω] * 0.8V = 19.2mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = [(2V – 1.6V)/50Ω] * 1.6V = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW IDT™ / ICS™ 3.3V LVPECL CLOCK SYNTHESIZER 9 ICS843S1066CG REV. A AUGUST 27, 2008 ICS843S1066 CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER Reliability Information Table 8. θJA vs. Air Flow Table for a 8 Lead TSSOP θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 115.2°C/W 110.9 108.8 Transistor Count The transistor count for ICS843S1066 is: 1023 Package Outline and Package Dimensions Package Outline - G Suffix for 8 Lead TSSOP Table 9. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT™ / ICS™ 3.3V LVPECL CLOCK SYNTHESIZER 10 ICS843S1066CG REV. A AUGUST 27, 2008 ICS843S1066 CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER Ordering Information Table 9. Ordering Information Part/Order Number 843S1066CGLF 843S1066CGLFT Marking 66CL 66CL Package “Lead-Free” 8 Lead TSSOP “Lead-Free” 8 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ 3.3V LVPECL CLOCK SYNTHESIZER 11 ICS843S1066CG REV. A AUGUST 27, 2008 ICS843S1066 CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER Contact Information: www.IDT.com www.IDT.com Sales Technical Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA