FemtoClock® Crystal-to-LVDS
Clock Generator
844008I-46
DATA SHEET
GENERAL DESCRIPTION
FEATURES
The 844008I-46 is a 10Gb Ethernet Clock Generator and a member
of the HiPerClocks™ family of high performance devices from
IDT. The 844008I-46 can synthesize 156.25MHz or 100MHz with
a 25MHz crystal. It has a total of 8 LVDS outputs. The 844008I-46
has excellent phase jitter performance and is packaged in a 32
Lead VFQFN package, making it ideal for use in systems with
limited board space.
• Eight differential LVDS outputs
• Crystal oscillator interface designed for 18pF parallel resonant
crystals
• Supports the following output frequencies:
156.25MHz or 100MHz
• VCO frequency: 625MHz or 600MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.45ps (typical)
• Full 2.5V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) packages
• For functional replacement part use 8T49N285
FREQUENCY SELECT FUNCTION TABLE
Input
XTAL Frequency
(MHz)
FREQ_SEL
FB Divider
Output Divider
VCO (MHz)
Output Frequency (MHz)
25
0
÷25
÷4
625
156.25 (default)
25
1
÷24
÷6
600
100
PIN ASSIGNMENT
BLOCK DIAGRAM
32 31 30 29 28 27 26 25
Q0
1
nQ0
2
GND
Q1
nQ1
FREQ_SEL Pulldown
VDDA
FB = ÷25 or ÷24
nQ0:nQ7
FREQ_SEL
8
Q0:Q7
nc
625MHz or
600MHz
÷4
or
÷6
VDD
VCO
nc
XTAL_OUT
Phase
Detector
XTAL_IN
8
OSC
GND
25MHz
XTAL_IN
XTAL_OUT
OE Pullup
VDDO
Q2
nQ2
3
ICS844008I-46
24
nc
23
OE
22
GND
32-Lead VFQFN
4
21
5mm x 5mm x 0.925mm pack5
20
age body
6
19
K Package
7
Top View
18
8
17
nQ7
Q7
VDDO
nQ6
Q6
1
Q5
nQ5
VDDO
Q4
nQ4
GND
Q3
844008I-46 REVISION A 11/6/15
nQ3
9 10 11 12 13 14 15 16
©2015 Integrated Device Technology, Inc.
844008I-46 DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2
Q0, nQ0
Output
Differential output pair. LVDS interface levels.
3, 11, 22, 32
GND
Power
Power supply ground.
4, 5
Q1, nQ1
Ouput
Differential output pair. LVDS interface levels.
6, 14, 19
VDDO
Power
Output supply pins.
7, 8
Q2, nQ2
Output
Differential output pair. LVDS interface levels.
9, 10
Q3, nQ3
Output
Differential output pair. LVDS interface levels.
12, 13
Q4, nQ4
Output
Differential output pair. LVDS interface levels.
15, 16
Q5, nQ5
Output
Differential output pair. LVDS interface levels.
17, 18
Q6, nQ6
Output
Differential output pair. LVDS interface levels.
20, 21
Q7, nQ7
Output
Differential output pair. LVDS interface levels.
23
OE
Input
24, 28, 29
nc
Unused
25
VDDA
Power
26
FREQ_SEL
Input
27
VDD
Power
Core supply pin.
30,
31
XTAL_IN,
XTAL_OUT
Input
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Pullup
Output enable pin. When LOW, outputs are disabled. When HIGH. outputs
are enabled. LVCMOS/LVTTL interface levels. See Table 3.
No connect.
Analog supply pin.
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
Minimum
Typical
4
Maximum
Units
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
RPULLUP
Input Pullup Resistor
51
kΩ
TABLE 3. OE FUNCTION TABLE
Inputs
OE
Outputs
Q[0:7]/nQ[0:7]
1
Enabled (default)
0
Hi-Z
FEMTOCLOCK™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
2
REVISION A 11/6/15
844008I-46 DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
Storage Temperature, TSTG
37°C/W (0 mps)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
VDDA
Analog Supply Voltage
VDD – 0.25
2.5
VDD
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
60
mA
IDDA
Analog Supply Current
25
mA
IDDO
Output Supply Current
140
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Maximum
Units
VIH
Input High Voltage
2
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input High Current
5
µA
150
µA
IIL
Input Low Current
Test Conditions
OE
FREQ_SEL
Minimum
Typical
VDD = VIN = 2.625
VDD = VIN = 2.625
OE
VDD = 2.625V, VIN = 0V
-150
µA
FREQ_SEL
VDD = 2.625V, VIN = 0V
-5
µA
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VOD
Differential Output Voltage
Δ VOD
VOD Magnitude Change
VOS
Offset Voltage
Δ VOS
VOS Magnitude Change
REVISION A 11/6/15
Test Conditions
3
Minimum
Typical
Maximum
Units
247
340
454
mV
50
mV
1.10
1.25
1.375
V
50
mV
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
844008I-46 DATA SHEET
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
300
µW
Maximum
Units
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
tsk(o)
Output Skew; NOTE 1, 2
tjit(cc)
Cycle-to-Cycle Jitter
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
Typical
FREQ_SEL = 0
156.25
MHz
FREQ_SEL = 1
100
MHz
75
ps
20
ps
156.25MHz (1.875MHz - 20MHz)
0.45
ps
100MHz (1.875MHz - 20MHz)
0.52
ps
20% to 80%
300
700
ps
48
52
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
FEMTOCLOCK™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
4
REVISION A 11/6/15
844008I-46 DATA SHEET
➤
TYPICAL PHASE NOISE AT 156.25MHZ
Ethernet Filter
156.25MHz
Raw Phase Noise Data
➤
➤
NOISE POWER dBc
Hz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.45ps (typical)
Phase Noise Result by adding
Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
➤
TYPICAL PHASE NOISE AT 100MHZ
10Gb Ethernet Filter
100MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.52ps (typical)
Raw Phase Noise Data
➤
➤
Phase Noise Result by adding a
10Gb Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
REVISION A 11/6/15
5
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
844008I-46 DATA SHEET
PARAMETER MEASUREMENT INFORMATION
2.5V LVDS OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
CYCLE-TO-CYCLE JITTER
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
FEMTOCLOCK™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
6
REVISION A 11/6/15
844008I-46 DATA SHEET
PARAMETER MEASUREMENT INFORMATION, CONTINUED
OFFSET VOLTAGE SETUP
DIFFERENTIAL OUTPUT VOLTAGE SETUP
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 844008I-46
provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and
V DDO should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be
used for each pin. Figure 1 illustrates this for a generic VCC pin
and also shows that VDDA requires that an additional 10Ω resistor
along with a 10µF bypass capacitor be connected to the VDDA pin.
REVISION A 11/6/15
FIGURE 1. POWER SUPPLY FILTERING
7
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
844008I-46 DATA SHEET
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
LVDS OUTPUTS
All unused LVDS output pairs can be either left floating or terminated
with 100Ω across. If they are left floating, there should be no trace
attached.
CRYSTAL INPUT INTERFACE
Figure 2 below were determined using a 25MHz parallel
resonant crystal and were chosen to minimize the ppm error.
The 844008I-46 has been characterized with an 18pF
parallel resonant crystals. The capacitor values shown in
XTAL_IN
C1
27pF
X1
18pF Parallel Crystal
XTAL_OUT
C2
27pF
FIGURE 2. CRYSTAL INPUt INTERFACE
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it
is recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be done
in one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1 and
R2 can be 100Ω. This can also be accomplished by removing R1
and making R2 50Ω.
VDD
VDD
R1
Ro
Rs
.1uf
Zo = 50
Zo = Ro + Rs
XTAL_IN
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
FEMTOCLOCK™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
8
REVISION A 11/6/15
844008I-46 DATA SHEET
VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on
the package, as shown in Figure 4. The solderable area on the PCB,
as defined by the solder mask, should be at least the same size/
shape as the exposed pad/slug area on the package to maximize
the thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
specific and dependent upon the package power dissipation as well
as electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern.
It is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This
is desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used as a
guideline only. For further information, refer to the Application Note
on the Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadfame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern
must be connected to ground through these vias. The vias act as
“heat pipes”. The number of vias (i.e. “heat pipes”) are application
FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
2.5V LVDS DRIVER TERMINATION
Figure 5 shows a typical termination for LVDS driver in characteristic
impedance of 100Ω differential (50Ω single) transmission line
environment.
2.5V
2.5V
LVDS_Driv er
+
R1
100
-
100ΩDifferential
Differential Transmission
Transmission Line
100 Ohm
Line
FIGURE 5. TYPICAL LVDS DRIVER TERMINATION
REVISION A 11/6/15
9
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
844008I-46 DATA SHEET
SCHEMATIC LAYOUT
for frequency accuracy. For different board layout, the C1
and C2 may be slightly adjusted for optimizing frequency
accuracy. Two examples of LVDS for receiver without built-in
termination are shown in this schematic.
Figure 6 shows an example of 844008I-46 application
schematic. In this example, the device is operated at
VDD = VDDO = 3.3V. The 18pF parallel resonant 25MHz crystal
is used. The C1 = 27pF and C2 = 27pF are recommended
VDD
C5
0.1uF
VDD
VDDA
X1
25MHz
18pF
C2
27pF
C3
0.01u
GND
FREQ_SEL
C4
10uF
R1
10
Q7
Zo = 50 Ohm
C1
27pF
U1
Q0
nQ0
1
2
3
4
5
6
7
8
Q1
nQ1
Q2
nQ2
nc
OE
GND
nQ7
Q7
VDDO
nQ6
Q6
24
23
22
21
20
19
18
17
-
nQ7
Q7
nQ6
Q6
VDDO
C6
0.1uF
VDD= VDDO=3.3V
Q5
nQ5
Q4
nQ4
Q3
nQ3
ICS844008I-46
Zo = 50 Ohm
OE
Q3
nQ3
GND
Q4
nQ4
VDDO
Q5
nQ5
C7
0.1uF
Q0
nQ0
GND
Q1
nQ1
VDDO
Q2
nQ2
nQ7
9
10
11
12
13
14
15
16
VDDO
GND
XTAL_OUT
XTAL_IN
nc
nc
VDD
FREQ_SEL
VDDA
32
31
30
29
28
27
26
25
+
R2
100
Q6
VDDO
Zo = 50 Ohm
Logic Control Input Examples
Set Logic
Input to
'1'
VDD
RU1
1K
Set Logic
Input to
'0'
VDD
R3
50
C8
0.1uF
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
nQ6
To Logic
Input
pins
RD2
1K
Zo = 50 Ohm
C9
0.1uF
R4
50
+
-
Alternate
LVDS
Termination
FIGURE 6. 844008I-46 SCHEMATIC LAYOUT
FEMTOCLOCK™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
10
REVISION A 11/6/15
844008I-46 DATA SHEET
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 844008I-46.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 844008I-46 is the sum of the core power plus the analog power plus the power dissipated in the
load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX + IDDO_MAX) = 2.625V * (60mA + 25mA + 140mA) = 590.625mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 37°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.591W * 37°C/W = 106.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the
type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 32-LEAD VFQFN, FORCED CONVECTION
θJA vs. Air Flow (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
REVISION A 11/6/15
0
1
2.5
37.0°C/W
32.4°C/W
29.0°C/W
11
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
844008I-46 DATA SHEET
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN
θJA vs. Air Flow (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
37.0°C/W
32.4°C/W
29.0°C/W
TRANSISTOR COUNT
The transistor count for 844008I-46 is: 2993
FEMTOCLOCK™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
12
REVISION A 11/6/15
844008I-46 DATA SHEET
PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 9 below.
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS (VHHD -2/ -4)
SYMBOL
Minimum
N
Maximum
32
A
0.80
1.0
A1
0
0.05
A3
b
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
8
NE
8
D, E
5.0 BASIC
D2, E2
3.0
3.3
L
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
REVISION A 11/6/15
13
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
844008I-46 DATA SHEET
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
844008AKI-46LF
ICS008AI46L
844008AKI-46LFT
ICS008AI46L
32 Lead “Lead-Free” VFQFN
Tray
-40°C to 85°C
32 Lead “Lead-Free” VFQFN
1000 Tape & Reel
-40°C to 85°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
FEMTOCLOCK™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
14
REVISION A 11/6/15
844008I-46 DATA SHEET
REVISION HISTORY SHEET
Rev
A
REVISION A 11/6/15
Table
Page
1
Description of Change
Product Discontinuation Notice - Last time buy expires November 2, 2016.
PDN# CQ-15-05
15
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
Date
11/6/15
Corporate Headquarters
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San Jose, California 95138
Sales
800-345-7015 or +408-284-8200
Fax: 408-284-2775
www.IDT.com
Technical Support
email: clocks@idt.com
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