PRELIMINARY
ICS844202-245
CRYSTAL-TO-LVDS PCI EXPRESS™
CLOCK SYNTHESIZER W/SPREAD SPECTRUM
GENERAL DESCRIPTION
FEATURES
The ICS844202-245 is a 2 output PCI Express™ clock
ICS
synthesizer optimized to generate low jitter PCIe
HiPerClockS™ reference clocks with or without spread spectrum
modulation and is a member of the HiPerClockS™
family of high performance clock solutions from IDT.
Spread type and amount can be configured via the SSC control
pins. Using a 25MHz, 18pF parallel resonant crystal, the device
will generate LVDS clocks at either 25MHz, 100MHz, 125MHz or
250MHz. The ICS844202-245 uses a low jitter VCO that easily
meets PCI Express jitter requirements and is packaged in a
32-pin VFQFN package.
• Two LVDS outputs at 25MHz, 100MHz, 125MHz or 250MHz
• Crystal oscillator interface, 25MHz, 18pF parallel resonant
crystal
• Supports the following output frequencies:
25MHz, 100MHz, 125MHz or 250MHz
• VCO range: 240MHz - 700MHz
• Supports SSC downspread at 0.50% and -0.75%,
centerspread at ±0.25% and no spread options
• Cycle-to-cycle jitter: 70ps (typical)
• Period jitter: 40ps (typical)
• Full 3.3V power supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
nQ1
Q1
VDDO
VDDA
GND
nQ0
GND
Q0
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
SSC1
7
18
nc
8
17
GND
5
nc
6
FSEL0
nc
GND
OE
Q1
XTAL_OUT
nQ0
9 10 11 12 13 14 15 16
XTAL_IN
÷2
nc
19
VDDO
OEB
11
nc
20
4
VDD
PLL Bypass
÷5
÷4
GND
21
nc
SSC0
240-700MHz
XTAL_OUT
00
01
10
22
3
FSEL1
OSC
VCO
nc
32-Lead VFQFN
5mm x 5mm x 0.75mm
package body
K Package
Top View
nc
Q0
Phase
Detector
ICS844202-245
2
OE Pullup
25MHz
nc
23
1
VDD
BLOCK DIAGRAM
XTAL_IN
24
VDD
nQ1
Feedback Divider
÷20
SSC[1:0] Pullup:Pullup
Default = 100MHz
FSEL[1:0] Pulldown:Pullup
2
Spread Spectrum
Control
2
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT ™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
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ICS844202BK-245 REV. A JULY 9, 2007
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CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Νυ μ β ε ρ
Number
Ναμ ε
Name
1, 2, 11
3, 4, 6, 8,
12, 18,
20, 21,
23, 24
5, 27
VDD
Power
nc
Unused
VDDO
Power
7
FSEL0
Input
9
10,
19
FSEL1
SSC0
SSC1
XTAL_IN,
XTAL_OUT
Input
13, 14
15
Τ
ψπ ε
Type
Core supply pins.
No connect.
Output supply pins.
Pullup
Input
Input
Output frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels.
Pulldown Output frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels.
Spread spectrum control pins. See Table 3B.
Pullup
LVCMOS/LVTTL interface levels.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
Pullup
XTAL_IN is the input. (PLL reference.)
Output enable pin. Logic HIgh, outputs are enabled.
Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels.
Input
OE
Δ ε σχριπ τιο ν
Description
16, 17,
22. 29.
30
25, 26
GND
Power
Power supply ground.
nQ1, Q1
Output
Differential output pair. LVDS interface levels.
28
VDDA
Power
Analog supply pin.
31, 32
nQ0, Q0
Output
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
4
pF
RPULLUP
Input Pulllup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
TABLE 3A. FSEL[1:0] FUNCTION TABLE
Input
Minimum
Typical
Maximum
Units
TABLE 3B. SSC[1:0] FUNCTION TABLE
Input
Outputs
Spread %
FSEL1
FSEL0
Q0:1/nQ0:1
SSC1
SSC0
0
0
PLL Bypass (25MHz)
0
0
0
1
100MHz (default)
0
1
Down -0.5
1
0
125MHz
1
0
Down -0.75
1
1
250MHz
1
1
No Spread (default)
IDT ™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
2
Center ± -0.25
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CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, θJA 42.4°C/W (0 mps)
-65°C to 150°C
Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
VDD – 0.12
3.3
VDD
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
83
mA
IDDA
Analog Supply Current
12
mA
IDDO
Output Supply Current
26
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VIH
Parameter
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum Typical
2
Maximum
VDD + 0.3
Units
V
0.8
V
VDD = VIN = 3.465V
150
µA
VDD = VIN = 3.465V
5
µA
-0.3
FSEL1
SSC0, SSC1,
FSEL0, OE
FSEL1
SSC0, SSC1,
FSEL0, OE
VDD = 3.465V, VIN = 0V
-5
µA
VDD = 3.465V, VIN = 0V
-150
µA
TABLE 4C. LVDS DC CHARACTERISTICS, DD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
VOD
Differential Output Voltage
350
mV
Δ VOD
VOD Magnitude Change
50
mV
VOS
Offset Voltage
1.33
V
Δ VOS
VOS Magnitude Change
50
mV
IDT ™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
3
Minimum
Typical
Maximum
Units
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CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
Frequency
25
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
MHz
TBD
Ω
7
pF
100
µW
Maximum
Units
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
fOUT
tjit(per)
t j it(cc)
Test Conditions
Minimum
Output Frequency
Period Jitter, RMS
Cycle-to-Cycle Jitter; NOTE 1, 2
tsk(o)
Output Skew; NOTE 2, 3
Fxtal
Crystal Input Range; NOTE 1
Typical
25
MHz
125
MHz
100
MHz
250
MHz
25MHz
35
ps
100MHz
45
ps
125MHz
40
ps
250MHz
40
ps
25MHz
60
ps
100MHz
70
ps
125MHz
60
ps
250MHz
70
ps
40
12
25
ps
35
MHz
FM
SSC Modulation Frequency; NOTE 4
TBD
kHz
F MF
SSC Modulation Factor; NOTE 4
TBD
%
SSCred
Spectral Reduction; NOTE 5
11
dB
tSTABLE
Power-up to Stable Clock Output
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
10
20% - 80%
ms
525
ps
50
%
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Only valid within the VCO operating range.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Spread Spectrum clocking enabled.
IDT ™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
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PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
VOH
VREF
SCOPE
3.3V±10%
POWER SUPPLY
+ Float GND –
VDD,
VDDO
Qx
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
VDDA
LVDS
nQx
Histogram
Reference Point
Mean Period
(Trigger Edge)
(First edge after trigger)
PERIOD JITTER
nQx
nQ0, nQ1
Qx
Q0, Q1
➤
nQy
➤
3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT
➤
tcycle n
tcycle n+1
➤
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
Qy
tsk(o)
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
nQ0, nQ1
80%
80%
Q0, Q1
VOD
Clock
Outputs
t PW
20%
20%
tR
t
tF
odc =
PERIOD
t PW
x 100%
t PERIOD
OUTPUT RISE/FALL TIME
IDT ™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844204-245 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V DD, V DDA and
V DDO should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance, power
supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VDDA.
3.3V
VDD
.01μF
10Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
were determined using a 25MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
The ICS844204-245 has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2 below
XTAL_OUT
C1
27p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
FIGURE 2. CRYSTAL INPUt INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
INPUTS:
LVDS OUTPUTS
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there should
be no trace attached.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT ™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
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CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
LVCMOS TO XTAL INTERFACE
(Ro) plus the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the crystal
input will attenuate the signal in half. This can be done in one
of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by
removing R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface
diagram is shown in Figure 3. The XTAL_OUT pin can be left
floating. The input edge rate can be as slow as 10ns. For
LVCMOS inputs, it is recommended that the amplitude be
reduced from full swing to half swing in order to prevent signal
interference with the power rail and to reduce noise. This
configuration requires that the output impedance of the driver
VDD
VCC
VDD
VCC
R1
Ro
.1uf
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER
TO
XTAL INPUT INTERFACE
THERMAL RELEASE PATH
The expose metal pad provides heat transfer from the device to
the P.C. board. The expose metal pad is ground pad connected
to ground plane through thermal via. The exposed pad on the
device to the exposed metal pad on the PCB is contacted through
PIN
PIN PAD
SOLDER
solder as shown in Figure 4. For further information, please refer
to the Application Note on Surface Mount Assembly of Amkor’s
Thermally /Electrically Enhance Leadframe Base Package, Amkor
Technology.
SOLDER
EPAD
GROUND PLANE
EXPOSED METAL PAD
THERMAL VIA
FIGURE 4. P.C. BOARD
PIN
FOR
IDT ™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
PIN PAD
(GROUND PAD)
EXPOSED PAD THERMAL RELEASE PATH EXAMPLE
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PRELIMINARY
3.3V LVDS DRIVER TERMINATION
input. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the un-used outputs.
A general LVDS interface is shown in Figure 5. In a 100Ω
differential transmission line environment, LVDS drivers require
a matched load termination of 100Ω across near the receiver
3.3V
3.3V
LVDS
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 5. TYPICAL LVDS DRIVER TERMINATION
IDT ™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
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CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844202-245.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844202-245 is the sum of the core power plus the analog power plus the power dissipated in
the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.645V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX + IDDO_MAX) = 2.465V * (83mA + 12mA + 26mA) = 121mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 42.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.121W * 42.4°C/W = 75.1°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA
FOR
32-LEAD VFQFN, FORCED CONVECTION
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
IDT ™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
0
1
2.5
42.4°C/W
37.0°C/W
33.2°C/W
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PRELIMINARY
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
32 LEAD VFQFN
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
42.4°C/W
37.0°C/W
33.2°C/W
TRANSISTOR COUNT
The transistor count for ICS844202-245 is: 4715
IDT ™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
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CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
VHHD-2
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
A
0.80
--
1.00
A1
0
--
0.05
0.25 Ref.
A3
b
0.18
0.25
0.30
ND
8
NE
8
5.00 BASIC
D
D2
1.25
2.25
E2
1.25
2.25
3.25
0.50 BASIC
e
L
3.25
5.00 BASIC
E
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
IDT ™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
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PRELIMINARY
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS844202BK-245
TBD
32 Lead VFQFN
tray
0°C to 70°C
ICS844202BK-245T
TBD
32 Lead VFQFN
2500 tape & reel
0°C to 70°C
ICS844202BK-245LF
ICS402B245L
32 Lead "Lead-Free" VFQFN
tray
0°C to 70°C
ICS844202BK-245LFT
ICS402B245L
32 Lead "Lead-Free" VFQFN
2500 tape & reel
0°C to 70°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extneded temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT ™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
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ICS844202BK-245 REV. A JULY 9, 2007
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CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
800-345-7015
408-284-8200
Fax: 408-284-2775
netcom@idt.com
480-763-2056
Corporate Headquarters
Asia Pacific and Japan
Europe
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
England
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
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