8442BYLFT

700MHZ, CRYSTAL OSCILLATOR-TODIFFERENTIAL LVDS FREQUENCY SYNTHESIZER ICS8442B DATA SHEET GENERAL DESCRIPTION FEATURES The ICS8442B is a general purpose, dual output Crystal-toDifferential LVDS High Frequency Synthesizer . The ICS8442B has a selectable TEST_CLK or crystal input. The TEST_CLK input accepts LVCMOS or LVTTL input levels and translates them to LVDS levels. The VCO operates at a frequency range of 250MHz to 700MHz.The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallel interface to the configuration logic. The low phase noise characteristics of the ICS8442B makes it an ideal clock source for Gigabit Ethernet and Sonet applications. • Dual differential LVDS outputs • Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK • Output frequency range: 31.25MHz to 700MHz • Crystal input frequency range: 10MHz to 25MHz • VCO range: 250MHz to 700MHz • Parallel or serial interface for programming counter and output dividers • RMS period jitter: 2.7ps (typical) • Cycle-to-cycle jitter: 18ps (typical) • 3.3V supply voltage • 0°C to 85°C ambient operating temperature • Lead-Free package fully RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT XTAL_IN nP_LOAD M0 32 31 30 29 28 27 26 25 1 XTAL_OUT PLL ÷1 PHASE DETECTOR MR VCO ÷M 0 1 ÷2 ÷4 ÷8 22 XTAL_SEL M8 4 21 VDDA N0 5 20 S_LOAD N1 6 19 S_DATA nc 7 18 S_CLOCK GND 8 17 MR ICS8442 9 10 11 12 13 14 15 16 GND 1 3 nFOUT0 ICS8442BY REVISION A NOVEMBER 18, 2013 TEST_CLK M7 FOUT0 N0:N1 23 VDD M0:M8 XTAL_OUT 2 nFOUT1 TEST 24 M6 FOUT1 CONFIGURATION INTERFACE LOGIC 1 VDD FOUT0 nFOUT0 FOUT1 nFOUT1 M5 TEST S_LOAD S_DATA S_CLOCK nP_LOAD M1 OSC M2 0 XTAL_IN M3 M4 XTAL_SEL TEST_CLK VCO_SEL VCO_SEL ICS 8442B 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x M NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. The ICS8442B features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 10 ≤ M ≤ 28. The frequency out is defined as follows: FOUT = fVCO = fxtal x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-toLOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: T1 T0 TEST Output The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVDS output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS8442B support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N 0 0 LOW 0 1 S_Data, Shift Register Input 1 0 Output of M divider 1 1 CMOS FOUT SERIAL LOADING S_CLOCK T1 S_DATA t S_LOAD S T0 *NULL N1 N0 M8 M7 M6 M5 M4 M2 M1 M0 t H nP_LOAD t S PARALLEL LOADING M0:M8, N0:N1 M, N nP_LOAD t S t H S_LOAD Time FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: The NULL timing slot must be observed. ICS8442BY REVISION A NOVEMBER 18, 2013 M3 2 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name 1 2, 3, 4, 28, 29, 30, 31, 32 M5 M6, M7, M8, M0, M1, M2, M3, M4 5, 6 Type Input Description Pullup Input M divider inputs. Data latched on LOW-to-HIGH transistion Pulldown of nP_LOAD input. LVCMOS / LVTTL interface levels. N0, N1 Input Pulldown 7 nc Unused 8 , 16 GND Power 9 TEST Output 10, 13 VDD Power Determines output divider value as defined in Table 3C Function Table. LVCMOS / LVTTL interface levels. No connect. Power supply ground. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS / LVTTL interface levels. Core supply pins. 11, 12 FOUT1, nFOUT1 Output Differential output for the synthesizer. LVDS interface levels. 14, 15 FOUT0, nFOUT0 Output 17 MR Input Pulldown 18 S_CLOCK Input Pulldown 19 S_DATA Input Pulldown 20 S_LOAD Input Pulldown 21 VDDA Power 22 XTAL_SEL Input Pullup 23 TEST_CLK XTAL_IN, XTAL_OUT Input Pulldown Differential output for the synthesizer. LVDS interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inver ted outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not effect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels. Analog supply pin. Selects between cr ystal oscillator or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels. Test clock input. LVCMOS / LVTTL interface levels. Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. LVCMOS / LVTTL interface levels. 24, 25 Input 26 nP_LOAD Input Pulldown 27 VCO_SEL Input Pullup NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ICS8442BY REVISION A NOVEMBER 18, 2013 Test Conditions 3 Minimum Typical Maximum Units 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. When HIGH, forces the outputs to a differential LOW state (FOUTx = LOW and nFOUTx = HIGH), but does not effect loaded M, N, and T values. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L ↑ Data Data L X X L H X X L ↑ Data L H X X ↑ L Data L H X X ↓ L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. L H X X H ↑ Data Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don't care ↑ = Rising edge transition ↓ = Falling edge transition TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 10 0 0 0 0 0 1 0 1 0 275 11 0 0 0 0 0 1 0 1 1 • • • • • • • • • • • VCO Frequency (MHz) M Divide 250 • • • • • • • • • • • 650 26 0 0 0 0 1 1 0 1 0 675 27 0 0 0 0 1 1 0 1 1 700 28 0 0 0 0 1 1 1 0 NOTE 1: These M divide values and the resulting frequencies correspond to cr ystal or TEST_CLK input frequency of 25MHz. TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs N1 N0 0 0 N Divider Value 1 Output Frequency (MHz) Minimum Maximum 250 700 0 1 2 125 350 1 0 4 62.5 175 1 1 8 31.25 87.5 ICS8442BY REVISION A NOVEMBER 18, 2013 4 0 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 182 mA IDDA Analog Supply Current 16 mA Maximum Units 2 VDD + 0.3 V 2 VDD + 0.3 V -0.3 0.8 V -0.3 1.3 V VDD = VIN = 3.465V 150 µA VDD = VIN = 3.465V 5 TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 85°C Symbol Parameter VIH VIL I IH IIL Input High Voltage Input Low Voltage Input High Current Input Low Current Test Conditions M0-M8, N0, N1, MR, nP_LOAD, S_CLOCK, S_DATA, S_LOAD, XTAL_SEL, VCO_SEL TEST_CLK M0-M8, N0, N1, MR, nP_LOAD, S_CLOCK, S_DATA, S_LOAD, XTAL_SEL, VCO_SEL TEST_CLK M0-M4, M6-M8, N0, N1, MR, nP_LOAD, S_CLOCK, S_DATA, S_LOAD, M5, XTAL_SEL, VCO_SEL M0-M4, M6-M8, N0, N1, MR, nP_LOAD, S_CLOCK, S_DATA, S_LOAD, Minimum Typical VDD = 3.465V, -5 VIN = 0V VDD = 3.465V, VIN = 0V M5, XTAL_SEL, VCO_SEL µA -150 Output TEST; NOTE 1 2.6 High Voltage Output TEST; NOTE 1 VOL Low Voltage NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information section, "3.3V Output Load Test Circuit". V VOH 0.5 V TABLE 4C. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 85°C Symbol Parameter V OD Differential Output Voltage Δ V OD VOD Magnitude Change V OS Offset Voltage Δ V OS VOS Magnitude Change ICS8442BY REVISION A NOVEMBER 18, 2013 Test Conditions Minimum Typical Maximum Units 250 450 600 mV 50 mV 1.125 5 1.4 1.6 V 50 mV ICS8442B Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units TEST_CLK; NOTE 1 10 25 MHz XTAL_IN, XTAL_OUT; Input Frequency 10 25 MHz f IN NOTE 1 S_CLOCK 50 MHz NOTE 1: For the input crystal and TEST_CLK frequency range the M value must be set for the VCO to operate within the 250MHz to 700MHz range. Using the minimum input frequency of 10MHz valid values of M are 25 ≤ M ≤ 70. Using the maximum frequency of 25MHz valid values of M are 10 ≤ M ≤ 28. TABLE 6. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 10 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW TABLE 7. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 85°C Symbol Parameter Test Conditions FOUT Output Frequency tjit(cc) Cycle-to-Cycle Jitter ; NOTE 1, 3 tjit(per) Period Jitter, RMS; NOTE 1, 3 tsk(o) Output Skew; NOTE 2, 3 t R / tF Output Rise/Fall Time tS tH Setup Time Hold Time Minimum Typical 31.25 Maximum Units 700 MHz N = 1, 2 18 28 ps N=4 27 45 ps 2.7 20% to 80% 150 7 ps 15 ps 650 ps M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns odc Output Duty Cycle; NOTE 4 N>1 48 52 % tPW Output Pulse Width N=1 tPeriod/2 - 150 tPeriod/2 + 150 ps PLL Lock Time 1 ms tLOCK NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: In the Applications Section, please refer to the application note, "Differential Duty Cycle Improvement." ICS8442BY REVISION A NOVEMBER 18, 2013 6 ICS8442B Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION VDD VDD out SCOPE Qx + Float GND LVDS ➤ DC Input Power Supply LVDS - ➤ out nQx VOS/Δ VOS ➤ OFFSET VOLTAGE SETUP 3.3V OUTPUT LOAD TEST CIRCUIT VDD nFOUTx LVDS 100 FOUTx ➤ VOD/Δ VOD out nFOUTy ➤ DC Input ➤ out FOUTy tsk(o) DIFFERENTIAL OUTPUT VOLTAGE SETUP OUTPUT SKEW VOH nFOUT0, nFOUT1 VREF FOUT0, FOUT1 ➤ ➤ tcycle n tcycle n+1 ➤ VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements ➤ tjit(cc) = tcycle n – tcycle n+1 1000 Cycles Histogram Reference Point Mean Period (Trigger Edge) (First edge after trigger) Cycle-to-Cycle Jitter Period Jitter nFOUT0, nFOUT1 nFOUT0, nFOUT1 FOUT0, FOUT1 t PW 80% t 80% VOD PERIOD t PW odc = FOUT0, FOUT1 x 100% t PERIOD tR OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD ICS8442BY REVISION A NOVEMBER 18, 2013 20% 20% 7 tF ICS8442B Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER APPLICATION INFORMATION STORAGE AREA NETWORKS A variety of technologies are used for interconnection of the elements within a SAN. The tables below lists the common fre- quencies used as well as the settings for the ICS8442B to generate the appropriate frequency. Table 8. Common SANs Application Frequencies Interconnect Technology Gigabit Ethernet Fibre Channel Clock Rate Reference Frequency to SERDES (MHz) Crystal Frequency (MHz) 1.25 GHz 125, 250, 156.25 25, 19.53125 FC1 1.0625 GHz FC2 2.1250 GHz 106.25, 53.125, 132.8125 16.6015625, 25 2.5 GHz 125, 250 25 Infiniband Table 9. Configuration Details for SANs Applications Interconnect Technology Crystal Frequency (MHz) ICS8442B Output Frequency to SERDES (MHz) 25 125 0 0 0 0 1 0 1 0 25 250 0 0 0 0 1 0 1 25 156.25 0 0 0 0 1 1 19.53125 156.25 0 0 0 1 0 25 53.125 0 0 0 0 25 106.25 0 0 0 16.6015625 132.8125 0 0 25 125 0 25 250 0 ICS8442B M & N Settings M8 M7 M6 M5 M4 M3 M2 M1 M0 N1 N0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 Gigabit Ethernet Fiber Channel 1 Fiber Channel 2 Infiniband POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8442B provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA, should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, better power supply isolation is required. Figure 2 illustrates how a 10Ω along |with a 10μF and a .01μF bypass capacitor should be connected to each VDDA pin. ICS8442BY REVISION A NOVEMBER 18, 2013 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 2. POWER SUPPLY FILTERING 8 ICS8442B Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER CRYSTAL INPUT INTERFACE A crystal can be characterized for either series or parallel mode operation. The ICS8442B has a built-in crystal oscillator circuit. This interface can accept either a series or parallel crystal without additional components and generate frequencies with accuracy suitable for most applications. Additional accuracy can be achieved by adding two small capacitors C1 and C2 as shown in Figure 3. Typical results using parallel 18pF crystals are shown in Table 10. XTAL_IN C1 18p X1 18pF Parallel Crystal XTAL_OUT C2 22p Figure 3. CRYSTAL INPUt INTERFACE LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver in- put. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs. 3.3V Zo = 50 Ohm 3.3V LVDS_DRIVER CLK R1 100 nCLK HiPerClockS Zo = 50 Ohm Ω Differential Transmission Line 100Ω FIGURE 4. TYPICAL LVDS DRIVER TERMINATION DIFFERENTIAL DUTY CYCLE IMPROVEMENT The schematic below is recommended for applications using the ÷1 output configuration for improving the differential duty cycle. Vcc = 3.3V R2 1.3k R4 1.3k C1 Zo = 50 R1 100 + .1uf C2 Zo = 50 .1uf R3 800 LVDS Driv er R5 800 Receiv er_dif FIGURE 5. DIFFERENTIAL DUTY CYCLE IMPROVEMENT ICS8442BY REVISION A NOVEMBER 18, 2013 9 ICS8442B Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER LAYOUT GUIDELINE The schematic of the ICS8442B layout example used in this layout guideline is shown in Figure 6A. The ICS8442B recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. C1 C2 M5 M6 M7 M8 N0 N1 nc GND VDD ICS8442 C14 0.1u X_OUT T_CLK nXTAL_SEL VDDA S_LOAD S_DATA S_CLOCK MR TEST VDD FOUT1 nFOUT1 VDD FOUT0 nFOUT0 GND 1 2 3 4 5 6 7 8 9 10 FOUT1 11 nFOUT1 12 VDD 13 FOUT0 14 nFOUT0 15 16 U1 M4 M3 M2 M1 M0 VCO_SEL nP_LOAD X_IN 32 31 30 29 28 27 26 25 X1 C15 0.1u VDD 24 23 22 21 20 19 18 17 R7 10 VDDA C11 C16 10u 0.01u Zo = 50 Ohm + Zo = 50 Ohm R1 100 - Zo = 50 Ohm + Zo = 50 Ohm R2 100 FIGURE 6A. RECOMMENDED SCHEMATIC LAYOUT ICS8442BY REVISION A NOVEMBER 18, 2013 10 - 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND traces should be routed first and should be locked prior to routing other signal traces. • The traces with 50Ω transmission lines TL1 and TL2 at FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. GROUNDING Place the decoupling capacitors C14 and C15 as close as possible to the power pins. If space allows, placing the decoupling capacitor at the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. • Keep the clock trace on same layer. Whenever possible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power (ground) plane and the component power (ground) pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. If VDDA shares the same power supply with VDD, insert the RC filter R7, C11, and C16 in between. Place this RC filter as close to the VDDA as possible. CLOCK TRACES AND • Make sure no other signal trace is routed between the clock trace pair. TERMINATION The matching termination resistors R1 and R2 should be located as close to the receiver input pins as possible. Other termination scheme can also be used but is not shown in this example. The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal CRYSTAL The crystal X1 should be located as close as possible to the pins 24 (XTAL_OUT) and 25 (XTAL_IN). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. GND C1 C2 VDD X1 VIA U1 PIN 1 C16 C11 VDDA TL1N R7 C14 TL1 Close to the input pins of the receiver R1 Same requirement fo FOUT1/nFOUT1 TL1 C15 TL1N FIGURE 6B. PCB BOARD LAYOUT ICS8442BY REVISION A NOVEMBER 18, 2013 11 FOR For FOUT0/n FOUT0 output TL1, TL1N are 50 Ohm traces and equal length ICS8442 ICS8442B Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 10. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8442B is: 3662 ICS8442BY REVISION A NOVEMBER 18, 2013 12 ICS8442B Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 11. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. 0.80 BASIC e L 0.45 0.60 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 ICS8442BY REVISION A NOVEMBER 18, 2013 13 0.75 ICS8442B Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER TABLE 12. ORDERING INFORMATION Part/Order Number 8442BYLF 8442BYLFT Marking ICS8442BYLF ICS8442BYLF ICS8442BY REVISION A NOVEMBER 18, 2013 Package 32 lead "Lead Free" LQFP 32 lead "Lead Free" LQFP 14 Shipping Packaging Tray Tape and Reel Temperature 0°C to +85°C 0°C to +85°C ICS8442B Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev A Table Page T4A 5 T12 14 Description of Change Per PCN: N1308-01 Effective date 1/31/2014 Changed par t number from ICS8442 to ICS8442B throughout the datasheet. Power Supply DC Characteristics Table - changed IDD spec from 155mA max. to 182mA max; and changed IDDA spec from 20mA max. to 16mA max. Ordering Information Table - changed ordering information and marking revision from "A" to "B". Deleted leaded par t information. ICS8442BY REVISION A NOVEMBER 18, 2013 15 Date 11/18/13 ICS8442B Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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