844N234AKILF

FEMTOCLOCK® NG CRYSTAL-TO-LVDS CLOCK SYNTHESIZER ICS844N234I PRELIMINARY DATA SHEET General Description Features The ICS844N234I is a 4-output clock synthesizer designed for SRIO 1.3 and 2.0 reference clock applications. The device generates four copies of a selectable 100MHz, 312.5MHz, 156.25MHz or 125MHz clock signals with excellent phase jitter performance. The four outputs are organized in two banks of two LVDS ouputs.The device uses IDT’s fourth generation FemtoClock® NG technology for an optimum of high clock frequency and low phase noise performance, combined with low power consumption and high power supply noise rejection. The synthesized clock frequency and the phase-noise performance are optimized for driving SRIO 1.3 and 2.0 SerDes reference clocks. The device supports 3.3V and 2.5V voltage supplies and is packaged in a small, lead-free (RoHS 6) 32-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. • • 4TH generation FemtoClock® NG technology • • • Four differential LVDS clock outputs • RMS phase jitter @ 156.25MHz, using a 31.25MHz crystal (12kHz - 20MHz): 0.26ps (typical) • • • • LVCMOS interface levels for the frequency select input Selectable 100MHz, 312.5MHz, 156.25MHz or 125MHz output clock synthesized from a 31.25MHz fundamental mode crystal Selectable 31.25MHz crystal interface or external reference clock RMS phase jitter @ 156.25MHz, using a 31.25MHz crystal (1MHz - 20MHz): 0.15ps (typical) Full 3.3V or 2.5V supply voltage Lead-free (RoHS 6) 32-lead VFQFN package -40°C to 85°C ambient operating temperature Block Diagram XTAL_IN 0 OSC ÷NA 0 XTAL_OUT Pulldown REF_CLK 1 Pin Assignment 1 ÷80 ÷NB QA1 nQA1 QB0 nQB0 Pullup QB1 nQB1 2 Pulldown Pullup, Pulldown 2 Pullup Pullup nBYPASS VDDA FSELB1 FSELB0 FSELA1 FSELA0 OEB OEA VDD GND Pin Assignment ICS844N234I 32-lead VFQFN 5.0mm x 5.0mm x 0.925mm, package body K Package Top View GND nc nc nc nc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 VDDOB 1 2 3 4 5 6 7 8 VDD XTAL_IN XTAL_OUT REF_SEL REF_CLK MR Pulldown QB1 nQB1 QA0 nQA0 QA1 nQA1 GND QB0 nQB0 FemtoClock® NG VCO 1960-2550MHz Pulldown REF_SEL nBYPASS FSELA[1:0] FSELB[1:0] OEA OEB MR VDDOA PFD & LPF QA0 nQA0 The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.. ICS844N234AKILF FEBRUARY 8, 2012 1 ©2012 Integrated Device Technology, Inc. ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER Pin Description and Characteristics Table 1: Pin Descriptions Number Name Type Description 1 VDDOA Power Output supply pin for Bank A outputs. 2, 3 QA0, nQA0 Output Differential clock output. LVDS interface levels. 4, 5 QA1, nQA1 Output Differential clock output. LVDS interface levels. 6, 12, 17 GND Power Power supply ground. 7, 8 QB0, nQB0 Output Differential clock output. LVDS interface levels. 9, 10 QB1, nQB1 Output Differential clock output. LVDS interface levels. 11 VDDOB Power Output supply pin for Bank B outputs. 13, 14, 15, 16 nc Unused 18, 27 VDD Power 19 OEA Input Pullup Output enable input. See Table 3E: for function. LVCMOS/LVTTL interface levels. 20 OEB Input Pullup Output enable input. See Table 3F: for function. LVCMOS/LVTTL interface levels. 21, 22 FSELA0, FSELA1 Input Pulldown Frequency select pins. See Table 3A: for function. LVCMOS/LVTTL interface levels. 23 FSELB0, Input Pulldown Frequency select pin. See Table 3B: for function. LVCMOS/LVTTL interface levels. 24 FSELB1 Input Pullup Frequency select pin. See Table 3B: for function. LVCMOS/LVTTL interface levels. 25 VDDA Power 26 nBYPASS Input Pullup 28 MR Input Pulldown Master reset. See Table 3G: for function. LVCMOS/LVTTL interface levels. 29 REF_CLK Input Pulldown Alternative single-ended reference clock input. LVCMOS/LVTTL interface levels. 30 REF_SEL Input Pulldown Reference select input. See Table 3C: for function. LVCMOS/LVTTL interface levels. 31, 32 XTAL_OUT, XTAL_IN Input No connect. Core supply pins. Analog power supply. Bypass mode select pin. See Table 3D: for function. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. NOTE: Pulldown and Pullup refer to an internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2: Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 k RPULLUP Input Pullup Resistor 51 k ICS844N234AKILF FEBRUARY 8, 2012 Test Conditions 2 Minimum Typical Maximum Units ©2012 Integrated Device Technology, Inc. ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER Function Tables Table 3E: OEA Output Enable Function Table Input Table 3A: FSELA Output Frequency Selection Input Divider OEA Operation FSELA1 FSELA0 NA Output Frequency with fXTAL = 31.25MHz 0 QA0, nQA0 and QA1, nQA1 outputs are disabled (high-impedance) 0 (default) 0 (default) 25 100MHz 1 (default) QA0, nQA0 and QA1, nQA1 outputs are enabled 0 1 8 312.5MHz 1 0 16 156.25MHz 1 1 20 125MHz NOTE: OEA is an asynchronous control. Table 3F: OEB Output Enable Function Table Input NOTE: FSELA[1:0] are asynchronous controls. OEB Table 3B: FSELB Output Frequency Selection Input Divider Operation 0 QB0, nQB0 and QB1, nQB1 outputs are disabled (high-impedance) 1 (default) QB0, nQB0 and QB1, nQB1 outputs are enabled FSELB1 FSELB0 NB Output Frequency with fXTAL = 31.25MHz 0 0 25 100MHz 0 1 8 312.5MHz 1 (default) 0 (default) 16 156.25MHz Input 1 1 20 125MHz MR NOTE: OEB is an asynchronous control. Table 3G: MR Master Reset Function Table NOTE: FSELB[1:0] are asynchronous controls. 0 (default) Table 3C: PLL Reference Clock Select Function Table 1 Input Operation Internal dividers are enabled Internal dividers are reset and outputs are in logic low state (Qx = L, nQx = H) NOTE: MR is an asynchronous control. REF_SEL Operation 0 (default) The crystal interface is selected as reference clock 1 The REF_CLK input is selected as reference clock NOTE: REF_SEL is an asynchronous control. Table 3D: PLL BYPASS Function Table Input nBYPASS Operation 0 PLL is bypassed. The reference frequency fREF is divided by the selected output dividers NA and NB. AC specifications do not apply in PLL bypass mode. 1 (default) PLL is enabled. The reference frequency fREF is multiplied by the PLL feedback divider of 80 and then divided by the selected output dividers NA and NB. NOTE: nBYPASS is an asynchronous control. ICS844N234AKILF FEBRUARY 8, 2012 3 ©2012 Integrated Device Technology, Inc. ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.  These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond  those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for  extended periods may affect product reliability. Item Rating Supply Voltage, VDD 3.6V Inputs, VI XTAL_IN Other Inputs  0V to 2V 0.5V to VDD+ 0.5V Outputs, IO Continuous Current Surge Current  10mA 15mA Package Thermal Impedance, JA 33.1°C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A: Power Supply DC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C Symbol Parameter VDD Core Supply Voltage VDDA Analog Supply Voltage VDDOA, VDDOB Output Supply Voltage IDD Power Supply Current 130 mA IDDA Analog Supply Current 30 mA IDDOA + IDDOB Output Supply Current 110 mA ICS844N234AKILF FEBRUARY 8, 2012 Test Conditions 4 Minimum Typical Maximum Units 3.135 3.3V 3.465 V 2.375 2.5V 2.625 V VDD – 0.30 3.3V VDD V VDD – 0.30 2.5V VDD V 3.135 3.3V 3.465 V 2.375 2.5V 2.625 V ©2012 Integrated Device Technology, Inc. ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER Table 4B: LVCMOS/LVTTL Input DC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input  High Current Input  High Current Test Conditions Minimum VDD = 3.3V Typical Maximum Units 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V REF_CLK,  MR, REF_SEL, FSELA[1:0], FSELB0 VDD = VIN = 2.625V or 3.465V 150 µA OEA, OEB,  FSELB1, nBYPASS VDD = VIN = 2.625V or 3.465V 5 µA REF_CLK,  MR, REF_SEL, FSELA[1:0], FSELB0 VDD = 2.625V or 3.465V, VIN = 0V -5 µA OEA, OEB,  FSELB1, nBYPASS VDD = 2.625V or 3.465V, VIN = 0V -150 µA Table 4C: LVDS DC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage 335 mV VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.28 V VOS VOS Magnitude Change 50 mV Table 4D: LVDS DC Characteristics, VDD = VDDOA = VDDOB = 2.5V±5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage 330 mV VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.27 V VOS VOS Magnitude Change 50 mV Table 5: Crystal Characteristics Parameter Test Conditions Minimum Maximum Units 31.875 MHz Equivalent Series Resistance (ESR) 80  Shunt Capacitance 7 pF Mode of Oscillation Typical Fundamental Frequency 19.6 31.25 NOTE: Characterized using an 12pF parallel resonant crystal. ICS844N234AKILF FEBRUARY 8, 2012 5 ©2012 Integrated Device Technology, Inc. ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER Table 6: AC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C Symbol fOUT Parameter Test Conditions Typical Maximum Units FSELx[1:0] = 00 100 MHz FSELx[1:0] = 01 312.5 MHz FSELx[1:0] = 10 156.25 MHz FSELx[1:0] = 11 125 MHz Output Frequency fREF Reference Frequency tjit(Ø) RMS Phase Jitter (Random); NOTE 1 N Minimum REF_CLK 19.6 31.25 31.875 MHz 156.25MHz, Integration Range: 1MHz – 20MHz 0.15 ps 156.25MHz, Integration Range: 12kHz – 20MHz 0.26 ps 156.25MHz, Offset: 100Hz -95 dBc/Hz 156.25MHz, Offset: 1kHz -120 dBc/Hz 156.25MHz, Offset: 10kHz -130 dBc/Hz 156.25MHz, Offset: 100kHz -134 dBc/Hz Single-Side Band Noise Power tsk(o) Output Skew; NOTE 2, 3, 4 45 ps tsk(b) Bank Skew; NOTE 2, 4, 5 5 ps t R / tF Output Rise/Fall Time 290 ps tLOCK PLL Lock Time 5 ms QB[0:1], nQB[0:1] 50 % odc Output Duty Cycle QA[0:1], nQA[0:1] 50 % 20% to 80% NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Please refer to the phase noise plots. NOTE 2: fREF = 31.25MHz.  NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. ICS844N234AKILF FEBRUARY 8, 2012 6 ©2012 Integrated Device Technology, Inc. ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER Noise Power dBc Typical Phase Noise at 156.25MHz (1MHz - 20MHz) Offset Frequency (Hz) ICS844N234AKILF FEBRUARY 8, 2012 7 ©2012 Integrated Device Technology, Inc. ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER Noise Power dBc Hz Typical Phase Noise at 156.25MHz (12MHz - 20MHz) Offset Frequency (Hz) ICS844N234AKILF FEBRUARY 8, 2012 8 ©2012 Integrated Device Technology, Inc. ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER Parameter Measurement Information SCOPE 3.3V±5% POWER SUPPLY + Float GND – VDD, VDDOA, VDDOB VDDA SCOPE Qx 2.5V±5% POWER SUPPLY + Float GND – Qx VDD, VDDOA, VDDOB VDDA nQx nQx 3.3V LVDS Output Load AC Test Circuit 2.5V LVDS Output Load AC Test Circuit nQx nQX0 Qx QX0 nQy nQX1 Qy QX1 tsk(b) tsk(o) X = Bank A or Bank B Output Skew Bank Skew Phase Noise Plot QA[0:1], QB[0:1] Noise Power nQA[0:1], nQB[0:1] t PW t odc = PERIOD t PW x 100% t PERIOD f1 Offset Frequency f2 RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers Output Duty Cycle/Pulse Width/Period ICS844N234AKILF FEBRUARY 8, 2012 RMS Phase Jitter 9 ©2012 Integrated Device Technology, Inc. ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER Parameter Measurement Information, continued VDD 80% 80% out ➤ nQA[0:1], nQB[0:1] ➤ VOD DC Input 20% 20% LVDS 100 tF tR VOD/Δ VOD out ➤ QA[0:1], QB[0:1] Differential Output Voltage Setup Output Rise/Fall Time VDD out LVDS ➤ DC Input ➤ out VOS/Δ VOS ➤ Offset Voltage Setup ICS844N234AKILF FEBRUARY 8, 2012 10 ©2012 Integrated Device Technology, Inc. ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER Applications Information Interface to IDT SRIO Switches  The ICS844N234I is designed for driving the differential reference clock input (REF_CLK) of IDT’s SRIO 1.3 and 2.0 switch devices. The LVDS outputs of the ICS844N234I have the low-jitter, differential voltage and impedance characteristics required to provide a high-quality 156.25MHz clock signal for both SRIO 1.3 and 2.0 switch devices. Please refer to Figure 1 for suggested interfaces. In Figure 1, the AC-coupling capacitors are mandatory by the IDT SRIO switch devices. The differential REF_CLK_P/N input is internally re-biased and AC-terminated. Both interface circuits are optimized for 50 transmission lines and generate the voltage swing required to reliably drive the clock reference input of a IDT SRIO switch. Please refer to IDT’s SRIO device datasheet for more details. QAn LVDS nQAn Figure 1 shows the recommended interface circuit for driving the 156.25MHz reference clock of an IDT SRIO 2.0 switch by a LVDS output (QA0, QA1, QB0 or QB1) of the ICS844N234I. The LVDS-to-differential interface as shown in Figure 1 does not require any external termination resistors: the ICS844N234I driver contains an internal source termination at all outputs. The differential REF_CLK input contains an internal AC-termination (RL) and re-bias (VBIAS). Use the LVDS Driver Termination (figure 5A and 5B) if the receiving device does not implement and internal termination. REF_CLK_P   T=50     REF_CLK_N LI CI RL VBIAS LI + REF_CLK RL CI IDT SRIO 1.3, 2.0 Switch ICS844N234I Figure 1. LVDS-to-SRIO 2.0 Reference Clock Interface Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS844N234I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, VDDOA and VDDOB should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. ICS844N234AKILF FEBRUARY 8, 2012 3.3V or 2.5V VCC .01µF 10Ω .01µF 10µF VCCA Figure 2. Power Supply Filtering 11 ©2012 Integrated Device Technology, Inc. ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER Crystal Input Interface The ICS844N234I has been characterized with 12pF parallel resonant crystals. The capacitor values shown in Figure 3 below were determined using a 31.25MHz, 12pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 10pF X1 12pF Parallel Crystal XTAL_OUT C2 10pF Figure 3. Crystal Input Interface Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 4A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 4B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. 3.3V 3.3V R1 100 Ro ~ 7 Ohm C1 Zo = 50 Ohm XTAL_IN RS 43 R2 100 Driv er_LVCMOS 0.1uF XTAL_OUT Cry stal Input Interf ace Figure 4A. General Diagram for LVCMOS Driver to XTAL Input Interface VCC=3.3V C1 Zo = 50 Ohm XTAL_IN R1 50 Zo = 50 Ohm 0.1uF XTAL_OUT LVPECL Cry stal Input Interf ace R2 50 R3 50 Figure 4B. General Diagram for LVPECL Driver to XTAL Input Interface ICS844N234AKILF FEBRUARY 8, 2012 12 ©2012 Integrated Device Technology, Inc. ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER Recommendations for Unused Input and Output Pins Inputs: Outputs: Crystal Inputs LVDS Outputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached. REF_CLK Input For applications not requiring the use of a reference clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_CLK input to ground. LVCMOS Control Pins All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The LVDS Driver standard termination schematic as shown in Figure 5A can be used with either type of output structure. Figure 5B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. Z O • ZT ZT LVDS Receiver Figure 5A. Standard Termination LVDS Driver Z O • ZT C ZT 2 LVDS ZT Receiver 2 Figure 5B. Optional Termination ICS844N234AKILF FEBRUARY 8, 2012 13 ©2012 Integrated Device Technology, Inc. ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 6. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ICS844N234AKILF FEBRUARY 8, 2012 14 ©2012 Integrated Device Technology, Inc. ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER Power Considerations This section provides information on power dissipation and junction temperature for the ICS844N234I for all outputs that are configured to LVDS (LEV_SEL = 0). Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844N234I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. The maximum current at 85°C is as follows: IDD_MAX = 159mA IDDA_MAX = 34mA IDDO_MAX = 134mA • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (159mA + 34mA) = 668.745mW • Power (output)MAX = VDDO_MAX * (IDDOA + IDDOB) = 3.465V *134mA = 464.31mW Total Power_MAX = 668.745mW + 464.31mW = 1133.055mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 33.1°C/W per Table 7B below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 1.133W * 33.1°C/W = 122.5°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance JA for 56 Lead VFQFN, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS844N234AKILF FEBRUARY 8, 2012 0 1 2.5 33.1°C/W 28.1°C/W 25.4°C/W 15 ©2012 Integrated Device Technology, Inc. ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER Reliability Information Table 8. JA vs. Air Flow Table for a 32 lead VFQFN JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 3 33.1°C/W 28.1°C/W 25.4°C/W Transistor Count The transistor count for ICS844N234I is: 22,700 ICS844N234AKILF FEBRUARY 8, 2012 16 ©2012 Integrated Device Technology, Inc. ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER Package Outline and Package Dimensions Package Outline - K Suffix for 32 Lead VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area L A3 N N Anvil Anvil Singulation Singula tion e (Ty p.) 2 If N & N 1 are Even 2 OR E2 (N -1)x e (Re f.) E2 2 To p View b A (Ref.) D Chamfer 4x 0.6 x 0.6 max OPTIONAL N &N Odd 0. 08 Bottom View w/Type A ID C 4 D2 2 Th er mal Ba se D2 C Bottom View w/Type C ID 2 1 2 1 CHAMFER e N N-1 RADIUS 4 N N-1 There are 2 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) Table 9. Package Dimensions Reference Document: JEDEC Publication 95, MO-220 JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 ICS844N234AKILF FEBRUARY 8, 2012 The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8. 17 ©2012 Integrated Device Technology, Inc. ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER Ordering Information Table 10. Ordering Information Part/Order Number 844N234AKILF 844N234AKILFT Marking ICS4N234AIL ICS4N234AIL Package Lead-Free, 32 Lead VFQFN Lead-Free, 32 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS844N234AKILF FEBRUARY 8, 2012 18 ©2012 Integrated Device Technology, Inc. ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2012. All rights reserved.