844S42I
Dual Output RF Frequency Synthesizer
Data Sheet
General Description
Features
The 844S42I is a 3.3V compatible, PLL based clock synthesizer
targeted for clock generation in high-performance instrumentation,
networking and computing applications. Using either the serial (I2C)
or parallel programming interface, the 844S42I enables the
generation of clock frequencies in the range of 81MHz to 2592MHz.
The internal crystal oscillator uses the external quartz crystal as the
basis of its frequency reference. Alternatively, a LVCMOS compatible
clock signal can be used as PLL reference signal. The devices uses
an integer-N synthesizer architecture and is optimized for low-jitter
generation. The VCO within the PLL operates over a range of
1296MHz to 2592MHz. Its output is scaled by a divider that is
configured by either the I2C or parallel interfaces. The crystal
oscillator frequency fXTAL, the PLL pre-divider P, the feedback-divider
M and the PLL post-divider N determine the output frequency. The
feedback path of the PLL is internal.
•
Programmable frequency synthesis optimized for instrumentation,
networking and computing applications
•
•
81MHz to 2592MHz synthesized clock output signal
•
Output frequency programmable through 2-wire I2C bus or
parallel interface
•
•
•
•
•
•
•
•
•
•
On-chip crystal oscillator for reference frequency generation
The PLL post-dividers NA and NB are configured through either the
I2C or the parallel interfaces, each can provide one of seven division
ratios (1, 2, 3, 4, 6, 8, 16). This divider extends the performance of
the part while providing a typical 50% duty cycle. The high-frequency
outputs QA and QB are differential and are capable of driving a pair
of transmission lines. The positive supply voltage for the internal PLL
is separated from the power supply for the core logic and output
drivers to minimize noise induced jitter. The serial interface is I2C
compatible and provides read and write access to the internal PLL
configuration registers. The lock state of the PLL is indicated by the
LVCMOS-compatible LOCK_DT output. The 844S42I is packaged
in a 8mm x 8mm 56-lead VFQFN package.
Two differential, universal LVDS or LVPECL compatible
high-frequency outputs
Alternative LVCMOS/LVTTL compatible reference clock input
Clock stop and output enable functionality
PLL lock indicator output (LVCMOS/LVTTL)
LVCMOS/LVTTL compatible control inputs
Fully integrated PLL
SiGe Technology
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in a lead-free (RoHS 6) compliant package
Pin Assignment
nc
LOCK_DT
LEV_SEL
3
4
5
6
7
8
9
10
11
40
39
38
41
1
ICS844S42I
56-Lead VFQFN
8mm x 8mm x 0.925mm
package body
K Package
Top View
12
13
14
15 16 17 18 19 20 21 22 23 24 25 26 27 28
VDD
VDD
42
37
36
35
34
33
32
31
30
29
nc
VDDOA
VDDOA
QA
nQA
GND
GND
GND
GND
QB
nQB
VDDOB
VDDOB
nc
GND
VDD
REF_CLK
GND
REF_SEL
XTAL_IN
XTAL_OUT
nMR
1
2
GND
P
NA0
NA1
NA2
NB0
NB1
NB2
SDA
SCL
nPLOAD
nBYPASS
nc
VDD
©2016 Integrated Device Technology, Inc
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
ADR0
ADR1
VDDA
56 55 54 53 52 51 50 49 48 47 46 45 44 43
GND
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Revision A April 28, 2016
844S42I Data Sheet
Block Diagram
fQA
1
REF_CLK
XTAL_IN
0
OSC
1
PLL
÷P
fREF
fVCO
QA
÷NA
0
fPD
fQB
XTAL_OUT
REF_SEL
÷NB
QB
÷M
SDA
SCL
ADR[1:0]
nPLOAD
M[9:0]
NA[2:0]
NB[2:0]
P
LEV_SEL
nBYPASS
nMR
PLL
Configuration
Registers
LOCK_DT
I2C Control
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844S42I Data Sheet
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 7, 16, 27, 34,
35, 36, 37
GND
Power
2, 4, 29, 42, 43
nc
Unused
3
nBYPASS
Input
5, 14, 15, 28
VDD
Power
6
REF_CLK
Input
Pulldown
8
REF_SEL
Input
Pullup
9,
10
XTAL_IN
XTAL_OUT
11
nMR
Input
12
LOCK_DT
Output
13
LEV_SEL
Input
Pulldown
17
P
Input
Pullup
18, 19, 20
NA0, NA1, NA2
Input
Pulldown
Parallel configuration of QA output dividers.
LVCMOS/LVTTL interface levels.
21, 22, 23
NB0, NB1, NB2
Input
Pulldown
Parallel configuration of QB output dividers.
LVCMOS/LVTTL interface levels.
24
SDA
I/O
Pullup
I2C data input/output pin.LVCMOS/LVTTL interface levels.
25
SCL
I/O
Pullup
I2C clock.LVCMOS/LVTTL interface levels.
26
nPLOAD
Input
Pulldown
30, 31
VDDOB
Power
Bank B output power supply pins.
32, 33
nQB, QB
Output
QB differential clock output pair. LVPECL or LVDS interface levels.
38, 39
nQA, QA
Output
QA differential clock output pair. LVPECL or LVDS interface levels.
40, 41
VDDOA
Power
Bank A output power supply pins.
44, 48, 49,
50, 53
M0, M4, M5,
M6, M9
Input
Pullup
45, 46, 47,
51, 52
M1, M2, M3,
M7, M8
Input
Pulldown
54, 55
ADR0, ADR1
Input
Pulldown
56
VDDA
Power
Power supply ground.
Do not connect.
Pulldown
PLL bypass. LVCMOS/LVTTL interface levels.
Digital power supply pins.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Reference select pin. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Pullup
Master reset. nMR resets the I2C, output dividers and the LOCK_DT.
LVCMOS/LVTTL interface levels.
Lock detect output. LVCMOS/LVTTL interface levels.
Output level select (LVDS and LVPECL).
LVCMOS/LVTTL interface levels.
Parallel configuration of PLL pre-divider. LVCMOS/LVTTL interface levels.
Selects the programming interface. LVCMOS/LVTTL interface levels.
Parallel configuration of PLL feedback dividers.
LVCMOS/LVTTL interface levels.
Bits 2 and 1 of the device I2C address. LVCMOS/LVTTL interface levels.
Internal PLL power supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2016 Integrated Device Technology, Inc
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844S42I Data Sheet
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
2
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN Input Pulldown Resistor
51
k
ROUT
20
Output Impedance
Test Conditions
LOCK_DT
Minimum
Typical
Maximum
Units
Functional Description
The 844S42I is a programmable high-frequency clock source (clock
synthesizer). The internal PLL generates a high frequency output
signal based on a low-frequency reference signal. The frequency of
the output signal is programmable and can be changed on the fly for
frequency margining purpose. The internal crystal oscillator uses the
parallel-resonance external quartz crystal as the basis of its
frequency reference. Alternatively, an LVCMOS compatible clock
signal can be used as a PLL reference signal. The frequency of the
internal crystal oscillator is divided by a selectable divider and then
multiplied by the PLL. The internal oscillator within the PLL operates
over a range of 1296 MHz to 2592 MHz. Its output is scaled by two
independent dividers that are configured by either the I2C or parallel
interfaces. The crystal oscillator frequency fXTAL, the PLL pre-divider
P, the feedback-divider M, and the PLL post-dividers NA, NB
determine the output frequency. The feedback path of the PLL is
internal.
©2016 Integrated Device Technology, Inc
The PLL post-dividers NA and NB are configured through either the
I2C or the parallel interfaces, and each can provide one of seven
division ratios (1, 2, 3, 4, 6, 8, 16) and can stop the output clock in a
logic low state. The divider extends the performance of the part while
providing a typical 50% duty cycle. The high-frequency outputs, QA
and QB, are differential and are capable of driving a pair of
transmission lines. The differential outputs are configured as LVDS
or LVPECL by the control input LEV_SEL. The positive supply
voltage for the internal PLL is separated from the power supply for
the core logic and output drivers to minimize noise induced jitter.
The configuration logic has two sections: I2C and parallel. The
parallel interface uses the values at the M[9:0], NA[2:0], NB[2:0] and
P parallel inputs to configure the internal PLL dividers. The parallel
programming interface has priority over the serial I2C interface. The
serial interface is I2C compatible and provides read and write access
to the internal PLL configuration registers.The lock state of the PLL
is indicated by the LVCMOS-compatible LOCK_DT output.
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Revision A April 28, 2016
844S42I Data Sheet
Device Configuration
The output frequency may be changed at any time by changing the
value of the PLL feedback divider M. The smallest possible output
frequency change is the synthesizer granularity G (difference in fOUT
when incrementing or decrementing M). At a given reference
frequency, G is a function of the PLL pre-divider P and post-divider
N:
The ICS844S42I supports an output frequency range of 81MHz to
2592MHz. The output frequency fOUT is a function of the reference
frequency fREF and the three internal PLL dividers P, M, and N. fOUT
can be represented by this formula:
fOUT = (fREF ÷ P) · M ÷ (NA, NB)
The M, N and P dividers require a configuration by the user to
achieve the desired output frequency. The output dividers NA, NB
determine the achievable output frequency range (see Table 3A).
The PLL feedback-divider M is the frequency multiplication factor
and the main variable for frequency synthesis. For a given reference
frequency fREF, the PLL feedback-divider M must be configured to
match the specified VCO frequency range in order to achieve a valid
PLL configuration:
G = fREF ÷ (P · NA, NB)
The purpose of the PLL pre-divider P is to situate the PLL into the
specified VCO frequency range fVCO (in combination with M). For a
given output frequency, P = ÷4 results in a smaller output frequency
granularity G, P = ÷2 results a larger output frequency granularity G
and also decreases the PLL bandwidth compared to the P = ÷4
setting. The following example illustrates the output frequency range
of the 844S42I using a 16MHz reference frequency.
fVCO = (fREF ÷ P) · M and 1296MHz fVCO 2592MHz
Table 3A. Device Configuration Table for fREF = 16MHz)
Output Frequency (MHz)
NA, NB
1296 – 2592
1
648 – 1296
432 – 864
324 – 648
216 – 432
162 – 324
81 – 162
M
P
G (MHz)
324 – 648
4
4
162 – 324
2
8
324 – 648
4
2
162 – 324
2
4
324 – 648
4
1.33
162 – 324
2
2.66
324 – 648
4
1
162 – 324
2
2
324 – 648
4
0.66
162 – 324
2
1.33
324 – 648
4
0.5
162 – 324
2
1
324 – 648
4
0.25
162 – 324
2
0.5
2
3
4
6
8
16
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844S42I Data Sheet
Example Output Frequency Configuration
If a single reference frequency of 16MHz is available, an output
frequency at QA of 2500MHz and a small frequency granularity is
desired, the following steps would be taken to identify the
appropriate P, M, and N configuration:
4. Configure the 844S42I with the obtained settings:
1. Use Table 3A to select the output divider, NA, that matches the
desired output frequency or frequency range. According to Table 3A
a target output frequency of 2500MHz falls in the fOUT range of
1296MHz to 2592MHz and requires to set NA = 1.
•
M[9:0] = 1001110001b (binary number for M = 625)
•
NA[2:0] = 000 (÷1 divider, see Table 3C)
•
P = 1 (÷4 divider, see Table 3B)
•
NB[2:0] = 111 will stop (disable) the QB output
5. Use either parallel or serial interface to apply the setting.
The I2C configuration byte for this examples are:
0x00 = 01110001b, 0x01 = 10111000b and 0x02 = 10000000b. See
Table 3H for a register map.
2. Calculate the VCO frequency fVCO = fOUT · NA, which is 2500MHz
in this example.
3. Determine the PLL feedback divider: M = fVCO ÷ P. The smallest
possible output granularity in this example calculation is 4MHz (set P
= 4). M calculates to a value of 2500MHz ÷ 4 = 625MHz.
PLL Divider Configuration
Table 3B. Pre-Divider (P) Table
P
Pre-Divider P
Operation
0
2
fPD = fREF ÷ 2
1 (default)
4
fPD = fREF ÷ 4
Table 3C. Post-Divider (Nx) Table
NA, NB
2
1
0
Post-Divider
NA, NB
0 (default)
0 (default)
0 (default)
1
fQA, fQB = fVCO ÷ 1
0
0
1
2
fQA, fQB = fVCO ÷ 2
0
1
0
3
fQA, fQB = fVCO ÷ 3
0
1
1
6
fQA, fQB = fVCO ÷ 6
1
0
0
4
fQA, fQB = fVCO ÷ 4
1
0
1
8
fQA, fQB = fVCO ÷ 8
1
1
0
16
fQA, fQB = fVCO ÷ 16
1
1
1
N/A
Output stopped in logic low state
©2016 Integrated Device Technology, Inc
Operation
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Revision A April 28, 2016
844S42I Data Sheet
Programming the 844S42I
The 844S42I has a parallel and a serial configuration interface. The
purpose of the parallel interface is to directly configure the PLL
dividers through hardware pins without the overhead of a serial
protocol. At device startup, the device always obtains an initial PLL
frequency configuration through the parallel interface. The parallel
interface does not support reading the PLL configuration. The serial
interface is I2C compatible. It allows reading and writing devices
settings by accessing internal device registers. The serial interface is
designed for host-controller access to the synthesizer frequency
settings, for instance, in frequency-margining applications.
to logic low level. During nPLOAD = 0, any change of the logical
state of the P, M[9:0], NA[2:0] and NB[2:0] pins will immediately
affect the internal PLL divider settings, resulting in a change of the
internal VCO frequency and the output frequency. The parallel
interface mode disables the I2C write-access to the internal
registers; however, I2C read-access to the internal configuration
registers is enabled. Upon startup, when the device reset signal is
released (rising edge of the nMR signal), the device reads its startup
configuration through the parallel interface and independent of the
state of nPLOAD. It is recommended to provide a valid PLL
configuration for startup. If the parallel interface pins are left open, a
default PLL configuration will be loaded. After the low-to-high
transition of nPLOAD, the configuration pins have no more effect and
the configuration registers are made accessible through the serial
interface.
Using the Parallel Interface
The parallel interface supports write-access to the PLL frequency
setting directly through 17 configuration pins (P, M[9:0], NA[2:0], and
NB[2:0]). The parallel interface must be enabled by setting nPLOAD
Table 3D. PLL Feedback Divider (M) Configuration Table
M Bits
9
8
7
6
5
4
3
2
1
0
Pin
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
Default
1
0
0
1
1
1
0
0
0
1
Table 3E. PLL Post-Divider (NA) Configuration Table
NA Bits
2
1
0
Pin
NA2
NA1
NA0
Default
0
0
0
Table 3F. PLL Post-Divider (NB) Configuration Table
NB Bits
2
1
0
Pin
NB2
NB1
NB0
Default
0
0
0
Table 3G. PLL Pre-Divider (P) Configuration Table
P
Pin
P
Default
1
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Revision A April 28, 2016
844S42I Data Sheet
Using the I2C Interface
the 844S42I is still visible at the I2C interface and I2C transfers are
acknowledged by the device. Read-access to the internal registers
during nPLOAD = 0 (parallel programming mode) is supported. Note
that the device automatically obtains a configuration using the
parallel interface upon the release of the device reset (rising edge of
nMR) and independent on the state of nPLOAD. Changing the state
of the nPLOAD input is not supported when the device performs any
transactions on the I2C interface.
nPLOAD = 1 enables the programming and monitoring of the
internal registers through the I2C interface. Device register access
(write and read) is possible through the 2-wire interface using SDA
(configuration data) and SCL (configuration clock) signals. The
844S42I acts as a slave device at the I2C bus. For further information
on I2C it is recommended to refer to the I2C bus specification
(version 2.1).
nPLOAD = 0 disables the I2C-write-access to the configuration
registers and any data written into the register is ignored. However,
Programming Model and Register Set
Register Map
The synthesizer contains three fully accessible configuration
registers (0x00 through 0x02). Programming the synthesizer
frequency through the I2C interface is a one step process at which all
registers are written at once by a single I2C transaction. The PLL
frequency is affected as a result of the completion of the entire three
register file write access at the end of writing byte 0x02. The
configuration registers are read as a single I2C transaction. All
registers are read back-to-back. Note that the synthesizer does not
check any boundary conditions such as the VCO frequency range.
Writing the PLL registers could result in invalid VCO frequencies
(VCO frequency beyond lock range).
It is always required to configure the entire 844S42I register file
(0x00, 0x01, 0x02), addressing single register bytes is not
supported. Writing any information to the bits 2, 1 and 0 in register
0x02 is ignored. These bits indicate information updated by the
synthesizer (bit 2 is the PLL lock status, bits 1 and 0 are copies of the
ADR[1:0] pin status).
Table 3H. Register File Table
Register Address
7
6
5
4
3
2
1
0
Access
0x00H
M7
M6
M5
M4
M3
M2
M1
M0
R/W
Default
0
1
1
1
0
0
0
1
0x01H
M9
M8
NA2
NA1
NA0
NB2
NB1
NB0
Default
1
0
0
0
0
0
0
0
0x02H
P
RES
RES
RES
RES
LOCK
ADR1
ADR0
Default
1
0
0
0
0
0
0
0
R/W
R/W
I2C Register Access in Parallel Mode
The 844S42I supports the configuration of the synthesizer through
the parallel interface (nPLOAD = 0) and serial interface (nPLOAD =
1). Register contents and the divider configurations are not changed
when the user switches from parallel mode to serial mode. However,
when switching from serial mode to parallel mode, the PLL dividers
immediately reflect the logical state of the hardware pins M[9:0],
NA[2:0], NB[2:0], and P. Applications using the parallel interface to
obtain a PLL configuration can use the serial interface to verify the
©2016 Integrated Device Technology, Inc
divider settings. In parallel mode (nPLOAD = 0), the 844S42I allows
read-access to the registers through I2C (if nPLOAD = 0), the current
PLL configuration is stored in the registers. After changing from
parallel to serial mode (nPLOAD = 1), the last PLL configuration is
still stored in the registers. The user now has full write and read
access to both configuration registers through the I2C bus and can
change the configuration at any time.
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844S42I Data Sheet
Programming the I2C Interface
Table 3I. I2C Slave Address Table
Table 3K. nBYPASS Configuration Table
Bit
7
6
5
4
3
2
1
0
Value
1
0
1
1
0
ADR1
ADR0
R/W
The 844S42I acts as a slave device at the I2C bus. The register file
is reset to its default values at power-up by an integrated power-on
reset circuit or by applying an external device reset signal (nMR).The
7-bit I2C slave address of the 844S42I synthesizer is a combination
of a 5-bit fixed addresses and two variable bits which are set by the
hardware pins ADR[1:0]. Bit 0 of the 844S42I slave address is used
by the bus controller to select either the read or write mode. ‘0’
indicates a transmission (I2C-WRITE) to the 844S42I. “1” indicates a
request for data (I2C-READ) from the synthesizer. The hardware
pins ADR1 and ADR0 and should be individually set by the user to
avoid address conflicts of multiple 844S42I devices on the same I2C
bus.
nBYPASS
Operation
0 (default)
fQA, fQB = ((fREF ÷ P) * M) ÷ NA, NB
PLL operation
1
fQA, fQB = fREF ÷ NA, NB
PLL is bypassed, AC specifications do not apply
The nBYPASS control should be set to logic LOW for normal
operation. nBYPASS = 1 enables the PLL bypass mode for factory
test. In PLL bypass mode, the output frequency is equal to the input
frequency divided by NA, NB and frequency multiplication is
disabled.
Table 3L. nMR Configuration Table
nMR
Each access to the I2C register file must read or write the entire four
register bytes at one time. Each transfer starts with register 0x00H,
followed by register 0x01H, until register 0x02H. Addressing
individual bytes is not supported. The bytes will program internal
part circuitry upon receipt of all three bytes and a given I2C bus
signal.
0
1 (default)
Operation
The device is reset and the default settings are
loaded into the I2C file (low to high transition of nMR)
Normal operation
The output type and output voltage levels of both outputs are
configured through the configuration input LEV_SEL. LEV_SEL
connected to logic high results in LVPECL output levels and
LEV_SEL connected to logic low results in LVDS output levels of
both QA and QB differential outputs.
Device Startup
General Device Configuration: It is recommended to reset the
844S42I after the system powers up. The device acquires an initial
PLL divider configuration through the parallel interface pins M[9:0],
NA[2:0], NB[2:0] and PNOTE1 with the low-to-high transition of
nMRNOTE2. PLL frequency lock is achieved within the specified lock
time (tLOCK) and is indicated by an assertion of the LOCK_DT signal
which completes the startup procedure. The output frequency can
be reconfigured at any time through either the parallel or the serial
interface.
Table 3M. LEV_SEL Configuration Table
LEV_SEL
Operation
0 (default)
QA, QB outputs are LVDS compatible
1
QA, QB outputs are LVPECL compatible
Starting-Up Using the Parallel Interface
The simplest way to use the 844S42I is through the parallel
interface. The serial interface pins (SDA, SDL, and ADR[1:0]) can be
left open and nPLOAD is set to logic low. After the release of nMR
and at any other time the PLL and output frequency configuration is
directly set to through the M[9:0], NA[2:0], NB[2:0] and P pins.
Table 3N. LOCK_DT Configuration Table
LOCK_DT
Operation
0
Device is not locked to the input reference clock
1
Device is locked to the input reference clock
Table 3J. REF_SEL Configuration Table
REF_SEL
0
1 (default)
Operation
Selects REF_CLK input as reference frequency
input
Selects the XTAL interface as reference frequency
NOTE 1: The parallel interface pins M[9:0], NA[2:0], NB[2:0] and P may be left open (floating). In this case the initial PLL configuration will have the default setting
of M = 625MHz, P = 1 (÷4), NA[2:0] = 000 (÷1), NB[2:0] = 000 (÷1), resulting in an internal VCO frequency of 2500MHz (fREF = 16MHz) and an output frequency
of 2500MHz at both outputs.
NOTE 2: The initial PLL configuration is independent on the selected programming mode (nPLOAD low or high).
©2016 Integrated Device Technology, Inc
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Revision A April 28, 2016
844S42I Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, IO (LVDS)
Continuos Current
Surge Current
10mA
15mA
Outputs, VO (LVCMOS)
-0.5V to VDDO + 0.5V
Package Thermal Impedance, JA
31.4°C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDOA = VDDOB = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VDD – 0.23
3.3
VDD
V
VDDOA,
VDDOB
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
LEV_SEL = 0
195
mA
IDDA
Analog Supply Current
LEV_SEL = 0
23
mA
IDDOA +
IDDOB
Output Supply Current
LEV_SEL = 0
52
mA
IGND
Power Supply Current
LEV_SEL = 1
275
mA
NOTE: Refer to the Power Considerations section. In LVDS output mode, the IDD, IDDA and IDDO specifications apply. IDDO is the current
through all VDDOA and VDDOB pins. In LVPECL mode, the IGND specification applies. IGND is the current through all GND pins.
©2016 Integrated Device Technology, Inc
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Revision A April 28, 2016
844S42I Data Sheet
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
Input High Current
Input Low Current
Test Conditions
Minimum
Typical
Maximum
Units
2.2
VDD + 0.3
V
-0.3
0.8
V
REF_CLK, nPLOAD,
LEV_SEL, ADR[1:0],
NA[0:2], NB[0:2], M1,
M2, M3, M7, M8,
nBYPASS
VDD = VIN = 3.465V
150
µA
M0, M4, M5, M6, M9,
P, nMR, SDA, SCL,
REF_SEL
VDD = VIN = 3.465V
10
µA
REF_CLK, nPLOAD,
LEV_SEL, ADR[1:0],
NA[0:2], NB[0:2], M1,
M2, M3, M7, M8,
nBYPASS
VDD = 3.465V, VIN = 0V
-10
µA
M0, M4, M5, M6, M9,
P, nMR, SDA, SCL,
REF_SEL
VDD = 3.465V, VIN = 0V
-150
µA
2.6
V
VOH
Output High Voltage
LOCK_DT
IOH = -12mA
VOL
Output Low Voltage
LOCK_DT
IOL = 12mA
0.5
V
Table 4C. LVDS DC Characteristics, VDD = VDDOA = VDDOB = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOD
Differential Output Voltage
LEV_SEL = 0
300
400
500
V
VOD
VOD Magnitude Change
LEV_SEL = 0
50
mV
VOS
Offset Voltage
LEV_SEL = 0
1.3
V
VOS
VOS Magnitude Change
LEV_SEL = 0
50
mV
Maximum
Units
1.1
1.2
Table 4D. LVPECL DC Characteristics, VDD = VDDOA = VDDOB = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
VOH
Typical
Output High Voltage; NOTE 1
LEV_SEL = 1
VDDOx – 1.2
VDDOx – 0.8
V
VOL
Output Low Voltage; NOTE 1
LEV_SEL = 1
VDDOx – 2.0
VDDOx – 1.4
V
VSWING
Peak-to-Peak Output Voltage Swing
LEV_SEL = 1
0.6
1
V
NOTE 1: Outputs termination with 50 to VDDOx – 2V.
©2016 Integrated Device Technology, Inc
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844S42I Data Sheet
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
Frequency
16
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = VDDOA = VDDOB = 3.3V ± 5%, TA = -40°C to +85°C
Symbol
Parameter
fREF
Input Reference Frequency
fVCO
VCO frequency range
fOUT
Test Conditions
QA, QB Output frequency
fQA= fQB
tsk(o)
Output Skew
NOTE 1, 2, 3
tjit(cc)
Cycle-to-Cycle Jitter
tjit(per)
RMS Period Jitter
tR / tF
odc
Output
Rise/Fall Time
Output Duty Cycle
fQA fQB
Minimum
Typical
Maximum
16
Units
MHz
1296
2592
MHz
NA, NB = ÷1
1296
2592
MHz
NA, NB = ÷2
648
1296
MHz
NA, NB = ÷3
432
864
MHz
NA, NB = ÷4
324
648
MHz
NA, NB = ÷6
216
432
MHz
NA, NB = ÷8
162
324
MHz
NA, NB = ÷16
81
162
MHz
NA, NB = ÷1
15
ps
NA, NB ÷1
25
ps
across QA and QB at
coincident edges,
NA, NB = ÷2 or ÷4
80
ps
across QA and QB at
coincident edges,
NA, NB = ÷4 or ÷8
35
ps
25
ps
fQA= fQB
fQA= fQB
f > 2GHz
3.4
ps rms
fQA= fQB
f 1GHz
3.0
ps rms
fQA= fQB
1GHz < f 2GHz
2.5
ps rms
LVDS, LVPECL
QA, QB
20% to 80%
60
220
ps
NA, NB = ÷1, LEV_SEL = 0
45
55
%
NA, NB = ÷1, LEV_SEL = 1
44
56
%
NA, NB = ÷2
46
54
%
NA, NB = ÷3
47
53
%
NA, NB = ÷4, ÷6, ÷8, ÷16
48
52
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between output at the same supply voltage and with equal load conditions. Measured from VDD/2 of the input to the
differential crossing point.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Other output divider combinations may yield much greater output skews.
©2016 Integrated Device Technology, Inc
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844S42I Data Sheet
Parameter Measurement Information
2V
2V
3.3V ±5%
VDD,
VDD,
VDDOA,
VDDOB V
Qx
VDDOA,
VDDOB, VDDA
DDA
SCOPE
nQx
GND
-1.3V±0.165V
3.3V LVDS Output Load AC Test Circuit
3.3V LVPECL Output Load AC Test Circuit
VOH
nQA, nQB
VREF
QA, QB
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Reference Point
(Trigger Edge)
tcycle n
tcycle n+1
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
Histogram
Mean Period
(First edge after trigger)
RMS Period Jitter
Cycle-to-Cycle Jitter
nQx
nQA, nQB
Qx
nQy
QA, QB
Qy
Output Skew
©2016 Integrated Device Technology, Inc
LVPECL Output Rise/Fall Time
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Revision A April 28, 2016
844S42I Data Sheet
Parameter Measurement Information, continued
nQA, nQB
nQA, nQB
80%
80%
QA, QB
VOD
QA, QB
20%
20%
tR
tF
LVDS Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
Offset Voltage Setup
Differential Output Voltage Setup
©2016 Integrated Device Technology, Inc
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844S42I Data Sheet
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 844S42I provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. VDD, VDDA, VDDOA and VDDOB should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10 resistor along with a 10F bypass
capacitor be connected to the VDDA pin.
3.3V
VDD
.01µF
10Ω
.01µF
10µF
VDDA
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVPECL Outputs
All control pins have internal pullups or pulldowns;
additional resistance is not required but can be added
for additional protection. A 1k resistor can be used.
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of
the differential output pair should either be left floating or
terminated.
Crystal Inputs
LVDS Outputs
For applications not requiring the use of the crystal
oscillator input, both XTAL_IN and XTAL_OUT can be
left floating. Though not required, but for additional
protection, a 1k resistor can be tied from XTAL_IN to
ground.
All unused LVDS output pairs can be either left floating
or terminated with 100 across. If they are left floating,
we recommend that there is no trace attached.
REF_CLK Input
For applications not requiring the use of the reference
clock, it can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from the
REF_CLK to ground.
©2016 Integrated Device Technology, Inc
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844S42I Data Sheet
Crystal Input Interface
The 844S42I has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 2 below
were determined using an 18pF parallel resonant crystal and were
chosen to minimize the ppm error. These same capacitor values will
tune any 18pF parallel resonant crystal over the frequency range and
other parameters specified in this data sheet. The optimum C1 and
C2 values can be slightly adjusted for different board layouts.
XTAL_IN
C1
22pF
X1
18pF Parallel Crystal
XTAL_OUT
C2
22pF
Figure 2. Crystal Input Interface
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100. This can also be
accomplished by removing R1 and making R2 50. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
3.3V
3.3V
R1
100
Ro ~ 7 Ohm
C1
Zo = 50 Ohm
XTAL_IN
RS
43
R2
100
Driv er_LVCMOS
0.1uF
XTAL_OUT
Cry stal Input Interf ace
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
VCC=3.3V
C1
Zo = 50 Ohm
XTAL_IN
R1
50
Zo = 50 Ohm
0.1uF
XTAL_OUT
LVPECL
Cry stal Input Interf ace
R2
50
R3
50
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
©2016 Integrated Device Technology, Inc
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Revision A April 28, 2016
844S42I Data Sheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 4. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
©2016 Integrated Device Technology, Inc
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844S42I Data Sheet
3.3V LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
LVDS
Driver
standard termination schematic as shown in Figure 5A can be used
with either type of output structure. Figure 5B, which can also be used
with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
ZO • ZT
ZT
LVDS
Receiver
Figure 5A. Standard Termination
LVDS
Driver
ZO • ZT
C
ZT
2 LVDS
ZT Receiver
2
Figure 5B. Optional Termination
Figure 5. Typical LVDS Driver Termination
©2016 Integrated Device Technology, Inc
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844S42I Data Sheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical
termination for LVPECL outputs. The two different
layouts mentioned are recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 6A and 6B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
Figure 6A. 3.3V LVPECL Output Termination
©2016 Integrated Device Technology, Inc
R2
84
Figure 6B. 3.3V LVPECL Output Termination
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Revision A April 28, 2016
844S42I Data Sheet
Schematic Example
Figure 7 shows an example of 844S42I application schematic. In this example, the device is operated at VDD = VDDOA = VDDOB = 3.3V. The
18pF parallel resonant 16MHz crystal is used. The C1 and C2 = 22pF and are recommended for frequency accuracy. For differential board
layouts, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Two examples of LVPECL terminations and one example
LVDS termination are shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note.
VDD
R1
10
AD R 1
AD R 0
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
VDDA
C3
10u
C4
0.01u
3.3V
R2
133
Q1
R3
133
Zo = 50 Ohm
R4
QA
33
56
55
54
53
52
51
50
49
48
47
46
45
44
43
Zo = 50
LVCMOS_Driv er
58
+
VD D A
AD R 1
AD R 0
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
nc
U1
PAD1
PAD4
61
Zo = 50 Ohm
-
nQA
GND
VDDOA
C1
22pF
XTAL_IN
XTAL_OUT
X1
nMR
LOCK_DT
LEV_SEL
16MHz, CL=18pF
C2
22pF
VDD
59
nc
VDDOA
VDDOA
QA
nQA
GND
GND
GND
GND
QB
nQB
VDDOB
VDDOB
nc
GND
nc
nBYPASS
nc
VDD
REF_CLK
GND
REF_SEL
XTAL_IN
XTAL_OUT
nMR
LOCK_DT
LEV_SEL
VDD
PAD2
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Logic Control Input Examples
PAD3
PAD
REF_CLK
GND
REF_SEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
42
41
40
39
38
37
36
35
34
33
32
31
30
29
R5
82.5
R6
82.5
LVPECL
Termination
VCC = VCCOA= VCCOB = 3.3V
VDDOB
60
Zo = 50 Ohm
QB
+
57
nBYPASS
VD D
GN D
P
N A0
N A1
N A2
N B0
N B1
N B2
SD A
SC L
nP LO A D
GN D
VD D
VDD
Zo = 50 Ohm
nQB
RD1
Not Install
VDD
nP LO A D
R7
50
RU2
Not Install
To Logic
Input
pins
-
VDD
RD2
1K
R10
SP
J1
R12
5 SDA
4
3
2
SCL
1
R11
SP
0
VDDOA
VDDOB
(U1:40)
R13
R9
50
Optional
Y-Termination
To Logic
Input
pins
R8
50
SD A
SC L
RU1
1K
VDD
Set Logic
Input to
'0'
VDD
N A0
N A1
N A2
N B0
N B1
N B2
Set Logic
Input to
'1'
VDD
(U1:41)
(U1:30)
(U1:31)
Zo = 50 Ohm
0
Q
C5
C6
0.1u
C7
0.1u
+
C8
0.1u
0.1u
Zo = 50 Ohm
nQ
R14
100
-
VDD
(U1:5) VDD
(U1:14)
C9
C10
0.1u
0.1u
(U1:15)
C11
0.1u
(U1:28)
LVDS
Termination_Option
C12
0.1u
Figure 7. 844S42I Schematic Example
©2016 Integrated Device Technology, Inc
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Revision A April 28, 2016
844S42I Data Sheet
Power Considerations – LVPECL Outputs
This section provides information on power dissipation and junction temperature for the 844S42I, for all outputs that are configured to LVPECL
(LEV_SEL = 1). Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 844S42I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VDD_MAX * IGND_MAX = 3.465V * 260mA = 900.9mW
•
Power (outputs)MAX = 36mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 36mW = 72mW
Total Power_MAX (3.465V, with all outputs switching) = 800.9mW + 72mW = 972.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 31.4°C/W per Table 7A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.973W * 31.4°C/W = 115.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7A. Thermal Resistance JA for 56 Lead VFQFN Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
©2016 Integrated Device Technology, Inc
0
1
2.5
31.4°C/W
27.5°C/W
24.6°C/W
21
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844S42I Data Sheet
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
LVPECL output driver circuit and termination are shown in Figure 8.
VDDO
Q1
VOUT
RL
50Ω
VDDO - 2V
Figure 8. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VDDO – 2V.
•
For logic high, VOUT = VOH_MAX = VDDO_MAX – 0.8V
(VDDO_MAX – VOH_MAX) = 0.8V
•
For logic low, VOUT = VOL_MAX = VDDO_MAX – 1.4V
(VDDO_MAX – VOL_MAX) = 1.4V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VDDO_MAX – 2V))/RL] * (VDDO_MAX – VOH_MAX) = [(2V – (VDDO_MAX – VOH_MAX))/RL] * (VDDO_MAX – VOH_MAX) =
[(2V – 0.8V)/50] * 0.8V = 19.2mW
Pd_L = [(VOL_MAX – (VDDO_MAX – 2V))/RL] * (VDDO_MAX – VOL_MAX) = [(2V – (VDDO_MAX – VOL_MAX))/RL] * (VDDO_MAX – VOL_MAX) =
[(2V – 1.4V)/50] * 1.4V = 16.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 36mW
©2016 Integrated Device Technology, Inc
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Revision A April 28, 2016
844S42I Data Sheet
Power Considerations – LVDS Outputs
This section provides information on power dissipation and junction temperature for the 844S42I for all outputs that are configured to LVDS
(LEV_SEL = 0). Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 844S42I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The
following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
The maximum current at 85°C is as follows:
IDD_MAX = 185mA
IDDA_MAX = 22mA
IDDO_MAX = 50mA
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (185mA + 22mA) = 717.255mW
•
Power (output)MAX = VDDO_MAX * (IDDOA + IDDOB) = 3.465V * 50mA = 173.25mW
Total Power_MAX = 717.255mW + 173.25mW = 890.505mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 31.4°C/W per Table 7B below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.891W * 31.4°C/W = 113°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7B. Thermal Resistance JA for 56 Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
©2016 Integrated Device Technology, Inc
0
1
2.5
31.4°C/W
27.5°C/W
24.6°C/W
23
Revision A April 28, 2016
Reliability Information
Table 8. JA vs. Air Flow Table for a 56 Lead VFQFN
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
Transistor Count
The transistor count for 844S42I is: 10,263
0
1
2.5
31.4°C/W
27.5°C/W
24.6°C/W
844S42I Data Sheet
Package Outline and Package Dimensions
Package Outline - K Suffix for 56 Lead VFQFN
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
A3
N
Anvil
Anvil
Singulation
Singula tion
or
OR
Sawn
Singulation
To p View
L
N
e (Ty p.)
2 If N & N
1
are Even
2
E2
(N -1)x e
(Re f.)
E2
2
b
A
(Ref.)
D
e
N &N
Odd
0. 08
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
C
Th er mal
Ba se
D2
2
D2
C
Bottom View w/Type A ID
Bottom View w/Type C ID
2
1
2
1
CHAMFER
4
RADIUS
N N-1
4
N N-1
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
Table 9. Package Dimensions
SPEC NON_JEDEC: VLLD-2/-5
All Dimensions in Millimeters
Symbol
Minimum
Maximum
E2
5.05
5.35
e
0.50 Basic
L
0.30
0.50
SPEC NON_JEDEC: VLLD-2/-5
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
56
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.30
14
ND & NE
D&E
8.00 Basic
D2
4.35
4.65
©2016 Integrated Device Technology, Inc
Reference Document: JEDEC Publication 95, MO-220
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 9.
25
Revision A April 28, 2016
844S42I Data Sheet
Ordering Information
Table 10. Ordering Information
Part/Order Number
844S42BKILF
844S42BKILFT
Marking
ICS844S42BKIL
ICS844S42BKIL
©2016 Integrated Device Technology, Inc
Package
“Lead-Free” 56 Lead VFQFN
“Lead-Free” 56 Lead VFQFN
26
Shipping Packaging
Tray
Tape & Reel
Temperature
-40C to +85C
-40C to +85C
Revision A April 28, 2016
844S42I Data Sheet
Revision History
Revision Date
April 28, 2016
Description of Change
▪ Removed ICS from part numbers where needed.
▪ Ordering Information - Remove quantity from Tape and Reel. Deleted LF note below table.
▪ Update data sheet headers and footers.
©2016 Integrated Device Technology, Inc
27
Revision A April 28, 2016
844S42I Data Sheet
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