FemtoClock® Crystal-to-CML Clock Generator
845252
Datasheet
General Description
Features
The 845252 is a 3.3V/2.5V CML clock generator designed for
Ethernet applications. The device synthesizes either a 50MHz,
62.5MHz, 100MHz, 125MHz, 156.25MHz, 250MHz or 312.5MHz
clock signal with excellent phase jitter performance. The clock signal
is distributed to two low-skew differential CML outputs. The device is
suitable for driving the reference clocks of Ethernet PHYs. The
device supports 3.3V and 2.5V voltage supply and is packaged in a
small, lead-free (RoHS 6) 32-lead VFQFN package. The extended
temperature range supports telecommunication, wireless
infrastructure and networking end equipment requirements. The
device is a member of the family of High Performance Clock
Solutions from IDT.
•
Clock generation of: 50MHz, 62.5MHz, 100MHz, 125MHz,
156.25MHz, 250MHz and 312.5MHz
•
•
Two differential CML clock output pairs
•
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 400fs (typical), 3.3V
Crystal interface designed for 25MHz,
18pF parallel resonant crystal
Offset
Noise Power
100Hz.................... -102.4 dBc/Hz
1kHz.................... -119.4 dBc/Hz
10kHz................... -124.8 dBc/Hz
100kHz................... -125.7 dBc/Hz
•
•
•
•
•
LVCMOS interface levels for the control inputs
Full 3.3V and 2.5V supply voltage
Available in lead-free (RoHS 6) 32 VFQFN package
-40°C to 85°C ambient operating temperature
For functional replacement part use 8T49N241
Block Diagram
OSC
0
0
XTAL_OUT
fREF
REF_CLK
Pulldown
REF_SEL
Pulldown
FBSEL
nBYPASS
FSEL1:0
nOE
Phase
Detector
1
VCO
490-680
MHz
1
÷2 (default),
÷4,
÷5,
÷10
Q1
nQ1
nc
FBSEL
nQ1
Q1
GND
nc
Q0
nQ0
nc
XTAL_IN
nc
Pin Assignment
32 31 30 29 28 27 26 25
nQ0
1
24
nc
Q0
2
23
nc
VDD
3
22
REF_SEL
21
FSEL1
5
20
FSEL0
Pulldown
nc
6
19
nc
Pullup
nc
7
18
VDD
nc
8
17
nc
nc
XTAL_IN
XTAL_OUT
10 11 12 13 14 15 16
GND
9
REF_CLK
Pulldown
nBYPASS
Pulldown, Pulldown
VDDA
4
nc
nc
nOE
÷20,
÷25 (default)
845252
32 lead VFQFN
5.0mm x 5.0mm x 0.925mm package body
K Package
Top View
©2016 Integrated Device Technology, Inc.
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Revision B, November 11, 2016
845252 Datasheet
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
nQ0, Q0
Output
Differential clock output pair. CML interface levels.
3, 18
VDD
Power
Core supply pins.
4
nOE
Input
5, 6, 7, 8, 9, 16,
17, 19, 23, 24,
25, 30, 31, 32
nc
Unused
10
VDDA
Power
11
nBYPASS
Input
Pullup
12
REF_CLK
Input
Pulldown
13, 29
GND
Power
14,
15
XTAL_OUT,
XTAL_IN
Input
20, 21
FSEL0, FSEL1
Input
Pulldown
Output frequency divider select enable pins. See Table 3C for function.
LVCMOS/LVTTL interface levels.
22
REF_SEL
Input
Pulldown
PLL reference clock select pin. See Table 3A for function.
LVCMOS/LVTTL interface levels.
26
FBSEL
Input
Pulldown
PLL feedback divider select pin. See Table 3B for function.
LVCMOS/LVTTL interface levels.
27, 28
nQ1, Q1
Output
Pulldown
Output enable pin. See Table 3E for function.
LVCMOS/LVTTL interface levels.
Do not connect.
Analog supply pin.
PLL bypass pin. See Table 3D for function.
LVCMOS/LVTTL interface levels.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Differential clock output pair. CML interface levels.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
k
RPULLUP
Input Pullup Resistor
51
k
©2016 Integrated Device Technology, Inc.
Test Conditions
2
Minimum
Typical
Maximum
Units
Revision B, November 11, 2016
845252 Datasheet
Function Tables
Table 3A. PLL Reference Clock Select Function Table
Input
REF_SEL
Operation
0 (default)
The crystal interface is the selected.
1
The REF_CLK input is the selected.
NOTE: REF_SEL is an asynchronous control.
Table 3B. PLL Feedback Select Function Table
Input
FBSEL
Operation
0 (default)
fVCO = fREF * 25
1
fVCO = fREF * 20
NOTE: FBSEL is an asynchronous control.
Table 3C. Output Divider Select Function Table
Input
Output Frequency fOUT with fREF = 25MHz
Operation
FBSEL = 0
FBSEL = 1
0 (default)
fOUT = fVCO ÷ 2
312.5MHz
250MHz
0
1
fOUT = fVCO ÷ 4
156.25MHz
125MHz
1
0
fOUT = fVCO ÷ 5
125MHz
100MHz
1
1
fOUT = fVCO ÷ 10
62.5MHz
50MHz
FSEL1
FSEL0
0 (default)
NOTE: FSEL[1:0] are asynchronous controls.
Table 3D. PLL nBYPASS Function Table
Input
nBYPASS
Operation
0
PLL is bypassed. The reference frequency fREF is divided by the selected
output divider. AC specifications do not apply in PLL bypass mode.
1 (default)
PLL is enabled. The reference frequency fREF is multiplied by the selected
feedback divider and then divided by the selected output divider.
NOTE: nBYPASS is an asynchronous control.
Table 3E. Output Enable Function Table
Input
nOE
0 (default)
1
Operation
Outputs enabled.
Outputs disabled (high-impedance).
NOTE: nOE is an asynchronous control.
©2016 Integrated Device Technology, Inc.
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Revision B, November 11, 2016
845252 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, JA
43.4°C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Analog Supply Voltage
IDD
IDDA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDD – 0.12
3.3
VDD
V
Power Supply Current
88
mA
Analog Supply Current
12
mA
Table 4B. Power Supply DC Characteristics, VDD = 2.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Analog Supply Voltage
IDD
IDDA
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
VDD – 0.11
2.5
VDD
V
Power Supply Current
84
mA
Analog Supply Current
11
mA
©2016 Integrated Device Technology, Inc.
Test Conditions
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Revision B, November 11, 2016
845252 Datasheet
Table 4C. LVCMOS/LVTTL Input DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input
High Current
IIL
Input
Low Current
Test Conditions
Minimum
VDD = 3.3V
Typical
Maximum
Units
2
VDD + 0.3
V
VDD = 2.5V
1.7
VDD + 0.3
V
VDD = 3.3V
-0.3
0.8
V
VDD = 2.5V
-0.3
0.7
V
FBSEL, nOE, FSEL[1:0],
REF_SEL, REF_CLK
VDD = VIN = 3.465V
150
µA
nBYPASS
VDD = VIN = 3.465V
5
µA
FBSEL, nOE, FSEL[1:0],
REF_SEL, REF_CLK
VDD = 3.465V or 2.625V,
VIN = 0V
-5
µA
nBYPASS
VDD = 3.465V or 2.625V,
VIN = 0V
-150
µA
Table 4D. CML DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
VOH
Output High Voltage
VOUT
Test Conditions
Minimum
Typical
Maximum
Units
VDD - 0.02
VDD - 0.01
VDD
V
Output Voltage Swing
325
400
600
mV
VDIFF_OUT Differential Output Voltage Swing
650
800
1200
mV
Typical
Maximum
Units
Table 5. Crystal Characteristics
Parameter
Test Conditions
Mode of Oscillation
Minimum
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
©2016 Integrated Device Technology, Inc.
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Revision B, November 11, 2016
845252 Datasheet
AC Characteristics
Table 6A. AC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C
Symbol
fOUT
Parameter
Output Frequency; NOTE 1
tsk(o)
Output Skew; NOTE 1, 2, 3
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 4
t R / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
Typical
Maximum
Units
FBSEL = 0, FSEL[1:0] = 00
312.5
MHz
FBSEL = 0, FSEL[1:0] = 01
156.25
MHz
FBSEL = 0, FSEL[1:0] = 10
125
MHz
FBSEL = 0, FSEL[1:0] = 11
62.5
MHz
FBSEL = 1, FSEL[1:0] = 00
250
MHz
FBSEL = 1, FSEL[1:0] = 01
125
MHz
FBSEL = 1, FSEL[1:0] = 10
100
MHz
FBSEL = 1, FSEL[1:0] = 11
50
MHz
60
ps
FSEL = 0, 125MHz,
Integration Range: 1.875MHz – 20MHz
400
fs
FSEL = 0, 156.25MHz,
Integration Range: 1.875MHz – 20MHz
408
fs
20% to 80%
300
850
ps
FBSEL[1:0] 10
48
52
%
FBSEL[1:0] = 10
46
54
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: fREF = 25 MHz.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Please refer to the phase noise plots.
Table 6B. AC Characteristics, VDD = 2.5V±5%, TA = -40°C to 85°C
Symbol
fOUT
Parameter
Output Frequency; NOTE 1
tsk(o)
Output Skew; NOTE 1, 2, 3
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 4
t R / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
Typical
Maximum
Units
FBSEL = 0, FSEL[1:0] = 00
312.5
MHz
FBSEL = 0, FSEL[1:0] = 01
156.25
MHz
FBSEL = 0, FSEL[1:0] = 10
125
MHz
FBSEL = 0, FSEL[1:0] = 11
62.5
MHz
FBSEL = 1, FSEL[1:0] = 00
250
MHz
FBSEL = 1, FSEL[1:0] = 01
125
MHz
FBSEL = 1, FSEL[1:0] = 10
100
MHz
FBSEL = 1, FSEL[1:0] = 11
50
MHz
60
ps
FSEL = 0, 125MHz,
Integration Range: 1.875MHz – 20MHz
406
fs
FSEL = 0, 156.25MHz,
Integration Range: 1.875MHz – 20MHz
441
fs
20% to 80%
300
850
ps
FBSEL[1:0] 10
48
52
%
FBSEL[1:0] = 10
46
54
%
For NOTES see Table 6A above.
©2016 Integrated Device Technology, Inc.
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Revision B, November 11, 2016
845252 Datasheet
Noise Power dBc
Hz
Typical Phase Noise at 125MHz (3.3V)
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc.
7
Revision B, November 11, 2016
845252 Datasheet
Noise Power dBc
Hz
Typical Phase Noise at 125MHz (2.5V)
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc.
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Revision B, November 11, 2016
845252 Datasheet
Parameter Measurement Information
0V
SCOPE
Power
Supply
SCOPE
0V
Qx
Qx
VDD
Power
Supply
CML Driver
GND
VDD
CML Driver
GND
-2.5V ± 5%
-3.3V ± 5%
3.3V CML Output Load AC Test Circuit
nQx
2.5V CML Output Load AC Test Circuit
nQx
Qx
nQy
Qy
Output Skew
RMS Phase Jitter
nQ0, nQ1
nQ0, nQ1
80%
Q0, Q1
80%
t PW
VSW I N G
Q0, Q1
t
20%
20%
tR
tF
odc =
PERIOD
t PW
x 100%
t PERIOD
Output Rise/Fall Time
©2016 Integrated Device Technology, Inc.
Output Duty Cycle/Pulse Width/Period
9
Revision B, November 11, 2016
845252 Datasheet
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 845252 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. VDD and VDDA should be individually connected
to the power supply plane through vias, and 0.01µF bypass
capacitors should be used for each pin. Figure 1 illustrates this for a
generic VDD pin and also shows that VDDA requires that an
additional 10 resistor along with a 10F bypass capacitor be
connected to the VDDA pin.
3.3V or 2.5V
VDD
.01µF
10Ω
.01µF
10µF
VDDA
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
CML Outputs
All control pins have internal pullups and pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
All unused CML outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
REF_CLK Input
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1k resistor can be tied from the REF_CLK to ground.
©2016 Integrated Device Technology, Inc.
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Revision B, November 11, 2016
845252 Datasheet
Crystal Input Interface
The 845252 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
determined using a 25MHz, 18pF parallel resonant crystal and were
chosen to minimize the ppm error.
XTAL_IN
C1
27pF
X1
18pF Parallel Crystal
XTAL_OUT
C2
27pF
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The input
edge rate can be as slow as 10ns. For LVCMOS signals, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
VDD
the transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done in
one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50 applications, R1 and R2
can be 100. This can also be accomplished by removing R1 and
making R2 50. By overdriving the crystal oscillator, the device will
be functional, but note, the device performance is guaranteed by
using a quartz crystal.
VDD
R1
Ro
Rs
0.1µf
50Ω
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
©2016 Integrated Device Technology, Inc.
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Revision B, November 11, 2016
845252 Datasheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 4. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be
taken to eliminate any solder voids between the exposed heat slug
and the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, please refer to the
Application Note on the Surface Mount Assembly of Amkor’s
Thermally/Electrically Enhance Leadframe Base Package, Amkor
Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
©2016 Integrated Device Technology, Inc.
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Revision B, November 11, 2016
845252 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 845252.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 845252 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VDD_MAX * (IDD + IDDA) = 3.465V * (88mA + 12mA) = 346.5mW
•
Power (outputs)MAX = 35.76mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 35.76mW = 71.52mW
Total Power_MAX (3.465V, with all outputs switching) = 346.5mW + 71.52mW = 418.02mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 43.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.418W * 43.4°C/W = 103°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
©2016 Integrated Device Technology, Inc.
0
1
2.5
43.4°C/W
37.9°C/W
34.0°C/W
13
Revision B, November 11, 2016
845252 Datasheet
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the CML driver output pair. The CML output circuit and termination are
shown in Figure 5.
VDD
RL1
50
RL2
50
Q
nQ
Q1
Q2
V_output
I_load
IC
Figure 5. CML Driver (without built-in 50 pullup) Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations:
Power dissipation when the output driver is logic LOW:
Pd_L = I Load * V Output
= (VOUT_MAX /RL) * (VDD_MAX – VOUT_MAX)
= (600mV/50) * (3.465V – 600mV)
= 34.38mW
Power dissipation when the output driver is logic HIGH:
Pd_H = I Load * V Output
= (0.02V/50) * (3.465V – 0.02V)
= 1.38mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 35.76mW
©2016 Integrated Device Technology, Inc.
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Revision B, November 11, 2016
845252 Datasheet
Reliability Information
Table 8. JA vs. Air Flow Table for a 32 VFQFN
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
43.4°C/W
37.9°C/W
34.0°C/W
Transistor Count
The transistor count for the 845252 is: 3064
Package Outline and Package Dimensions
Package Outline - K Suffix for VFQFN Packages
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
A3
N
To p View
Anvil
Anvil
Singulation
Singula tion
or
OR
Sawn
Singulation
L
N
e (Ty p.)
2 If N & N
1
are Even
2
E2
(N -1)x e
(Re f.)
E2
2
b
A
(Ref.)
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
e
D2
2
N &N
Odd
0. 08
C
Th er mal
Ba se
D2
C
Table 9. Package Dimensions
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pin-out are shown on the front page. The
package dimensions are in Table 9.
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.25
0.30
8
ND & NE
D&E
5.00 Basic
D2 & E2
3.0
3.3
e
0.50 Basic
L
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
©2016 Integrated Device Technology, Inc.
15
Revision B, November 11, 2016
Table 10. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
845252AKILF
ICS45252AIL
Lead-Free, 32 Lead VFQFN
Tray
-40C to 85C
845252AKILFT
ICS45252AIL
Lead-Free, 32 Lead VFQFN
Tape & Reel
-40C to 85C
Revision History Sheet
Rev
Table
1
A
B
Page
T10
16
Description of Change
Date
Product Discontinuation Notice - Last time buy expires November 2, 2016.
PDN# CQ-15-05
11/6/15
Obsolete datasheet per PDN# CQ-15-05.
Ordering Information table - deleted Tape & Reel count and table note.
Updated datasheet header/footer.
11/11/16
Corporate Headquarters
Sales
Tech Support
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www.IDT.com
1-800-345-7015 or 408-284-8200
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