849S625
Crystal-to-LVPECL/LVDS
Clock Synthesizer
Data Sheet
General Description
Features
The 849S625 is a high frequency clock generator. The 849S625
uses an external 25MHz crystal to synthesize 625MHz, 312.5MHz,
156.25MHz and 125MHz clocks. The 849S625 has excellent
cycle-to-cycle and RMS phase jitter performance.
•
•
Ten selectable differential LVPECL or LVDS outputs
•
•
•
Crystal interface designed for a 25MHz, parallel resonant crystal
•
•
•
•
Output duty cycle: 53% (maximum)
The 849S625 operates at full 3.3V supply mode and is available in a
fully RoHS compliant 48-lead TQFP, E-Pad package.
Output frequencies of 625MHz, 312.5MHz, 156.25MHz or
125MHz using a 25MHz crystal.
Cycle-to-cycle jitter: 25ps (maximum)
RMS phase jitter at 156.25MHz (1MHz - 20MHz):
0.375ps (typical), LVDS outputs
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packaging
Frequency Table for Bank A, B and C Outputs
Crystal Frequency (MHz)
M Feedback Divider
VCO Frequency (MHz)
Nx Output Divider
Output Frequency (MHz)
25
25
625
1
625
25
25
625
2
312.5
25
25
625
4
156.25
25
25
625
5
125
VCCO
nQC1
SELB1
VEE
ICS849S625I
QA1
nQA1
QA2
nQA2
VCCO
VEE
QA3
nQA3
QA4
nQA4
QA5
nQA5
VCCO
OEB
OEC
SELB0
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
5
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
QC1
nQC0
QC0
nc
VCCO
nQB1
QB1
nQB0
QB0
XTAL_IN
XTAL_OUT
VEE
SELC0
SELC1
OEA
VCC
VCCO
VCC
REF_CLK
VEE
BYPASS
MR
SEL_OUT
SELA0
SELA1
VCCA
QA0
nQA0
Pin Assignment
48 Lead TQFP, E-Pad
7mm x 7mm x 1.0mm package body
Y Package
Top View
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849S625 Data Sheet
Block Diagram
SEL_OUT
OEA
Pulldown
Pullup
SELA[1:0]
Pulldown
BYPASS
Pulldown
REF_CLK
Pulldown
2
1
÷2
NA =
XTAL_IN
25MHz
Phase
Detector
OSC
VCO
÷1, ÷2,
575MHz - 630MHz
÷4, ÷5
0
6
QA[0:5]
6
nQA[0:5]
NB =
÷1, ÷2,
÷4, ÷5
2
QB[0:1]
2
nQB[0:1]
NC =
÷1, ÷2,
÷4, ÷5
2
XTAL_OUT
M = ÷25
MR
OEB
SELB[0:1]
SELC[0:1]
OEC
Pulldown
Pullup
Pulldown
Pulldown
2
2
QC[0:1]
nQC[0:1]
2
Pullup
©2015 Integrated Device Technology, Inc
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December 2, 2015
849S625 Data Sheet
Table 1. Pin Descriptions
Number
Name
Type
Description
1,
2
XTAL_IN
XTAL_OUT
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
3, 12, 31, 46
VEE
Power
Negative supply pins.
4,
5
SELC0,
SELC1
Input
Pulldown
6
OEA
Input
Pullup
Active high output enable. When logic HIGH, Bank A outputs are enabled and
active. When logic LOW, the outputs are disabled and forced to HIGH/LOW.
LVCMOS/LVTTL interface levels.
7, 48
VCC
Power
Core supply pins.
Selects the output divider value. See Table 3D.
LVCMOS/LVTTL interface levels.
8
OEB
Input
Pullup
Active high output enable. When logic HIGH, Bank B outputs are enabled and
active. When logic LOW, the outputs are disabled and forced to HIGH/LOW.
LVCMOS/LVTTL interface levels.
9
OEC
Input
Pullup
Active high output enable. When logic HIGH, Bank C outputs are enabled and
active. When logic LOW, the outputs are disabled and forced to HIGH/LOW.
LVCMOS/LVTTL interface levels.
10,
11
SELB0,
SELB1
Input
Pulldown
13, 19, 24,
32, 37
VCCO
Power
Output supply pins.
14, 15
nQC1, QC1
Output
Differential output pair. LVPECL or LVDS interface levels.
16, 17
nQC0, QC0
Output
Differential output pair. LVPECL or LVDS interface levels.
18
nc
Unused
No connect.
20, 21
nQB1, QB1
Output
Differential output pair. LVPECL or LVDS interface levels.
22, 23
nQB0, QB0
Output
Differential output pair. LVPECL or LVDS interface levels.
25, 26
nQA5, QA5
Output
Differential output pair. LVPECL or LVDS interface levels.
27, 28
nQA4, QA4
Output
Differential output pair. LVPECL or LVDS interface levels.
29, 30
nQA3, QA3
Output
Differential output pair. LVPECL or LVDS interface levels.
33, 34
nQA2, QA2
Output
Differential output pair. LVPECL or LVDS interface levels.
35, 36
nQA1, QA1
Output
Differential output pair. LVPECL or LVDS interface levels.
38, 39
nQA0, QA0
Output
Differential output pair. LVPECL or LVDS interface levels.
40
VCCA
Power
Analog supply pin.
41,
42
SELA1,
SELA0
Input
Pulldown
Selects the output divider value. See Table 3B.
LVCMOS/LVTTL interface levels.
43
SEL_OUT
Input
Pulldown
Selects between either LVDS or LVPECL output levels. See Table 3A.
LVCMOS/LVTTL interface levels.
44
MR
Input
Pulldown
Master Reset. LVCMOS/LVTTL interface levels.
45
BYPASS
Input
Pulldown
PLL BYPASS mode select pin. See Table 3F.
LVCMOS/LVTTL interface levels.
47
REF_CLK
Input
Pulldown
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Selects the output divider value. See Table 3C.
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulludown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2015 Integrated Device Technology, Inc
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849S625 Data Sheet
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
2
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
Function Tables
Table 3A. SEL_OUT Function Table
Table 3E. MR Function Table
Input
Input
SEL_OUT
Output Levels
MR
Device Function
0 (default)
LVDS
0 (default)
Normal
1
LVPECL
1
Master Reset
Table 3B. SELA Function Table
Inputs
Table 3F. BYPASS Function Table
SELA0
SELA1
NA
Bank A Output Divider
0 (default)
0 (default)
÷1
0
1
÷2
1
0
÷4
1
1
÷5
Input
BYPASS
Device Function
0 (default)
PLL mode. The output frequency is the VCO
frequency divided by the selected output divider.
1
Bypass mode. The output frequency is the
REF_CLK frequency divided by two and then
divided by the selected output divider.
Table 3C. SELB Function Table
Inputs
SELB0
SELB1
NB
Bank B Output Divider
0 (default)
0 (default)
÷1
0
1
÷2
1
0
÷4
1
1
÷5
Table 3D. SELC Function Table
Inputs
SELC0
SELC1
NC
Bank C Output Divider
0 (default)
0 (default)
÷1
0
1
÷2
1
0
÷4
1
1
÷5
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849S625 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
XTAL_IN
Other Inputs
0V to VCC
-0.5V to VCC + 0.5V
Outputs, LVPECL IO
Continuos Current
Surge Current
50mA
100mA
Outputs, LVDS IO
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, JA
33.1C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics, VCC = VCCO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VCC – 0.16
3.3
VCC
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
ICC
Power Supply Current
107
mA
ICCA
Analog Supply Current
16
mA
ICCO
Output Supply Current
228
mA
NOTE: Outputs configured as LVDS (SEL_OUT = 0).
NOTE: For the Power Supply Voltage Sequence Information, see Applications Information section.
Table 4B. LVPECL Power Supply DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VCC – 0.16
3.3
VCC
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
181
mA
ICCA
Analog Supply Current
16
mA
NOTE: Outputs configured as LVPECL (SEL_OUT = 1).
NOTE: For the Power Supply Voltage Sequence Information, see Applications Information section.
©2015 Integrated Device Technology, Inc
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849S625 Data Sheet
Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
VIH
Input High Voltage
VCC = 3.3V
VIL
Input Low Voltage
VCC = 3.3V
IIH
Input
High
Current
IIL
Input
Low Current
Typical
Maximum
Units
2.2
VCC + 0.3
V
-0.3
0.8
V
REF_CLK, BYPASS, MR,
SELA[1:0], SELB[1:0],
SELC[1:0], SEL_OUT
VCC = VIN = 3.465V
150
µA
OEA, OEB, OEC
VCC = VIN = 3.465V
10
µA
REF_CLK, BYPASS, MR,
SELA[1:0], SELB[1:0],
SELC[1:0], SEL_OUT
VCC = 3.465V, VIN = 0V
-10
µA
OEA, OEB, OEC
VCC = 3.465V, VIN = 0V
-150
µA
Table 4D. LVPECL DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VOH
Output High Voltage
VOL
Output Low Voltage
VSWING
Peak-to-Peak
Output Voltage Swing
Test Conditions
Minimum
Typical
Maximum
Units
VCCO – 1.2
VCCO – 0.7
V
VCCO – 2.0
VCCO – 1.5
V
0.6
1.0
V
Maximum
Units
475
mV
50
mV
1.375
V
50
mV
Table 4E. LVDS DC Characteristics, VCC = VCCO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VOD
Differential Output Voltage
VOD
VOD Magnitude Change
VOS
Offset Voltage
VOS
VOS Magnitude Change
©2015 Integrated Device Technology, Inc
Test Conditions
Minimum
268
1.125
6
Typical
December 2, 2015
849S625 Data Sheet
AC Electrical Characteristics
Table 5A. LVPECL AC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
fOUT
tjit(Ø)
Parameter
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 2
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
tLOCK
PLL Lock Time
Test Conditions
Minimum
Typical
Maximum
Units
Qx = ÷1
575
625
630
MHz
Qx = ÷2
287.5
312.5
315
MHz
Qx = ÷4
143.75
156.25
157.5
MHz
Qx = ÷5
115
125
126
MHz
156.25MHz, Integration Range:
(1MHz – 20MHz)
0.373
0.422
ps
156.25MHz, Integration Range:
(12kHz – 20MHz)
0.694
1.04
ps
25
ps
180
350
ps
53
%
130
ms
10% to 90%
65
47
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Outputs configured as LVPECL (SEL_OUT = 1).
NOTE 1: Refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. LVDS AC Characteristics, VCC = VCCO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
fOUT
tjit(Ø)
Parameter
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 2
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
tLOCK
PLL Lock Time
Test Conditions
Minimum
Typical
Maximum
Units
Qx = ÷1
575
625
630
MHz
Qx = ÷2
287.5
312.5
315
MHz
Qx = ÷4
143.75
156.25
157.5
MHz
Qx = ÷5
115
125
126
MHz
156.25MHz, Integration Range:
(1MHz – 20MHz)
0.375
0.413
ps
156.25MHz, Integration Range:
(12kHz – 20MHz)
0.712
1.26
ps
20
ps
190
350
ps
53
%
130
ms
10% to 90%
65
47
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Outputs configured as LVDS (SEL_OUT = 0).
NOTE 1: Refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
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849S625 Data Sheet
Typical Phase Noise at 156.25MHz (LVPECL)
Noise Power
dBc
Hz
156.25MHz
RMS Phase Jitter (Random)
1MHz to 20MHz = 0.373ps (typical)
Offset Frequency (Hz)
Typical Phase Noise at 156.25MHz (LVPECL)
Noise Power
dBc
Hz
156.25MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.694ps (typical)
Offset Frequency (Hz)
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849S625 Data Sheet
Typical Phase Noise at 156.25MHz (LVDS)
Noise Power
dBc
Hz
156.25MHz
RMS Phase Jitter (Random)
1MHz to 20MHz = 0.375ps (typical)
Offset Frequency (Hz)
Typical Phase Noise at 156.25MHz (LVDS)
Noise Power
dBc
Hz
156.25MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.712ps (typical)
Offset Frequency (Hz)
©2015 Integrated Device Technology, Inc
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December 2, 2015
849S625 Data Sheet
Parameter Measurement Information
2V
2V
VCC,
VCCO
3.3V ±5%
VCC,
VCCO
VCCA
VCCA
-1.3V±0.165V
LVDS Output Load AC Test Circuit
LVPECL Output Load AC Test Circuit
nQAx,
nQBx,
nQCx
QAx,
QBx,
QCx
tcycle n
tcycle n+1
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
Cycle-to-Cycle Jitter
RMS Phase Jitter
nQAx,
nQBx,
nQCx
nQAx,
nQBx,
nQCx
90%
QAx,
QBx,
QCx
90%
90%
VSW I N G
QAx,
QBx,
QCx
10%
10%
tR
tF
VOD
10%
10%
tR
tF
LVDS Output Rise/Fall Time
LVPECL Output Rise/Fall Time
©2015 Integrated Device Technology, Inc
90%
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December 2, 2015
849S625 Data Sheet
Parameter Measurement Information, continued
nQAx, nQBx, nQCx
QAx, QBx, QCx
Output Duty Cycle/Pulse Width/Period
Offset Voltage Setup
Differential Output Voltage Setup
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849S625 Data Sheet
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
REF_CLK Input
LVPECL Outputs
For applications not requiring the use of the reference clock, it can be
left floating. Though not required, but for additional protection, a 1k
resistor can be tied from the REF_CLK to ground.
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Crystal Inputs
LVDS Outputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Table 6. Recommended Crystal Specifications
Symbol
Parameter
Value
Crystal Cut
Fundamental at Cut
Resonance
Parallel Resonance
fT
Frequency Tolerance
±25ppm at 250C
fS
Frequency Stability
±25ppm over -400C to +850C
CL
Load Capacitance
18pF
CO
Shunt Capacitance
5pF - 7pF
ESR
Equivalent Series Resistance
20 - 50
Aging @ 25
0C
±15ppm/10 Years Maximum
NOTE: External tuning capacitors must be used for proper operation.
Power Supply Voltage Sequence Information
No power sequence restrictions apply if VCC and VCCA are supplied
by the same power plane and the recommended VCCA filter is used (
see Figure 6). VCCO may be applied at any time before or after VCC
©2015 Integrated Device Technology, Inc
and VCCA are applied. If VCC and VCCA are not supplied by the same
power plane, VCCA must be powered on before or at the same time
VCC is applied. The VCCO supply voltage may be applied at any time.
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December 2, 2015
849S625 Data Sheet
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 1A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100. This can also be
accomplished by removing R1 and making R2 50. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
3.3V
3.3V
R1
100
Ro ~ 7 Ohm
C1
Zo = 50 Ohm
XTAL_IN
RS
43
R2
100
Driv er_LVCMOS
0.1uF
XTAL_OUT
Cry stal Input Interf ace
Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface
VCC=3.3V
C1
Zo = 50 Ohm
XTAL_IN
R1
50
Zo = 50 Ohm
0.1uF
XTAL_OUT
LVPECL
Cry stal Input Interf ace
R2
50
R3
50
Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface
©2015 Integrated Device Technology, Inc
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December 2, 2015
849S625 Data Sheet
LVDS Driver Termination
A general LVDS interface is shown in Figure 2. Standard termination
for LVDS type output structure requires both a 100 parallel resistor
at the receiver and a 100 differential transmission line environment.
In order to avoid any transmission line reflection issues, the 100
resistor must be placed as close to the receiver as possible. IDT
offers a full line of LVDS compliant devices with two types of output
structures: current source and voltage source. The standard
termination schematic as shown in Figure 2 can be used with either
type of output structure. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output is a current
source or a voltage source type structure. In addition, since these
outputs are LVDS compatible, the input receivers amplitude and
common mode input range should be verified for compatibility with
the output.
+
LVDS Driver
LVDS
Receiver
100Ω
–
100Ω Differential Transmission Line
Figure 2. Typical LVDS Driver Termination
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
Figure 3A. 3.3V LVPECL Output Termination
©2015 Integrated Device Technology, Inc
R2
84
Figure 3B. 3.3V LVPECL Output Termination
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December 2, 2015
849S625 Data Sheet
EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 4. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, refer to the Application Note
on the Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
SOLDER
PIN
PIN PAD
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
PIN
LAND PATTERN
(GROUND PAD)
SOLDER
PIN PAD
Figure 4. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
©2015 Integrated Device Technology, Inc
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December 2, 2015
849S625 Data Sheet
Application Schematic Example
Figure 5 shows an example of 849S625 application schematic. In this example, the device is operated at VCC = VCCA = VCCO = 3.3V. An 18pF
parallel resonant 25MHz crystal is used. The load capacitance C1 = 27pF and C2 = 27pF are recommended for frequency accuracy. Depending
on the parasitics of the printed circuit board layout, these values might required slight adjustment to optimize the frequency accuracy. Crystals
with other load capacitance specifications can be used. This will require adjusting C1 and C2. For this device, the crystal load capacitors are
required for proper operation.
As with any high speed analog circuitry, the power supply pins are vulnerable to noise. To achieve optimum jitter performance, power supply
isolation is required. The 849S625 provides separate power supplies to isolate from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB
as close to the power pins as possible. If space is limited, the 0.1uF capacitor in each power pin filter should be placed on the device side of
the PCB and the other components can be placed on the opposite side.
Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter
performance is designed for wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific
frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and
if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk
capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables
in the datasheet to ensure the logic control inputs are properly set.
VCC O
VCC
Z o_dif f = 100 ohm
VCC
C1
C2
C3
C4
C5
C6
C7
R1
0.01u
0. 01u
0.01u
0.01u
0. 01u
0.01u
0.01u
100
+
R2
10
VCC A
41
42
SELB0
SELB1
10
11
SELC0
SELC1
4
5
O EA
O EB
O EC
6
8
9
1
X1
CL=18pF
2
C1
3
12
31
46
VEE
VEE
VEE
VEE
7
48
VCC
VCC
VCC O
VCCO
VC CO
VC CO
VCC O
SELA0
SELA1
40
U1
13
19
24
32
37
LVDS
Termination
SELA0
SELA1
SELB0
SELB1
SELC0
SELC1
O EA
O EB
O EC
Q A0
nQ A0
Q A1
nQ A1
Q A2
nQ A2
Q A3
nQ A3
Q A4
nQ A4
Q A5
nQ A5
Q B0
nQ B0
Q B1
nQ B1
XTAL_IN
SEL_OU T
MR
BYPASS
REF _CLK
NC
Tuning
capacitor
required
C 10
0. 01u
VC CA
C 11
10uF
XTAL_OU T
25MHz
Q A0
nQ A
Q A1
nQ A1
Q A2
nQ A2
Q A3
nQ A3
Q A4
nQ A4
Q A5
nQ A5
23
22
21
20
Q B0
nQ B0
Q B1
nQ B1
17
16
15
14
Q C0
nQ C0
Q C1
nQ C1
3. 3V
R4
133
R3
133
Z o = 50 O hm
+
Z o = 50 O hm
-
LVPECL
Termination
R5
82.5
R6
82.5
43
44
45
47
18
27pF
QC 0
nQC 0
QC 1
nQC 1
39
38
36
35
34
33
30
29
28
27
26
25
I CS849S625I
C2
SEL_O UT
nR ESET
PLL_BY PASS
27pF
R7
1K
Z o = 50 O hm
Logic Control Input Examples
+
3.3V
BLM18BB221SN 1
Set Logic
Input to '1'
VC C
Z o = 50 O hm
Set Logic
Input to '0'
VCC
1
2
Fer rite Bead
R U1
1K
C 12
0. 1uF
R U2
N ot Install
To Logic
Input
pins
R D1
N ot I nstall
To Logic
Input
pins
VCC
C13
10uF
3.3V
-
C14
0.1uF
BLM18BB221SN 2
1
R D2
1K
2
Fer rite Bead
C 15
0. 1uF
LVPECL
Optional
Y-Termination
R8
R9
50
50
R 10
50
VC CO
C16
C17
10uF
0.1uF
Figure 5. 849S625 Application Schematic
©2015 Integrated Device Technology, Inc
16
December 2, 2015
849S625 Data Sheet
LVPECL Power Considerations
This section provides information on power dissipation and junction temperature for the 849S625.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 849S625 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
The maximum current at 85°C is as follows:
IEE_MAX = 170mA
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 170mA = 589.05mW
•
Power (outputs)MAX = 33.2mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 33.2mW = 332mW
Total Power_MAX (3.465V, with all outputs switching) = 589.05mW + 332mW = 921.05mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 33.1°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.921W * 33.1°C/W = 115.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 48 Lead TQFP, E-Pad, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
©2015 Integrated Device Technology, Inc
0
1
2.5
33.1°C/W
27.2°C/W
25.7°C/W
17
December 2, 2015
849S625 Data Sheet
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCCO – 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.7V
(VCCO_MAX – VOH_MAX) = 0.7V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.5V
(VCCO_MAX – VOL_MAX) = 1.5V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.7V)/50] * 0.7V = 18.2mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.5V)/50] * 1.5V = 15mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 33.2mW
©2015 Integrated Device Technology, Inc
18
December 2, 2015
849S625 Data Sheet
LVDS Power Considerations
This section provides information on power dissipation and junction temperature for the 849S625.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 849S625 is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
The maximum current at 85°C is as follows:
ICC_MAX = 100mA
ICCA_MAX = 15mA
ICCO_MAX = 212mA
•
Power (core)MAX = VCC_MAX * (ICC_MAX + ICCA_MAX) = 3.465V * (100mA + 15mA) = 398.475mW
•
Power (outputs)MAX = VCCO_MAX * ICCO_MAX = 3.465V * 212mA = 734.58mW
Total Power_MAX = 398.475mW + 734.58mW = 1133.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 33.1°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.133W * 33.1°C/W = 122.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 8. Thermal Resistance JA for 48 Lead TQFP, E-Pad, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
©2015 Integrated Device Technology, Inc
0
1
2.5
33.1°C/W
27.2°C/W
25.7°C/W
19
December 2, 2015
849S625 Data Sheet
Reliability Information
Table 9. JA vs. Air Flow Table for a 48 Lead TQFP, E-Pad
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
33.1°C/W
27.2°C/W
25.7°C/W
Transistor Count
The transistor count for 849S625 is: 3696
©2015 Integrated Device Technology, Inc
20
December 2, 2015
849S625 Data Sheet
Package Outline and Package Dimensions
Package Outline - Y Suffix for 48 Lead TQFP, E-Pad
-HD VERSION
EXPOSED PAD DOWN
0.20 TAB
-TAB, EXPOSED PART OF CONNECTION BAR OR TIE BAR
Table 10. Package Dimensions for 48 Lead TQFP, E-Pad
Symbol
N
A
A1
A2
b
c
D&E
D1 & E1
D2 & E2
D3 & E3
e
L
JEDEC Variation: BBC - HD
All Dimensions in Millimeters
Minimum
Nominal
48
0.05
0.95
0.17
0.09
0.45
0°
0.10
1.00
0.22
9.00 Basic
7.00 Basic
5.50 Ref.
3.5
0.5 Basic
0.60
Maximum
1.20
0.15
1.05
0.27
0.20
0.75
7°
Reference Document: JEDEC Publication 95, MS-026
©2015 Integrated Device Technology, Inc
21
December 2, 2015
849S625 Data Sheet
Ordering Information
Table 11. Ordering Information
Part/Order Number
849S625BYILF
849S625BYILFT
Marking
ICS49S625BIL
ICS49S625BIL
©2015 Integrated Device Technology, Inc
Package
“Lead-Free” 48 Lead TQFP, E-Pad
“Lead-Free” 48 Lead TQFP, E-Pad
22
Shipping Packaging
Tray
Tape & Reel
Temperature
-40C to 85C
-40C to 85C
December 2, 2015
849S625 Data Sheet
Revision History Sheet
Rev
A
Table
Page
Description of Change
T4E
6
VOD: changed units from V to mV
T11
22
Deleted quantity from Tape &Rreel. Deleted Lead-Free note.
©2015 Integrated Device Technology, Inc
Date
23
10/1/12
December 2, 2015
849S625 Data Sheet
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