8533AG-01LFT

8533-01 Low Skew, 1-to-4 Differential-to-3.3V LVPECL Fanout Buffer GENERAL DESCRIPTION FEATURES The 8533-01 is a low skew, high performance 1-to-4 Differential-to-3.3V LVPECL Fanout Buffer. The 853301 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8533-01 ideal for those applications demanding well defined performance and repeatability. • Four differential 3.3V LVPECL outputs Data Sheet • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum output frequency: 650MHz • Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input • Output skew: 30ps (maximum) • Part-to-part skew: 150ps (maximum) • Propagation delay: 1.4ns (maximum) • Additive phase jitter, RMS: 0.06ps (typical) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Lead-Free package • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT 8533-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View ©2016 Integrated Device Technology, Inc 1 Revision F January 19, 2016 8533-01 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name 1 VEE Power Type 2 CLK_EN Input 3 CLK_SEL Input 4 CLK Input 5 nCLK Input 6 PCLK Input 7 nPCLK Input Description Negative supply pin. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects differential PCLK, nPCLK inputs. Pulldown When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. Pullup Pulldown Non-inverting differential clock input. Pullup Inverting differential clock input. Pulldown Non-inverting differential LVPECL clock input. Pullup Inverting differential LVPECL clock input. 8, 9 nc Unused 10, 13, 18 VCC Power No connect. Positive supply pins. 11, 12 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 14, 15 nQ2, Q2 Output Differential output pair. LVPECL interface levels. 16, 17 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 19, 20 nQ0, Q0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ©2016 Integrated Device Technology, Inc 2 Revision F January 19, 2016 8533-01 Data Sheet TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs Outputs CLK_EN CLK_SEL Selected Source Q0:Q3 nQ0:nQ3 0 0 CLK, nCLK Disabled; LOW Disabled; HIGH 0 1 PCLK, nPCLK Disabled; LOW Disabled; HIGH 1 0 CLK, nCLK Enabled Enabled 1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described in Table 3B. FIGURE 1. CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs CLK or PCLK nCLK or nPCLK 0 1 Input to Output Mode Polarity HIGH Differential to Differential Non Inverting LOW Differential to Differential Non Inverting HIGH Single Ended to Differential Non Inverting Q0:Q3 nQ0:nQ3 1 LOW 0 HIGH 0 Biased; NOTE 1 LOW 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inverting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inverting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inverting NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”. ©2016 Integrated Device Technology, Inc 3 Revision F January 19, 2016 8533-01 Data Sheet ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VCC Positive Supply Voltage Test Conditions IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 50 mA Maximum Units TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage 2 VEE + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current 5 µA 150 µA IIL Input Low Current Test Conditions CLK_EN Minimum Typical VIN = VCC = 3.465V CLK_SEL VIN = VCC = 3.465V CLK_EN VIN = 0V, VCC = 3.465V -150 µA CLK_SEL VIN = 0V, VCC = 3.465V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol IIH Parameter Input High Current Test Conditions nCLK Minimum Typical VCC = VIN = 3.465V Maximum 5 µA CLK VCC = VIN = 3.465V nCLK VCC = 3.465V, VIN = 0V -150 µA CLK VCC = 3.465V, VIN = 0V -5 µA IIL Input Low Current VPP Peak-to-Peak Input Voltage 150 Units 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH. ©2016 Integrated Device Technology, Inc 4 µA 1.3 V VCC - 0.85 V Revision F January 19, 2016 8533-01 Data Sheet TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol IIH IIL Parameter Input High Current Input Low Current Test Conditions PCLK Minimum Typical VCC = VIN = 3.465V Maximum Units 150 µA nPCLK VCC = VIN = 3.465V PCLK VCC = 3.465V, VIN = 0V -5 µA nPCLK VCC = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Input Voltage VCMR Common Mode Input Voltage; NOTE 1, 2 5 µA 0.3 1 V VEE + 1.5 VCC V VOH Output High Voltage; NOTE 3 VCC - 1.4 VCC - 0.9 V VOL Output Low Voltage; NOTE 3 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Maximum Units 650 MHz NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications the maximum input voltage for PCLK and nPCLK is VCC + 0.3V. NOTE 3: Outputs terminated with 50Ω to VCC - 2V. TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency Test Conditions tPD Propagation Delay; NOTE 1 1.4 ns tsk(o) Output Skew; NOTE 2, 4 30 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 150 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 tR / t F Output Rise/Fall Time odc Output Duty Cycle ƒ ≤ 650MHz Minimum Typical 1.0 0.06 20% to 80% @ 50MHz ps 300 700 ps 47 53 % All parameters measured at 500MHz unless noted otherwise. The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Driving only one input clock. ©2016 Integrated Device Technology, Inc 5 Revision F January 19, 2016 8533-01 Data Sheet ADDITIVE PHASE JITTER 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 0 -10 Input/Output Additive Phase Jitter at 156.25MHz = 0.06ps (typical) -20 -30 -40 SSB PHASE NOISE dBc/HZ -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The ©2016 Integrated Device Technology, Inc 6 Revision F January 19, 2016 8533-01 Data Sheet PARAMETER MEASUREMENT INFORMATION 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL OUTPUT SKEW PROPAGATION DELAY OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD ©2016 Integrated Device Technology, Inc 7 Revision F January 19, 2016 8533-01 Data Sheet APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT TERMINATION FOR LVPECL OUTPUTS drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to FIGURE 3A. LVPECL OUTPUT TERMINATION ©2016 Integrated Device Technology, Inc FIGURE 3B. LVPECL OUTPUT TERMINATION 8 Revision F January 19, 2016 8533-01 Data Sheet DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 4A. CLK/NCLK INPUT DRIVEN BY LVHSTL DRIVER FIGURE 4B. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm Zo = 50 Ohm LVDS_Driv er CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 4C. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 4D. CLK/NCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 4E. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE ©2016 Integrated Device Technology, Inc 9 Revision F January 19, 2016 8533-01 Data Sheet LVPECL CLOCK INPUT INTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5F show interface examples for the PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 3.3V 3.3V 3.3V R1 50 CML R2 50 Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK FIGURE 5A. PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER FIGURE 5B. PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 3.3V LVPECL Zo = 50 Ohm Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK PCLK Zo = 50 Ohm nPCLK nPCLK LVPECL R1 84 HiPerClockS Input R5 100 - 200 R2 84 FIGURE 5C. PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER R6 100 - 200 R1 125 FIGURE 5D. PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 2.5V 3.3V 3.3V 3.3V 2.5V R3 120 SSTL 3.3V R4 120 Zo = 50 Ohm Zo = 60 Ohm C1 LVDS R3 1K R4 1K PCLK PCLK R5 100 Zo = 60 Ohm nPCLK R1 120 HiPerClockS PCLK/nPCLK C2 nPCLK Zo = 50 Ohm R2 120 FIGURE 5E. PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER ©2016 Integrated Device Technology, Inc HiPerClockS PCLK/nPCLK R2 125 R1 1K HiPerClockS PCLK/nPCLK R2 1K FIGURE 5F. PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 10 Revision F January 19, 2016 8533-01 Data Sheet POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 8533-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 8533-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 50mA = 173.3mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power_MAX (3.465V, with all outputs switching) = 173.3mW + 120mW = 293.3mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.293W * 66.6°C/W = 89.5°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 73.2°C/W 200 500 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. ©2016 Integrated Device Technology, Inc 11 Revision F January 19, 2016 8533-01 Data Sheet 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCC- 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (VCC_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) = [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) = [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ©2016 Integrated Device Technology, Inc 12 Revision F January 19, 2016 8533-01 Data Sheet RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 73.2°C/W 200 500 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for 8533-01 is: 404 ©2016 Integrated Device Technology, Inc 13 Revision F January 19, 2016 8533-01 Data Sheet PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N Maximum 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MS-153 ©2016 Integrated Device Technology, Inc 14 Revision F January 19, 2016 8533-01 Data Sheet TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 8533AG-01LN ICS8533A01LN 20 lead “Lead Free Annealed” TSSOP Tube 0°C to +70°C 8533AG-01LNT ICS8533A01LN 20 lead “Lead Free Annealed” TSSOP Tape and Reel 0°C to +70°C 8533AG-01LF ICS8533A01LF 20 lead “Lead Free” TSSOP Tube 0°C to +70°C 8533AG-01LFT ICS8533A01LF 20 lead “Lead Free” TSSOP Tape and Reel 0°C to +70°C ©2016 Integrated Device Technology, Inc 15 Revision F January 19, 2016 8533-01 Data Sheet REVISION HISTORY SHEET Rev B B B C Table Page 4C 4 4D 5 5 5 Description of Change Date VPP values changed from 0.1 Min. to 0.15 Min. VCMR values changed from 0.13 Min., 1.3 Max. to 1.5 Min, VCC Max. Deleted VIH and VIL rows. tR values changed from 100 Min. to 300 Min, and added 700 Max. tF values changed from 100 Min., 600 Max. to 300 Min. to 700 Max. For tR and tF rows changed test conditions from 30% to 70% to 20% to 80%. tjit(cc) values changed 150 Max. to 0 Max. 5/22/01 5 5 Deleted tS and tH rows. 6/4/01 4D 5 VPP values changed from 0.15 Min., 1.3 Max. to 0.3 Min., 1 Max. VCMR values changed from 1.5 Min., to VEE + 1.5 Min. 6/28/01 4B 5 4 5 VIH values changed from 3.765 Max. to VCC + 0.3 Max. Deleted tjit(cc) row. 10/15/01 C 6, 7 Revised Parameter Measurement diagrams. 10/18/01 C 3 Updated Figure 1, CLK_EN Timing Diagram. 11/1/01 C 8 Added Termination for LVPECL Outputs section. 5/28/02 6 Output Load Test Circuit diagram - corrected VEE equation to read, VEE = -1.3V ± 0.165V from VEE = -1.3V ± 0.135V. 10/03/02 1 2 4 5 5 6 8 9 10 Added RMS Jitter to Features section. Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. Changed Outputs Absolute Maximum Rating. LVPECL Table - changed VSWING 0.85V max. to 1.0V max. AC Characteristics Table - added RMS jitter. Added Additive Phase Jitter Section. Updated LVPECL Output Termination diagrams. Added Differential Clock Input Interface. Added LVPECL Clock Input Interface. Updated format throughout data sheet. 10/12/03 T9 15 Added Lead Free Annealed part number to Ordering Information table. 2/9/04 T9 10 15 Updated LVPECL Clock Input Interface section. Ordering Information Table - added Lead Free part number. 6/17/04 T4D 5 LVPECL DC Characteristics Table -corrected VOH max. from VCC - 1.0V to VCC- 0.9V. Power Considerations - corrected power dissipation to reflect VOH max in Table 4D. Ordering Information Table - added lead-free note. Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefix from Part/Order Number column. Added Contact Page. Removed ICS from part numbers where needed. Ordering Information - removed quantity in tape and reel. Deleted LF note below table. Updated header and footer C T2 D D D T4D T5 11 - 12 E F F T9 15 T9 15 17 T9 15 ©2016 Integrated Device Technology, Inc 16 4/12/07 8/4/10 1/19/16 Revision F January 19, 2016 8533-01 Data Sheet Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. 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